Chip testing system, method and device

Abstract

The invention relates to a chip testing system, device and method. The chip test system comprises a server and an embedded test device which are in communication connection. The server is configured to store a test program and load the stored test program to the embedded test device; the embedded test device is configured to run a test program so as to test one or more chips to be tested connected with the embedded test device, and the test program simultaneously tests the computing power load and the memory pressure of the chips to be tested in parallel when running. According to the chip testing system, device and method, the testing efficiency can be remarkably improved, and the real performance of the chip in an actual service scene can be accurately reflected.

Description

Technical Field

[0001] The present invention relates to the field of chip testing and performance screening, and in particular to a chip testing system, method and device. Background Art

[0002] With the widespread application of AI chips in areas such as automotive and smart homes, pre-shipment testing and performance screening have become critical to ensuring chip quality. For example, chip testing typically involves testing the performance of each chip, specifically its computing power, to screen out chips of varying specifications. Due to the large number of chips, accurate and efficient chip testing methods are essential. Summary of the Invention

[0003] The present application provides a chip testing system, a chip testing device and a chip testing method, which can significantly improve the testing efficiency and accurately reflect the actual performance of the chip in actual business scenarios.

[0004] One aspect of the present application provides a chip testing system, comprising a server and an embedded testing device that are communicatively connected, wherein: the server is configured to store a test program and load the stored test program into the embedded testing device; the embedded testing device is configured to run the test program to test one or more chips to be tested connected to the embedded testing device, and the test program simultaneously implements computing load testing and memory stress testing of the chips to be tested in parallel during execution.

[0005] In some embodiments, the embedded test device includes a visual presentation module; the embedded test device is further configured to present the test status and test results of the one or more chips to be tested through the visual presentation module.

[0006] In some embodiments, the chip testing system also includes a client that is communicatively connected to the server and the embedded testing device; the embedded testing device is also configured to: in response to completing the test of one or more chips to be tested, send a test completion signal to the client, and send the test results to the server; the server is also configured to: receive and store the test results; the client is configured to: in response to receiving the test completion signal, query the test results from the server, and present the test results in a visual form on the interactive interface of the client.

[0007] In some embodiments, the client is further configured to: send a test instruction to the embedded test device; the embedded test device is further configured to: based on the test instruction, send a test program acquisition request corresponding to the test instruction to the server; the server is further configured to: based on the test program acquisition request, load the test program corresponding to the test program acquisition request to the embedded test device.

[0008] In some embodiments, the chip testing system includes multiple servers; and the client is further configured to dynamically configure resources of the multiple servers according to a test scenario.

[0009] In some embodiments, the client is further configured to communicate with the server to modify and update the test program according to a test scenario.

[0010] In some embodiments, the embedded testing device is further configured to: run the test program to simultaneously execute the computing load test and the memory stress test through multi-threading or multi-tasking concurrency.

[0011] In some embodiments, the computing power load test includes at least one of the following: verification of various neural network models, verification of different frequencies of neural networks, verification of neural network memory ECC, verification of neural network computing power accuracy, and verification of maximum computing power of specific neural network models; the memory stress test includes at least one of the following: image processing data stream writing, sensor high-frequency data writing, and radar point cloud analysis and calculation.

[0012] Another aspect of the present application provides a chip testing device, comprising: a chip interface configured to be electrically connected to one or more chips to be tested; and a processor configured to run a test program to test the one or more chips to be tested, wherein the test program simultaneously implements computing power load testing and memory stress testing on the chips to be tested in parallel during execution.

[0013] Another aspect of the present application provides a chip testing method, which is performed by an embedded testing device, including: loading a test program corresponding to the chip to be tested and the test scenario electrically connected to the embedded testing device; and running the test program to test the chip to be tested, wherein the test program simultaneously implements computing power load testing and memory stress testing of the chip to be tested in parallel during execution.

[0014] According to the above-mentioned chip testing system, device and method, the embedded test device is only equipped with a minimum system, without the need for long-term storage of test programs, to achieve lightweight management of the embedded test device, and different test programs can be replaced for different chips to be tested and different test scenarios, to achieve the scalability of the embedded test device. When the chip to be tested is tested, by performing computing power load test and memory stress test at the same time, the resource competition in the actual business scene (such as visual recognition and path planning concurrency in autonomous driving) is reproduced, and the more accurate computing power specifications of the chip can be measured. In addition, since computing power load test and memory stress test are performed in parallel, the test time can be shortened and the chip test efficiency can be improved. Thus, the chip testing system of the present application can significantly improve test efficiency and can accurately reflect the true performance of the chip in the actual business scene. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 1 is an architectural diagram of a chip testing system according to an embodiment of the present application;

[0016] Figure 2 1 is an architectural diagram of a chip testing system according to an embodiment of the present application;

[0017] Figure 3 Schematic diagram of chip test results according to an embodiment of the present application;

[0018] Figure 4 A schematic diagram showing statistics of chip test results according to an embodiment of the present application;

[0019] Figure 5 Schematic diagram of a chip testing routine according to an embodiment of the present application;

[0020] Figure 6 Schematic diagram of a test process of a chip test system according to an embodiment of the present application;

[0021] Figure 7 is a structural block diagram of an embedded testing device according to an embodiment of the present application;

[0022] Figure 8 Flowchart of a chip testing method according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] Artificial intelligence chips are digital chips. The computing power specification of artificial intelligence chips is an important indicator for their performance screening. In the field of artificial intelligence chips, TOPS (Tera Operations Per Second) value is the core indicator for measuring the computing power specification of artificial intelligence chips. It represents the chip processor can perform one trillion (10 12) operation. For example, the computing power specifications of autonomous driving chips are usually between 100-1000TOPS. During chip testing and performance screening, the chip's computing power needs to be tested to select chips that meet the predetermined computing power specifications.

[0024] Some technologies, when testing AI chips, only focus on load testing neural network computing power (for example, for neural network model verification), without a comprehensive assessment of memory resource contention. In real-world scenarios, memory is preempted by other services (for example, multi-source data from cameras and sensors), resulting in inflated computing power specifications presented in load testing, making the tested computing power inconsistent with actual business scenarios.

[0025] In other technologies, when testing artificial intelligence chips, only the chip's memory pressure is tested, and for the neural network, only whether the function is normal is verified, which makes it difficult to screen the computing power specifications.

[0026] In addition, due to the large number and variety of chips, different business tests are required for different types of chips, which significantly increases the testing cost and testing cycle.

[0027] The present application provides a chip testing system, device and method, which can significantly improve testing efficiency and accurately reflect the actual performance of the chip in actual business scenarios.

[0028] like Figure 1 As shown, the chip testing system 100 includes a server 120 and an embedded testing device 140. The server 120 and the embedded testing device 140 are communicatively connected, for example, via an Ethernet cable.

[0029] The server 120 is a computer that manages computing resources, including a memory. The server 120 stores test programs in its memory, for example, multiple sets of test programs can be stored, each adapted to different chip architectures and different test scenarios. For example, the first version of the test program is dedicated to the test of the chip of the first manufacturer, and the second version of the test program is dedicated to the test of the chip of the second manufacturer, etc. The test program is a special software for verifying the performance, function and reliability of the chip, and its function is to quantify the chip performance indicators (such as computing power, power consumption, stability) by simulating the execution logic of the real scene. The server 120 can load the stored test program to the embedded test device 140 via the communication connection between the server 120 and the embedded test device 140. The test program can be run by being deployed in the embedded test device 140 without being stored in the embedded test device 140 for a long time.

[0030] The embedded test device 140 provides a physical carrier and a test execution environment for the chip to be tested, and is a hardware device for chip testing. For example, the embedded test device 140 may include one or more chip placement slots 142, each of which may accommodate a chip to be tested. The chip placement slot 142 includes a chip interface. After the chip to be tested is placed in the chip placement slot 142, it is connected to the chip interface, so that the chip to be tested is electrically connected to the embedded test device 140 through its pins. In some examples, such as Figure 1 As shown, the embedded test device 140 may include multiple frames, each frame including one or more chip racks 148, and each chip rack 148 including multiple chip placement slots 142. The chip rack 148 may be in the form of a drawer, which can be pulled out from the embedded test device 140 to facilitate the user to insert / remove chips, and can be inserted into the embedded test device 140 to electrically connect the chips to the embedded test device 140, thereby performing testing on the chips.

[0031] The embedded test device 140 includes a memory, in which a software development kit (SDK) that can start a minimum system and meet the requirements for running the test program is pre-burned (deployed). The SDK can support the correct operation of the test program on the embedded test device 140. The memory is also used to temporarily store the test program loaded from the server 120 for execution. The test program can be loaded into the random access memory in the memory of the embedded test device 140 for short-term storage, without having to be stored in the embedded test device 140 for a long time. The embedded test device 140 includes a processor configured to run the test program loaded from the server 120, execute the preset algorithm in the test program, generate a test load, apply it to one or more chips under test connected to the embedded test device 140 for testing, and collect performance data of the chips under test. It is easy to understand that the one or more chips under test connected to the embedded test device 140 refer to chips that are correctly placed in the chip placement slot 142 and the chip rack 148 is correctly inserted into the embedded test device 140. The embedded test device 140 is a chip testing device that cooperates with software and hardware.

[0032] When running the test program, the embedded test device 140 simultaneously performs a computing load test and a memory stress test on the chip under test. The computing load test involves running a neural network model to simulate neural network inference to calibrate the TOPS value, while the memory stress test is implemented by simulating memory contention in parallel business scenarios. The computing load test and memory stress test are executed in parallel, meaning that they are processed simultaneously within the same time window.

[0033] According to the above-mentioned chip testing system 100, the embedded test device 140 is only equipped with a minimum system, without the need for long-term storage of test programs, thereby realizing lightweight management of the embedded test device 140, and different test programs can be replaced for different chips to be tested and different test scenarios, thereby realizing the scalability of the embedded test device 140. When the chip to be tested is tested, by simultaneously executing computing power load test and memory stress test, the resource competition in the actual business scene (such as visual recognition and path planning concurrency in autonomous driving) is reproduced, and the computing power specification of the chip can be measured more accurately. In addition, since computing power load test and memory stress test are executed in parallel, the test time can be shortened and the chip test efficiency can be improved. Thus, the chip testing system 100 of the present application can significantly improve test efficiency and can accurately reflect the real performance of the chip in the actual business scene.

[0034] In some embodiments, the embedded test device 140 includes a visual presentation module; the embedded test device 140 is further configured to present the test status and test results of the one or more chips to be tested through the visual presentation module.

[0035] In some examples, the visual presentation module includes a first indicator light 143 and a second indicator light 145. In a specific example, each chip placement slot corresponds to a first indicator light 143 and a second indicator light 145, and accordingly, each chip under test corresponds to an indicator light 143 and a second indicator light 145. The first indicator light 143 and the second indicator light 145 can each be an LED light capable of displaying multiple colors. It is easy to understand that the visual presentation module is not limited to this and can be a display provided on the embedded test device 140, etc.

[0036] In this example, the embedded test device 140 runs the test program, and after the test is completed, the first indicator light 143 is lit with a specific color based on the test result, that is, the test result of the chip to be tested corresponding to the first indicator light is presented by the first indicator light 143. For example, each color that the first indicator light 143 can present corresponds to a preset computing power specification interval, such as when the test result is that the computing power specification of the chip is greater than 100TOPS, the first indicator light 143 is lit with yellow light, and when the test result is that the computing power specification of the chip is less than 100TOPS, the first indicator light 143 is lit with blue light. Users (such as testers) can easily classify, collect and ship chips by observing the first indicator light 143. For example, the chip corresponding to the first indicator light 143 lit with yellow light can be classified as a qualified chip, and the chip lit with blue light can be classified as a defective chip. The mapping relationship between different computing power specifications and the different colors lit by the first indicator light 143 can be defined in the test program or the SDK burned in the embedded test device 140. The embedded test device 140 operates the signal pin of the first indicator light 143 by running the test program to light up the first indicator light 143 with a predetermined color.

[0037] The embedded test device 140 runs a test program. During the test, if a specific test state occurs, the second indicator light 145 can be lit with a predetermined color of light. Exemplarily, the test state may include insufficient chip computing power, insufficient memory pressure, or power outage, abnormal SDK startup, abnormal program deployment, etc. during the test. When a specific test state occurs, the second indicator light 145 is lit with a color corresponding to the specific test state. For example, when the chip computing power is insufficient, the second indicator light 145 is lit in red, and when the chip memory pressure is insufficient, the second indicator light is lit in green, etc. The mapping relationship between different test states and the different colors of the second indicator light 145 can be defined in the test program or the SDK burned in the embedded test device 140. The embedded test device 140 operates the signal pin of the second indicator light 145 by running the test program to light the second indicator light 145 with a predetermined color of light.

[0038] In this embodiment, by providing a visual presentation module, the raw test status and test result data can be converted into physical signals, allowing for intuitive presentation of chip computing power specification test results, making it easier to classify, collect, and ship chips. Furthermore, error messages during chip testing can be visually presented, allowing testers to promptly address any anomalies that arise during testing.

[0039] In some embodiments, chip testing system 100 further includes a client 160 communicatively connected to server 120 and embedded test device 140. Embedded test device 140 is further configured to, upon completion of testing of one or more chips under test, send a test completion signal to client 160 and a test result to server 120. Server 120 is further configured to receive and store the test result. Upon receipt of the test completion signal, client 160 is configured to query the server 120 for the test result and present the test result in a visual format on the interactive interface of client 160.

[0040] In this embodiment, if Figure 2 As shown, chip testing system 100 also includes client 160, which is connected to server 120 and embedded test device 140 via Ethernet cables, for example. Client 160 can be a computer, tablet, or other computing device with an interactive interface that receives user input and outputs information to the user, for example, via a display. Client 160 implements the scheduling of chip testing processes.

[0041] The test completion signal is used to notify the user of client 160 that the test has completed, allowing the user to view the test results promptly. The test results are generated by the embedded test device 140 running the test software and can be a test result document, including the chip number, test program download records, chip computing power peak / average values, and abnormal event markers during the test. Upon test completion, the embedded test device 140 sends the test completion signal and test results to client 160 and server 120, respectively.

[0042] Server 120 receives the test results and stores them in its memory. Server 120 can act as a data center, enabling persistent storage of raw data. Neither embedded test device 140 nor client 160 needs to store test results long-term, enabling lightweight management of embedded test device 140 and server 120.

[0043] The client 160 queries the test results from the server 120. The server 120 sends data representing the test results to the client 160 in response to the query. The client 160 then displays the test results on the display of the client 160 for the user to view. The client 160 has data pulling and visualization capabilities. Figure 3 and Figure 4 As shown, Figure 3 Shows the computing power test results for a certain chip using a neural network model, showing test parameters such as frequency, model, and time; Figure 4A statistical table of test results for a certain chip using multiple neural network models is shown, which presents parameters such as computing power, memory usage, frame rate, etc. corresponding to various neural network models.

[0044] Furthermore, the chip testing system 100 may further include a switch 180, which may be an Ethernet switch that can provide an exclusive electrical signal path for any two network nodes connected to the switch 180. In this case, the server 120, the embedded test device 140, and the client 160 are all connected to the switch 180, thereby achieving mutual communication.

[0045] In this embodiment, users can query detailed chip test results through client 160, facilitating the tracing of the test process. In this chip testing system 100, test programs, test results, and other related data are stored in the server 120 for centralized management, without occupying the memory space of the client 160 or the embedded test device 140.

[0046] In some embodiments, client 160 is further configured to send a test instruction to embedded test device 140. Embedded test device 140 is further configured to, based on the test instruction, send a test program acquisition request corresponding to the test instruction to server 120. Server 120 is further configured to, based on the test program acquisition request, load a test program corresponding to the test program acquisition request to embedded test device 140.

[0047] The client 160 is capable of receiving a signal that the embedded test device 140 has been successfully powered on, and in response to receiving the signal that the embedded test device 140 has been successfully powered on, sends a test instruction to the embedded test device 140. The user can configure the corresponding test instruction according to the architecture of the chip to be tested and the test scenario. The test scenario refers to the test task configuration defined according to different chip characteristics, test objectives, test requirements and simulated business scenarios. The test instruction includes information indicating the test content and information indicating the corresponding test program, that is, the test instruction indicates which test program needs to be obtained for the current test.

[0048] The embedded testing device 140 sends a test program acquisition request to the server 120 based on the test instruction. The test program acquisition request includes information indicating which test program to obtain. That is, the test program acquisition request corresponds to the test instruction.

[0049] Based on the test program acquisition request, the server 120 deploys the test program corresponding to the test program acquisition request to the embedded test device 140. As described above, the server 120 can store multiple sets of test programs, with different test programs adapted to different chips or corresponding to different test requirements for testing different performance indicators. Since the test program acquisition request specifies which test program to obtain, the server 120 loads the corresponding test program to the embedded test device 140 based on the test program acquisition request. The specific test program to be obtained as indicated by the test program acquisition request is thus deployed to the embedded test device 140.

[0050] In this embodiment, the loading of the test program is controlled by the client 160 , which enables dynamic on-demand loading of the test program and improves the flexibility of the chip testing system 100 .

[0051] In some embodiments, the chip testing system 100 includes multiple servers 120. The client 160 is further configured to dynamically configure resources of the multiple servers 120 according to a test scenario.

[0052] Different test scenarios require different server resources. The embedded test device 140 may utilize server resources during chip testing. The test scenario affects the server resource scheduling strategy. For example, when the computing power test load is high, high floating point performance server nodes can be allocated first. When the memory test pressure is high, high bandwidth memory server nodes can be allocated first. The client 160 dynamically schedules the resources of the server 120 based on the chip type, test objectives, business needs, etc. to achieve reasonable test resource allocation.

[0053] In this embodiment, based on the test scenario, such as computing intensive or memory intensive, resources are dynamically allocated to optimize load balancing.

[0054] In some embodiments, the client 160 is further configured to communicate with the server 120 to modify and update the test program according to the test scenario.

[0055] The test parameters and algorithm logic in the test program are configurable. For example, the neural network model complexity level, the number of concurrent threads for memory stress testing, the test duration threshold, etc. can be modified or updated. The test program can be modified and updated to support the testing of new types of chips in the future. Furthermore, through user interaction on client 160, new test programs can be added to server 120.

[0056] In this embodiment, the client 160 maintains the test program stored in the server 120 and dynamically updates the test program. Thus, the embedded test device 140 can be reused for different chips to be tested and different test scenarios.

[0057] In the above embodiment, client 160 controls server 120 and embedded test device 140 and schedules the test process. Client 160 provides an interactive interface for easy user control. Data storage and computing power simulation are implemented by server 120, making the client lightweight.

[0058] In some embodiments, the embedded testing device 140 is further configured to run a test program to simultaneously perform computing load testing and memory stress testing through multi-threading or multi-tasking concurrency.

[0059] For example, when running the test program, two groups of threads can be executed simultaneously, one group of threads is used to perform computing load testing, and the other group is used to perform memory stress testing. The two groups of threads run simultaneously. In this way, while the computing load test is running, the memory stress test is also consuming memory bandwidth and capacity, thereby simulating the memory preemption situation in actual business. In actual applications, the resource allocation can be dynamically adjusted according to the chip's use in scenarios such as in-vehicle, mobile phones, and smart homes. For example, in the test of an in-vehicle autonomous driving chip, 70% of the resources can be allocated to computing load testing (such as reasoning of a neural network model) and 30% of the resources can be allocated to memory stress testing (such as simulating memory contention). In this way, within the same time period, the chip is under pressure from both computing power and memory, thereby exposing problems that cannot be discovered in a single test or serial test.

[0060] In this embodiment, the chip testing system 100 can simulate and reproduce resource competition in actual business scenarios during testing, thereby being able to measure more accurate computing power specifications of the chip and reflect the actual performance of the chip in actual business scenarios.

[0061] In some embodiments, computing load testing includes at least one of the following: verification of various neural network models, verification of different neural network frequencies, verification of neural network memory ECC, verification of neural network computing accuracy, and verification of the maximum computing power of a specific neural network model. Memory stress testing includes at least one of the following: writing image processing data streams, writing high-frequency sensor data, and radar point cloud analysis and calculation.

[0062] like Figure 5 As shown in the figure, the test program executes the computing load test and memory stress test in parallel during the running process. Throughout the test process, the computing load test and memory stress test are executed together.

[0063] Verification of various neural network models refers to verifying the chip's compatibility with neural networks of different architectures and verifying the neural network's functional implementation. Verification of different neural network frequencies refers to testing the chip's stability at different operating frequencies and verifying whether computational errors occur at high frequencies. Verification of neural network memory ECC (Error Checking and Correction) refers to verifying the chip's memory error correction capabilities, for example by injecting bit flip errors, running the neural network, and monitoring the error correction capabilities. Verification of neural network computing power accuracy refers to detecting the computational errors of the neural network under different precision modes. Verification of the maximum computing power of a specific neural network model refers to verifying the peak computing power for a specific neural network model. The above multiple verification processes of the computing power load test can be performed sequentially or simultaneously. It is easy to understand that the computing power load test is not limited to the above content and can also be other tests on neural network models.

[0064] The memory stress test performed simultaneously with the computing power load test is intended to simulate actual business scenarios, such as the concurrent processing of high-frequency burst writes of camera and radar data in intelligent driving, which affects the memory occupancy and processing performance of the neural network. The memory stress test can include at least one of the image processing data stream writing, sensor high-frequency data writing, and radar point cloud analysis calculation. For example, while simulating neural network reasoning, it is possible to trigger the writing of multi-channel camera data in parallel to accurately reproduce the resource contention conflict of visual recognition + multi-sensor fusion of the chip in the autonomous driving scenario. The above-mentioned multiple memory stress tests can be executed sequentially or simultaneously according to the needs of memory pressure simulation. It is easy to understand that the memory stress test is not limited to the above content, and can also be other data processing that occupies memory.

[0065] In this embodiment, the chip testing system 100 can test the performance indicators of various aspects of the artificial intelligence chip neural network, and at the same time accurately simulate the memory contention of the artificial intelligence chip during actual use during the test process, which is close to actual business scenarios, such as autonomous driving scenarios, and avoids false computing power due to memory preemption during actual business processing.

[0066] The following references Figure 6 The testing process of the chip testing system 100 of the present application is described in detail.

[0067] The embedded test device 140 is pre-burned with an SDK that can boot a minimum system and meet the requirements for running test programs. The server 120 pre-stores multiple test programs. A user places the chip to be tested into the chip placement slot 142 and inserts the chip rack 148, thereby electrically connecting the chip to be tested to the embedded test device 140. The client 160 sends power-on commands to the server 120 and embedded test device 140, respectively. The server 120 and embedded test device 140 power on and start in response to the power-on commands. The power-on commands sent to the embedded test device 140 can be for one or more chip racks 148, thereby starting those or more chip racks 148. For example, only the chip rack 148 containing the chip to be tested can be started. In response to a normal startup, the embedded test device 140 sends a normal startup signal to the client 160. The user of the client 160 can easily determine whether the embedded test device 140 has started normally. If the embedded test device 140 has started normally, the user can send test commands to the embedded test device 140 via the client 160. In some examples, if the same type of chips to be tested are placed in one or more chip racks 148 and the test requirements for these chips to be tested are the same, the same test instructions can be sent to the one or more chip racks 148. Based on the test instructions, the embedded test device 140 sends a corresponding test program acquisition request to the server 120. The server 120 loads the corresponding test program to the embedded test device 140 based on the received test program acquisition request. The embedded test device 140 deploys the test program. In response to the successful deployment of the test program, a test program deployment success signal is sent to the client 160. Correspondingly, if the test program deployment is unsuccessful, a test program deployment failure signal is sent to the client 160. This allows the user of the client 160 to easily know whether the test program is successfully deployed on the embedded test device 140. If the test program is successfully deployed on the embedded test device 140, the user can send a test start instruction to the embedded test device 140 via the client 160, so that the embedded test device 140 runs the test program and starts testing the chip to be tested. In a specific implementation, one or more chip racks 148 can share a set of test programs, and one or more chip racks 148 can share a memory area to run the test program to test multiple chips to be tested in multiple chip placement slots 142 in the one or more chip racks 148. After the test is completed, the embedded test device 140 sends a test completion signal to the client 160 and sends the test results to the server 120, and the server 120 stores the test results. As a result, the user at the client 160 can know that the test has been completed, and can therefore send a test result query signal to the server 120 via the client 160. In response to receiving the test result query signal, the server 120 sends data including the test results to the client 160.Thus, the client 160 can present the test results, for example, via its display, for the user to analyze and trace the test process.

[0068] See also Figure 7 The present application also provides a chip testing device 700, comprising a chip interface and a processor. The chip interface is configured to electrically connect to one or more chips under test. The processor is configured to run a test program to test the one or more chips under test. When the test program is run, it simultaneously performs a computing load test and a memory stress test on the chips under test.

[0069] like Figure 7 As shown, the chip testing device 700 may further include a communication interface for electrically connecting to the server 120 and the client 160 in the chip testing system 100. The chip testing device 700 may further include a memory in which an SDK capable of booting a minimum system and running a test program is pre-installed. After the test program is downloaded to the chip testing device 700, it is volatilely deployed in the memory for execution by the chip testing device 700.

[0070] In the above-mentioned various embodiments of the embedded test system, the description of the embedded test device 140 can be applied to the chip test device 700 of this embodiment, and will not be repeated here.

[0071] See also Figure 8 The present application also provides a chip testing method, which is executed by the above-mentioned embedded testing device 140 .

[0072] In step 810 , a test program corresponding to the chip to be tested electrically connected to the embedded test device 140 and the test scenario is loaded.

[0073] In step 820, a test program is run to test the chip to be tested. When the test program is run, a computing load test and a memory stress test of the chip to be tested are simultaneously implemented in parallel.

[0074] In the above-mentioned various embodiments of the embedded test system, the related descriptions can be applied to the chip test method, which will not be repeated here.

[0075] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0076] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A chip testing system, comprising a server and an embedded testing device in communication connection, wherein: The server is configured to: store a test program and load the stored test program into the embedded test device; The embedded testing device is configured to run the test program to test one or more chips to be tested connected to the embedded testing device, and the test program simultaneously implements computing power load testing and memory stress testing on the chips to be tested in parallel during execution.

2. The chip testing system according to claim 1, wherein: The embedded test device includes a visual presentation module; The embedded test device is further configured to present the test status and test results of the one or more chips to be tested through the visual presentation module.

3. The chip testing system according to claim 1, further comprising a client connected to the server and the embedded testing device for communication; The embedded test device is further configured to: in response to completing the test of one or more chips to be tested, send a test completion signal to the client and send a test result to the server; The server is further configured to: receive and store the test results; The client is configured to: in response to receiving the test completion signal, query the test result from the server, and present the test result in a visual form on the interactive interface of the client.

4. The chip testing system according to claim 3, wherein: The client is further configured to: send a test instruction to the embedded test device, The embedded test device is further configured to: based on the test instruction, send a test program acquisition request corresponding to the test instruction to the server; The server is further configured to: based on the test program acquisition request, load a test program corresponding to the test program acquisition request into the embedded test device.

5. The chip testing system according to claim 3, wherein: The chip testing system includes multiple servers; The client is further configured to dynamically configure resources of the multiple servers according to a test scenario.

6. The chip testing system according to claim 3, wherein: The client is further configured to communicate with the server to modify and update the test program according to a test scenario.

7. The chip testing system according to any one of claims 1 to 6, wherein: The embedded testing device is further configured to run the test program to concurrently execute the computing load test and the memory stress test through multi-threading or multi-tasking.

8. The chip testing system according to claim 7, wherein: The computing power load test includes at least one of the following: verification of various neural network models, verification of different neural network frequencies, verification of neural network memory ECC, verification of neural network computing power accuracy, and verification of the maximum computing power of a specific neural network model; The memory stress test includes at least one of the following: image processing data stream writing, sensor high-frequency data writing, and radar point cloud analysis calculation.

9. Chip testing device, including: a chip interface configured to be electrically connected to one or more chips to be tested; as well as The processor is configured to run a test program to test the one or more chips to be tested, and the test program simultaneously implements a computing load test and a memory stress test on the chips to be tested in parallel when running.

10. A chip testing method, performed by an embedded testing device, comprising: Loading a test program corresponding to the chip to be tested and the test scenario electrically connected to the embedded test device; as well as The test program is run to test the chip to be tested. When the test program is run, the computing power load test and the memory stress test of the chip to be tested are simultaneously implemented in parallel.

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