Test method and device, electronic equipment, storage medium and computer program product

Abstract

The invention relates to a test method and device, electronic equipment, a storage medium and a computer program product. The method comprises the following steps: acquiring configuration information of a plurality of to-be-tested functional components on a chip; wherein the configuration information comprises a bus interface protocol of each functional component and a connection relationship among the plurality of functional components; based on a bus interface protocol of each functional component in the configuration information, determining a verification intellectual property VIP module for simulating each functional component from a preset template library, and forming a test environment based on a connection relationship among the simulated VIP modules; wherein the connection relationship among the plurality of VIP modules is the same as the connection relationship among the plurality of functional components; determining a test case associated with the plurality of VIP modules from a template library based on the connection relationship among the plurality of VIP modules; and in the test environment, based on the test case, testing channels among the plurality of functional components by using the plurality of VIP modules. According to the method, the test efficiency can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a testing method, device, electronic device, storage medium, and computer program product. Background Art

[0002] With the rapid development of information technology, system-on-chip (SoC) technology has demonstrated tremendous potential in the integrated circuit field and is widely used in emerging semiconductor and smart terminal products. SoC's high degree of integration and powerful scalability make it a preferred solution for meeting the needs of very large-scale integrated circuits. However, as SoC scale continues to expand, the complexity of communication lines between SoC functional components has increased dramatically. Testing the SoC bus has become a critical step in ensuring stable and reliable system performance. However, current SoC bus testing solutions are generally inefficient, which not only prolongs product development cycles but also increases manufacturing costs. Summary of the Invention

[0003] To overcome the problems existing in the related art, the present disclosure provides a testing method, apparatus, electronic device, storage medium and computer program product.

[0004] According to a first aspect of an embodiment of the present disclosure, a testing method is provided, the method comprising:

[0005] Obtaining configuration information of multiple functional components to be tested on the chip; wherein the configuration information includes a bus interface protocol of each functional component and a connection relationship between the multiple functional components;

[0006] Based on the bus interface protocol of each functional component in the configuration information, a verification intellectual property (VIP) module for simulating each functional component is determined from a preset template library, and a test environment is formed based on the connection relationship between the simulated multiple VIP modules; wherein the connection relationship between the multiple VIP modules is the same as the connection relationship between the multiple functional components;

[0007] Determining, from the template library, test cases associated with the multiple VIP modules based on the connection relationships between the multiple VIP modules;

[0008] In the test environment, based on the test case, the paths between the multiple functional components are tested using the multiple VIP modules.

[0009] In some embodiments, the test includes a path accuracy test between the plurality of functional components; and the testing of the paths between the plurality of functional components using the plurality of VIP modules based on the test case includes:

[0010] Based on the test case, the data sending and receiving process between the multiple functional components is simulated using the multiple VIP modules, and based on the consistency of the sent data and the received data, the accuracy of the path between the multiple functional components is determined.

[0011] In some embodiments, the test includes a performance test of paths between the multiple functional components; and the testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0012] Based on the test case, the data sending and receiving process between the multiple functional components is simulated using the multiple VIP modules, and based on the path parameters in the data sending and receiving process, the path performance between the multiple functional components is determined.

[0013] In some embodiments, the path parameter includes a bus bandwidth, the multiple VIP modules include a master VIP module for sending data and a slave VIP module for receiving data, the master VIP module is associated with one or more slave VIP modules, the configuration information also includes a data bit width and a clock frequency of a data sending component corresponding to the master VIP module, and the method further includes:

[0014] Determining a theoretical bus bandwidth between the master VIP module and a slave VIP module associated with the master VIP module based on a data bit width and a clock frequency of a data sending component corresponding to the master VIP module;

[0015] The determining of the path performance between the plurality of functional components based on the path parameters during the data sending and receiving process includes:

[0016] Based on the theoretical bus bandwidth of the master VIP module and the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module, the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to each slave VIP module associated with the master VIP module is determined.

[0017] In some embodiments, the path parameter includes a path bandwidth; the multiple VIP modules include multiple master VIP modules for sending data and slave VIP modules for receiving data; wherein the slave VIP modules are associated with the multiple master VIP modules;

[0018] The determining of the path performance between the plurality of functional components based on the path parameters during the data sending and receiving process includes:

[0019] determining an actual bus bandwidth between each master VIP module associated with the slave VIP module and the slave VIP module;

[0020] Determining a minimum bus bandwidth value among a plurality of actual bus bandwidths corresponding to a plurality of master VIP modules associated with the slave VIP module;

[0021] Based on the relationship between the minimum bus bandwidth value and a preset bus bandwidth threshold, the path performance between the data receiving component corresponding to the slave VIP module and each data sending component associated with the slave VIP module is determined.

[0022] In some embodiments, the plurality of VIP modules include a master VIP module for sending data and a slave VIP module for receiving data; the method further includes:

[0023] Obtaining a preset delay time and / or transmission mode; wherein the delay time is the difference between the time when the slave VIP module receives the data sent by the master VIP module and the time when the slave VIP module feeds back a notification message of receiving the data to the master VIP module; the transmission mode is the transmission mode when the master VIP module sends data to the slave VIP module;

[0024] The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0025] Based on the test case, the multiple VIP modules are utilized to simulate the data sending and receiving process between the multiple functional components with the preset delay time and / or transmission mode.

[0026] In some embodiments, the connection relationships between the multiple VIP modules include multiple groups of connection relationships, each group of connection relationships is associated with a test case; the method further includes:

[0027] Determine a test case to be executed among the multiple test cases, and set the VIP module associated with the test case to be executed to an open state, and the VIP module associated with the test case other than the test case to be executed to a closed state;

[0028] The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0029] The test case to be executed is started, and the paths between the multiple functional components corresponding to the multiple VIP modules in the turned-on state are tested using the multiple VIP modules in the turned-on state.

[0030] In some embodiments, the multiple functional components include a data sending component and a data receiving component, the configuration information also includes an address range for the data receiving component to receive data, and the method further includes:

[0031] Randomly select a target address from the address range of the data receiving component;

[0032] The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0033] Based on the test case, the VIP module corresponding to the data sending component is utilized to send data to the target address of the VIP module corresponding to the data receiving component to test the path between the data sending component and the data receiving component.

[0034] According to a second aspect of an embodiment of the present disclosure, a testing device is provided, the device comprising:

[0035] A first acquisition module is configured to acquire configuration information of multiple functional components to be tested on the chip; wherein the configuration information includes a bus interface protocol of each functional component and a connection relationship between the multiple functional components;

[0036] a formation module configured to determine, from a preset template library, a verification intellectual property (VIP) module for simulating each functional component based on a bus interface protocol of each functional component in the configuration information, and to form a test environment based on a connection relationship between the simulated plurality of VIP modules; wherein the connection relationship between the plurality of VIP modules is the same as the connection relationship between the plurality of functional components;

[0037] a first determining module configured to determine, from the template library, test cases associated with the multiple VIP modules based on the connection relationships between the multiple VIP modules;

[0038] The test module is configured to test the paths between the multiple functional components using the multiple VIP modules based on the test case under the test environment.

[0039] In some embodiments, the test includes a path accuracy test between the multiple functional components; the test module is also configured to simulate the data sending and receiving process between the multiple functional components based on the test case using the multiple VIP modules, and determine the accuracy of the path between the multiple functional components based on the consistency of the sent data and the received data.

[0040] In some embodiments, the test includes a path performance test between the multiple functional components; the test module is further configured to simulate the data sending and receiving process between the multiple functional components using the multiple VIPs based on the test case, and determine the path performance between the multiple functional components based on the path parameters in the data sending and receiving process.

[0041] In some embodiments, the path parameter includes a bus bandwidth, the multiple VIP modules include a master VIP module for sending data and a slave VIP module for receiving data, the master VIP module is associated with one or more slave VIP modules, the configuration information also includes a data bit width and a clock frequency of a data sending component corresponding to the master VIP module, and the apparatus further includes:

[0042] a second determining module configured to determine a theoretical bus bandwidth between the master VIP module and a slave VIP module associated with the master VIP module based on a data bit width and a clock frequency of a data sending component corresponding to the master VIP module;

[0043] The test module is also configured to determine the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to each slave VIP module associated with the master VIP module based on the theoretical bus bandwidth and the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module.

[0044] In some embodiments, the path parameters include bus bandwidth; the multiple VIP modules include multiple master VIP modules for sending data and slave VIP modules for receiving data; wherein, the slave VIP module is associated with the multiple master VIP modules; the test module is further configured to determine the actual bus bandwidth between each master VIP module associated with the slave VIP module and the slave VIP module; determine the minimum bus bandwidth value among the multiple actual bus bandwidths corresponding to the multiple master VIP modules associated with the slave VIP module; based on the relationship between the minimum bus bandwidth value and the preset bus bandwidth threshold, determine the path performance between the data receiving component corresponding to the slave VIP module and each data sending component associated with the slave VIP module.

[0045] In some embodiments, the plurality of VIP modules include a master VIP module for sending data and a slave VIP module for receiving data; the apparatus further includes:

[0046] A second acquisition module is configured to acquire a preset delay time and / or transmission mode; wherein the delay time is the difference between the time when the slave VIP module receives the data sent by the master VIP module and the time when the slave VIP module feeds back a notification message of receiving the data to the master VIP module; and the transmission mode is the transmission mode in which the master VIP module sends data to the slave VIP module;

[0047] The test module is further configured to simulate the data sending and receiving process between the multiple functional components based on the test case and using the multiple VIP modules with the preset delay time and / or transmission method.

[0048] In some embodiments, the connection relationships between the multiple VIP modules include multiple groups of connection relationships, each group of connection relationships is associated with a test case; the apparatus further includes:

[0049] a setting module configured to determine a test case to be executed among the multiple test cases, and set the VIP module associated with the test case to be executed to an open state, and set the VIP module associated with the test case other than the test case to be executed to a closed state;

[0050] The test module is further configured to start the test case to be executed, and use the multiple VIP modules in the open state to test the paths between the multiple functional components corresponding to the multiple VIP modules in the open state.

[0051] In some embodiments, the multiple functional components include a data sending component and a data receiving component, the configuration information also includes an address range for the data receiving component to receive data, and the apparatus further includes:

[0052] a selection module configured to randomly select a target address from the address range of the data receiving component;

[0053] The test module is further configured to send data to the target address of the VIP module corresponding to the data receiving component based on the test case using the VIP module corresponding to the data sending component to test the path between the data sending component and the data receiving component.

[0054] According to a third aspect of an embodiment of the present disclosure, there is provided an electronic device, including:

[0055] processor;

[0056] memory for storing computer programs or instructions;

[0057] The processor executes the computer program or instructions to implement the steps of the testing method described in the first aspect above.

[0058] According to a fourth aspect of an embodiment of the present disclosure, a non-temporary computer-readable storage medium is provided, which stores a computer program or instructions. When the computer program or instructions in the storage medium are executed by a processor, the steps of the testing method described in the first aspect above are implemented.

[0059] According to a fifth aspect of an embodiment of the present disclosure, a computer program product is provided, comprising a computer program or instructions, which, when executed by a processor, implement the steps of the testing method described in the first aspect above.

[0060] The technical solutions provided by the embodiments of the present disclosure may have the following beneficial effects:

[0061] In an embodiment of the present disclosure, an electronic device obtains configuration information of multiple functional components to be tested on a chip, determines a VIP module to simulate each functional component from a preset template library based on the bus interface protocol of each functional component in the configuration information, forms a test environment based on the connection relationships between multiple VIP modules that are identical to the connection relationships between the multiple functional components in the configuration information, further determines test cases associated with the multiple VIP modules from the template library based on the connection relationships between the multiple VIP modules, and, within the test environment, uses the multiple VIP modules based on the test cases to test the paths between the multiple functional components. Compared to the related art method of manually creating a test environment and test cases, this solution can automatically generate a test environment and test cases based on the configuration information and template library, is more intelligent, and can improve the efficiency of generating the test environment and test cases, thereby improving the efficiency of verifying the paths between the functional components to be tested on the chip. Compared to the manual operation method, this solution can also reduce the high error rate caused by manual operation, thereby improving the accuracy of verifying the paths between the functional components to be tested on the chip.

[0062] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0064] Figure 1 The figure is a flow chart showing a testing method according to an exemplary embodiment.

[0065] Figure 2It is a schematic diagram showing a framework of a testing method according to an exemplary embodiment.

[0066] Figure 3 The figure is a principle diagram of a test case according to an exemplary embodiment.

[0067] Figure 4 The figure is a flowchart illustrating an example of a testing method according to an exemplary embodiment.

[0068] Figure 5 The figure is a block diagram of a testing device according to an exemplary embodiment.

[0069] Figure 6 The figure is a structural block diagram of an electronic device according to an exemplary embodiment. DETAILED DESCRIPTION

[0070] Exemplary embodiments will be described in detail herein, with examples illustrated in the accompanying drawings. In the following description, when referring to the drawings, identical numerals in different figures represent identical or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present disclosure. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present disclosure, as detailed in the appended claims.

[0071] In the related art, there is a method for testing a system-level chip bus, which requires manual acquisition of the configuration information of each functional component on the chip to be tested, and manual selection of the verification intellectual property (VIP) used to simulate each functional component based on the configuration information of each functional component, and manual connection of the verification intellectual property corresponding to each functional component to generate a test environment for simulating the connection relationship between each functional component. After the test environment is manually established, it is necessary to manually determine the test cases for testing the paths between each functional component, and test the paths between each functional component based on the test environment and the test cases.

[0072] In the above method, creating a test environment and determining test cases are all done manually, which greatly reduces the efficiency of establishing a test environment for testing the system-level chip bus and determining test cases, and the error rate of manual operation is high. In addition, the recording of test data and the analysis of data after the test in the related technology are also performed manually, which is prone to reduce the reliability of the recorded data due to manual data entry errors or inaccurate recording, thereby affecting the subsequent analysis of the data and the decision-making results based on the data analysis results.

[0073] In this regard, the present disclosure provides a testing method. Figure 1FIG. 1 is a flow chart showing a testing method according to an exemplary embodiment. Figure 1 As shown, the method mainly includes the following steps:

[0074] S11. Obtain configuration information of multiple functional components to be tested on the chip; wherein the configuration information includes a bus interface protocol of each functional component and a connection relationship between the multiple functional components;

[0075] S12. Based on the bus interface protocol of each functional component in the configuration information, determine a verification intellectual property (VIP) module to simulate each functional component from a preset template library, and form a test environment based on the connection relationship between the simulated multiple VIP modules; wherein the connection relationship between the multiple VIP modules is the same as the connection relationship between the multiple functional components;

[0076] S13. Based on the connection relationship between the multiple VIP modules, determine test cases associated with the multiple VIP modules from the template library;

[0077] S14. Under the test environment, based on the test case, use the multiple VIP modules to test the paths between the multiple functional components.

[0078] The test method of the embodiments of the present disclosure can be applied to electronic devices that can form a test environment for simulating the connection relationship between various functional components on a chip, such as integrated circuit test equipment, user equipment (UE), mobile devices, user terminals, computing devices, cloud servers and other electronic devices. The embodiments of the present disclosure are not limited to this, and the following description is based on the electronic device as the execution subject.

[0079] In step S11, the electronic device obtains configuration information of multiple functional components to be tested on the chip, where the chip may be a SoC chip, an application-specific integrated circuit (ASIC) chip, a field-programmable gate array (FPGA), or other chip that can integrate multiple functional components. The embodiments of the present disclosure are described using the SoC chip as an example.

[0080] In the embodiments of the present disclosure, the SoC chip includes multiple functional components, each of which performs different functions, and the functional components work together to realize complex system functions. For example, the functional components may include a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), a digital signal processor (DSP), a double data rate (DDR) memory, a static random access memory (SRAM), a direct memory access (DMA), etc.

[0081] In an embodiment of the present disclosure, an electronic device obtains configuration information of multiple functional components to be tested on a chip, wherein a user can pre-select multiple functional components to be tested from all functional components on the chip. The number of the multiple functional components to be tested is at least two, and can also be 3, 10, 100, etc. It should be noted that the lower limit of the number of the multiple functional components to be tested is two, and the upper limit of the number of the multiple functional components to be tested is the number of all functional components on the chip. For example, if there are 200 functional components on the chip, the number of the multiple functional components to be tested can be any integer between 2 and 200. The multiple functional components to be tested must include at least one data sending component for sending data and at least one data receiving component for receiving data. The number of data sending components and data receiving components can be flexibly adjusted according to the number of functional components to be tested. The electronic device obtains configuration information of the multiple functional components to be tested, wherein the configuration information of the multiple functional components to be tested can be configured in the same configuration file, or each functional component can have a configuration file. This embodiment of the present disclosure does not impose any limitation on this.

[0082] In the embodiment of the present disclosure, the configuration information includes the bus interface protocol of each functional component and the connection relationship between multiple functional components. Among them, the bus interface protocol is an agreement and specification for a functional component to exchange data and communicate with other functional components between different systems, devices or software, which defines the rules, format, transmission method, etc. of communication. The bus interface protocol of each functional component must comply with the bus standard on the chip. For example, when the bus standard of the chip is the Advanced Microcontroller Bus Architecture (AMBA), the bus interface protocol of each function is the AMBA bus interface protocol; the bus interface protocol may include the Advanced Extensible Interface (AXI) protocol, the Advanced High-performance Bus (AHB) interface protocol, the Advanced Peripheral Bus (APB) interface protocol, the Advanced Coherence Extensible Interface (AXI Coherency Extensions, ACE) protocol, etc. It should be noted that the bus interface protocols of different functional components may be the same or different, and the embodiment of the present disclosure does not limit this.

[0083] In step S12, the electronic device determines a VIP module from a preset template library to simulate each functional component based on the bus interface protocol of each functional component in the configuration information. The preset template library stores VIP modules supporting different bus interface protocols. Each VIP module corresponds to one functional component, and each VIP module uses the same bus interface protocol as its corresponding functional component.

[0084] In the disclosed embodiment, a VIP module is determined to simulate each functional component, and a test environment is formed based on the connection relationship between the multiple simulated VIP modules. Since one VIP module corresponds to one functional component, and the configuration information of the multiple functional components obtained by the electronic device includes the connection relationship between the multiple functional components, the connection relationship between the multiple VIP modules can be established based on the configuration information to form the test environment. The connection relationship between the multiple VIP modules is the same as the connection relationship between the multiple functional components. It should be noted that the test environment in the disclosed embodiment can be generated based on the Universal Verification Methodology (UVM).

[0085] In the embodiment of the present disclosure, the electronic device can also generate a virtual sequence (vseq) associated with multiple VIP modules based on the template library to describe a series of operations that need to be performed during the test process, a specific implementation environment (env) for characterizing the test environment, and a virtual sequencer (vsqr) to form a complete test environment.

[0086] Figure 2 is a schematic diagram of a testing method according to an exemplary embodiment. Figure 2 As shown, the verification intellectual property module is a VIP module, the master device verification intellectual property module represents that the function of the functional component simulated by the verification intellectual property module on the chip is to send data to other functional components; the slave device intellectual property module represents that the function of the functional component simulated by the verification intellectual property module on the chip is to receive data sent by other functional components. L21 is a test environment for a system-on-chip, L22 is an advanced extensible interface protocol environment, L22 includes multiple verification intellectual property modules for simulating the functional components to be tested on the chip, wherein the verification intellectual property module located in the advanced extensible interface protocol environment L22 represents that the bus interface protocol of the functional component simulated by the verification intellectual property module is the advanced extensible interface protocol. L23 is an advanced consistency extensible interface protocol environment, L23 includes multiple verification intellectual property modules for simulating the functional components to be tested on the chip, wherein the verification intellectual property module located in the advanced consistency extensible interface protocol environment L23 represents that the bus interface protocol of the functional component simulated by the verification intellectual property module is the advanced consistency extensible interface protocol. L24 is an advanced peripheral bus protocol environment. L24 includes multiple verification intellectual property modules for simulating functional components to be tested on the chip. The verification intellectual property module located in the advanced peripheral bus protocol environment L24 represents that the bus interface protocol of the functional components simulated by the verification intellectual property module is the advanced peripheral bus protocol. L25 is an advanced high-performance bus protocol environment. L25 includes multiple verification intellectual property modules for simulating functional components to be tested on the chip. The verification intellectual property module located in the advanced high-performance bus protocol environment L25 represents that the bus interface protocol of the functional components simulated by the verification intellectual property module is the advanced high-performance bus protocol. L26 is the chip bus. The verification intellectual property rights that communicate with each other are connected via the chip bus L26.

[0087] In step S13, the electronic device determines test cases associated with multiple VIP modules from a template library based on the connection relationship between the multiple VIP modules. The preset template library stores multiple test cases associated with each functional component on the chip. After determining the multiple functional components to be tested on the chip and the multiple VIP modules to simulate each functional component to be tested, test cases associated with the functional components corresponding to the multiple VIP modules are determined from the preset template library. It should be noted that the test case associated with the multiple VIP modules determined from the template library can be one or more, and the number of test cases is associated with the number of VIP modules, and the number of test cases is positively correlated with the number of VIP modules.

[0088] For example, in some embodiments, when the number of functional components to be tested is two, the number of corresponding VIP modules is also two, and the number of test cases may be one, which is used to test the path between the two functional components.

[0089] In other embodiments, when the number of functional components to be tested is 3, and the functional components to be tested include 2 data sending components for sending data and one data receiving component for receiving data, the number of test cases may be two, each used to test the path between any data sending component and the data receiving component; the number of test cases may also be 3, including the aforementioned two test cases for testing the path between any data sending component and the data receiving component, and also including two data sending components sending data to the data receiving component at the same time, for testing the path between each data sending component and the data receiving component when the two data sending components send data to the data receiving component at the same time. The number of test cases can be even greater, and the embodiments of the present disclosure do not impose any restrictions on this. It should be noted that, when multiple test cases are included, the VIP modules associated with different test cases are not exactly the same. As mentioned above, the functional components to be tested include two data sending components for sending data and one data receiving component for receiving data, wherein the two data sending components are A and B, and the data receiving component is C. When there are three test cases, the VIP modules associated with the first test case are the VIP module corresponding to A and the VIP module corresponding to C, the VIP modules associated with the second test case are the VIP module corresponding to B and the VIP module corresponding to C, and the VIP modules associated with the third test case are the VIP module corresponding to A, the VIP module corresponding to B, and the VIP module corresponding to C.

[0090] In other embodiments, when the number of functional components to be tested is greater than 3, the test cases may include test cases for testing the path between any data sending component and any data receiving component in multiple functional components to be tested, and / or test cases for testing the path between each data sending component in any number of data sending components and the data receiving component when any number of data sending components communicate with any data receiving component.

[0091] In the embodiments of the present disclosure, it is understood that functional components capable of forming a path need to be connected. Therefore, based on the connection relationship between multiple VIP modules, VIP modules capable of forming a path between multiple VIP modules can be determined.

[0092] In step S14, the electronic device, under a test environment, utilizes multiple VIP modules to test the paths between multiple functional components based on the test case. As previously mentioned, the number of test cases can be one or more. Under a test environment, the electronic device, based on the test case, utilizes at least two VIP modules associated with the test case to test the paths between at least two functional components associated with the at least two VIP modules.

[0093] In the embodiment of the present disclosure, the communication between multiple functional components includes burst transfer communication, narrow transfer communication, outstanding transfer communication, etc. When the embodiment of the present disclosure uses multiple VIP modules to test the paths between multiple functional components, any of the above communication methods can be simulated. In this regard, the embodiment of the present disclosure does not impose any restrictions.

[0094] In an embodiment of the present disclosure, an electronic device obtains configuration information of multiple functional components to be tested on a chip, determines a VIP module to simulate each functional component from a preset template library based on the bus interface protocol of each functional component in the configuration information, forms a test environment based on the connection relationships between multiple VIP modules that are identical to the connection relationships between the multiple functional components in the configuration information, further determines test cases associated with the multiple VIP modules from the template library based on the connection relationships between the multiple VIP modules, and, within the test environment, uses the multiple VIP modules based on the test cases to test the paths between the multiple functional components. Compared to the related art method of manually creating a test environment and test cases, this solution can automatically generate a test environment and test cases based on the configuration information and template library, is more intelligent, and can improve the efficiency of generating the test environment and test cases, thereby improving the efficiency of verifying the paths between the functional components to be tested on the chip. Compared to the manual operation method, this solution can also reduce the high error rate caused by manual operation, thereby improving the accuracy of verifying the paths between the functional components to be tested on the chip.

[0095] In some embodiments, the test includes a path accuracy test between the plurality of functional components; and the testing of the paths between the plurality of functional components using the plurality of VIP modules based on the test case includes:

[0096] Based on the test case, the data sending and receiving process between the multiple functional components is simulated using the multiple VIP modules, and based on the consistency of the sent data and the received data, the accuracy of the path between the multiple functional components is determined.

[0097] In the disclosed embodiment, the test includes a path accuracy test between multiple functional components, which is used to test whether the multiple functional components can work together as expected after being integrated into the chip, including the integrity of data transmission, the correctness of timing, and the consistency of the protocol.

[0098] In an embodiment of the present disclosure, an electronic device utilizes multiple VIP modules to simulate the data sending and receiving process between multiple functional components based on test cases, and determines the accuracy of the paths between the multiple functional components based on the consistency of the sent data and the received data. Based on a test case, an electronic device can utilize multiple VIP modules associated with the test case to simulate data sending and receiving between multiple functional components simulated by the multiple VIP modules associated with the test case. The electronic device can obtain data sent by a VIP module for sending data among the multiple VIP modules, and obtain data received by a VIP module for receiving data corresponding to the VIP module sending data among the multiple VIP modules, and compare the sent data with the received data. Based on the consistency of the sent data and the received data, the accuracy of the path between the data sending component simulated by the VIP module sending data and the data receiving component simulated by the VIP module receiving data is determined. If the sent data and the received data are consistent, it indicates that the data has not been tampered with or lost during the sending and / or receiving process, indicating that the path between the data sending component simulated by the VIP module sending data and the data receiving component simulated by the VIP module receiving data is accurate; if the sent data and the received data are inconsistent, it indicates that the data may have been tampered with or lost during the sending and / or receiving process, indicating that the path between the data sending component simulated by the VIP module sending data and the data receiving component simulated by the VIP module receiving data is inaccurate.

[0099] In the embodiment of the present disclosure, as described above, the test case may include multiple test cases, and the VIP modules associated with each test case are not exactly the same. For each test case, the VIP module associated with the test case is used to simulate the data sending and receiving process between the functional components associated with the test case, and based on the consistency of the sent data and the received data, the accuracy of the path between the functional components associated with the test case is determined.

[0100] It should be noted that, in the embodiments of the present disclosure, based on the test case, different sequences may be used to generate stimuli so as to utilize multiple VIP modules to simulate the data sending and receiving process between multiple functional components simulated by the multiple VIP modules.

[0101] In the disclosed embodiments, an electronic device determines the accuracy of paths between multiple functional components based on the consistency of sent data and received data. On the one hand, this solution is simple, effective, and highly intelligent. On the other hand, by testing the accuracy of paths between multiple functional components, the multiple functional components can be debugged based on the test results, thereby improving the accuracy of paths between the multiple functional components in actual use. On another hand, compared with the related art of manually recording data and manually analyzing the data to debug the functional components, this solution automatically compares the consistency of sent data and received data, thereby improving the accuracy of data recording, thereby improving the accuracy of subsequent data analysis and decision-making results based on the data analysis results.

[0102] In some embodiments, the test includes a performance test of paths between the multiple functional components; and the testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0103] Based on the test case, the data sending and receiving process between the multiple functional components is simulated using the multiple VIP modules, and based on the path parameters in the data sending and receiving process, the path performance between the multiple functional components is determined.

[0104] In the disclosed embodiments, the test includes testing the performance of the paths between the multiple functional components. This is used to test whether the path performance between the multiple functional components meets the expected standards after the multiple functional components are integrated into the chip. This includes testing data transmission rate, effective bandwidth utilization, control of communication delays, and the compatibility and efficiency of communication protocols.

[0105] In an embodiment of the present disclosure, an electronic device utilizes multiple VIP modules to simulate the data transmission and reception process between multiple functional components based on a test case, and determines the path performance between the multiple functional components based on path parameters during the data transmission and reception process. In some embodiments, the path parameters may include a data transmission rate. The electronic device may record the data transmission and reception rate between the multiple functional components, and determine the path performance between the multiple functional components based on the relationship between the data transmission and reception rate between the multiple functional components and a preset rate threshold. For example, when the data transmission and reception rate between the multiple functional components is greater than the preset rate threshold, the path performance between the multiple functional components is determined to meet the requirements. Otherwise, the path performance between the multiple functional components does not meet the requirements and needs to be adjusted, wherein the preset rate threshold is a set value.

[0106] In other embodiments, the path parameters may also be bus bandwidth, path packet loss rate, etc., and corresponding preset bus bandwidth thresholds, packet loss rate thresholds, etc. may be set, and the path performance between multiple functional components may be determined based on the relationship between actual data and each threshold.

[0107] In the disclosed embodiments, an electronic device determines the path performance between multiple functional components based on path parameters during data transmission and reception. The solution is simple, effective, and highly intelligent. By testing the path performance between multiple functional components, the multiple functional components can be debugged based on the test results, thereby improving the efficiency and reliability of the paths of the multiple functional components in actual use.

[0108] In some embodiments, the path parameter includes a bus bandwidth, the multiple VIP modules include a master VIP module for sending data and a slave VIP module for receiving data, the master VIP module is associated with one or more slave VIP modules, the configuration information also includes a data bit width and a clock frequency of a data sending component corresponding to the master VIP module, and the method further includes:

[0109] Determining a theoretical bus bandwidth between the master VIP module and a slave VIP module associated with the master VIP module based on a data bit width and a clock frequency of a data sending component corresponding to the master VIP module;

[0110] The determining of the path performance between the plurality of functional components based on the path parameters during the data sending and receiving process includes:

[0111] Based on the theoretical bus bandwidth and the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module, the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to each slave VIP module associated with the master VIP module is determined.

[0112] In the embodiment of the present disclosure, multiple VIP modules include a master (Master) VIP module for sending data and a slave (Slave) VIP module for receiving data. The master VIP module is associated with one or more slave VIP modules. When the number of master VIP modules is one, the master VIP module is associated with one or more slave VIP modules. When the number of master VIP modules is multiple, each master VIP module is associated with one or more slave VIP modules. The slave VIP modules associated with different master VIP modules may be the same or different.

[0113] In the embodiment of the present disclosure, the configuration information also includes the data bit width and clock frequency of the data sending component corresponding to the main VIP module, wherein the data bit width represents the amount of data that can be transmitted by the data sending component to the associated data receiving component during one communication process, which determines the width or capacity of the data during the transmission process; the clock frequency refers to the basic frequency of the clock in the synchronization circuit, which determines the operating speed of the internal logic circuit of the data sending component. A higher clock frequency means that the data sending component can complete more operations in a shorter time.

[0114] In the disclosed embodiment, the electronic device further determines the theoretical bus bandwidth between the master VIP module and a slave VIP module associated with the master VIP module based on the data bit width and clock frequency of the data transmission component corresponding to the master VIP module. For example, the theoretical bus bandwidth may be determined based on the product of the data bit width and clock frequency of the data transmission component corresponding to the master VIP module. If there are multiple master VIP modules, the theoretical bus bandwidth is determined for each master VIP module.

[0115] In an embodiment of the present disclosure, the electronic device determines the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to each slave VIP module associated with the master VIP module based on the theoretical bus bandwidth and the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module. If the difference between the actual bus bandwidth and the theoretical bus bandwidth between the master VIP module and a slave VIP module associated with the master VIP module is less than a preset difference threshold, it indicates that the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to the above-mentioned slave VIP module associated with the master VIP module meets the requirements; otherwise, it does not meet the requirements.

[0116] In the embodiment of the present disclosure, the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module can be obtained by measurement. The embodiment of the present disclosure does not limit the method of obtaining the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module, such as it can be measured using a network performance testing tool.

[0117] In the embodiment of the present disclosure, when there are multiple master VIP modules, the electronic device determines, for each master VIP module, the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to each slave VIP module associated with the master VIP module based on the theoretical bus bandwidth of the master VIP module and the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module.

[0118] The embodiment of the present disclosure determines the theoretical bus bandwidth of the main VIP module, and based on the theoretical bus bandwidth and the actual bus bandwidth, determines the path performance between the data sending component corresponding to the main VIP module and the data receiving component corresponding to each slave VIP module associated with the main VIP module; the embodiment of the present disclosure introduces the calculation of the theoretical bus bandwidth and the comparison of the theoretical bus bandwidth and the actual bus bandwidth, which can further improve the accuracy of determining the path performance and has a high degree of intelligence.

[0119] In some embodiments, the path parameter includes a bus bandwidth; the plurality of VIP modules include a plurality of master VIP modules for sending data and slave VIP modules for receiving data; wherein the slave VIP modules are associated with the plurality of master VIP modules;

[0120] The determining of the path performance between the plurality of functional components based on the path parameters during the data sending and receiving process includes:

[0121] determining an actual bus bandwidth between each master VIP module associated with the slave VIP module and the slave VIP module;

[0122] Determining a minimum bus bandwidth value among a plurality of actual bus bandwidths corresponding to a plurality of master VIP modules associated with the slave VIP module;

[0123] Based on the relationship between the minimum bus bandwidth value and a preset bus bandwidth threshold, the path performance between the data receiving component corresponding to the slave VIP module and each data sending component associated with the slave VIP module is determined.

[0124] In the embodiment of the present disclosure, multiple VIP modules include a master VIP module for sending data and a slave VIP module for receiving data. The slave VIP module is associated with multiple master VIP modules. When the number of slave VIP modules is one, the slave VIP module is associated with multiple master VIP modules. When the number of slave VIP modules is multiple, each slave VIP module is associated with multiple master VIP modules. It should be noted that when the number of slave VIP modules is multiple, the multiple master VIP modules associated with each slave VIP module may be the same or different, and the embodiment of the present disclosure does not impose any limitation on this.

[0125] In an embodiment of the present disclosure, the electronic device determines the actual bus bandwidth between each master VIP module associated with the slave VIP module and the slave VIP module, wherein, when there are multiple slave VIP modules, the electronic device needs to determine the actual bus bandwidth between each master VIP module associated with the slave VIP module and the slave VIP module for each slave VIP module. The actual bus bandwidth between each master VIP module and the slave VIP modules associated with the master VIP module can be obtained by measurement, and the embodiment of the present disclosure does not limit the method of obtaining the actual bus bandwidth between each master VIP module and the slave VIP modules associated with the master VIP module, such as the method of measuring using a network performance testing tool.

[0126] In an embodiment of the present disclosure, the electronic device determines the minimum bus bandwidth value among multiple actual bus bandwidths of multiple master VIP modules associated with the slave VIP module, wherein, when the number of slave VIP modules is multiple, the electronic device determines, for each slave VIP module, the minimum bus bandwidth value among multiple actual bus bandwidths of multiple master VIP modules associated with the slave VIP module.

[0127] In an embodiment of the present disclosure, an electronic device determines the performance of a path between a data receiving component corresponding to a slave VIP module and each data transmitting component associated with the slave VIP module, when multiple data transmitting components transmit data to a data receiving component corresponding to a slave VIP, based on the relationship between a minimum bus bandwidth value and a preset bus bandwidth threshold. The preset bus bandwidth threshold is a set value that can be set in advance by a user. If the minimum bus bandwidth is less than the preset bus bandwidth threshold, it indicates that the current path performance does not meet the requirements and requires adjustment. Otherwise, it meets the requirements.

[0128] In the embodiment of the present disclosure, the data receiving component corresponding to the VIP module may be a memory, such as a DDR memory, SRAM, DMA, etc. It can be understood that in the actual use of the chip, there may be multiple data sending components sending data to the same memory. At this time, if the minimum bus bandwidth does not meet the conditions, it may affect the normal operation of other functional components in the chip. Therefore, the communication of the memory needs to be stress tested.

[0129] In the disclosed embodiment, since the minimum bus bandwidth often determines the lower limit of the path performance when multiple functional components communicate, by determining the minimum bus bandwidth among multiple actual bus bandwidths of multiple main VIP modules associated with the slave VIP module and comparing it with the threshold, the path bottleneck can be identified more intuitively and the low-performance path can be optimized in advance, thereby improving the overall stability and communication efficiency of the chip and being more intelligent.

[0130] In some embodiments, the plurality of VIP modules include a master VIP module for sending data and a slave VIP module for receiving data; the method further includes:

[0131] Obtaining a preset delay time and / or transmission mode; wherein the delay time is the difference between the time when the slave VIP module receives the data sent by the master VIP module and the time when the slave VIP module feeds back a notification message of receiving the data to the master VIP module; the transmission mode is the transmission mode when the master VIP module sends data to the slave VIP module;

[0132] The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0133] Based on the test case, the multiple VIP modules are utilized to simulate the data sending and receiving process between the multiple functional components with the preset delay time and / or transmission mode.

[0134] In the embodiment of the present disclosure, multiple VIP modules include a main VIP module for sending data and a slave VIP module for receiving data, and the electronic device also obtains a preset delay time and / or transmission mode; wherein the delay time is the difference between the time when the slave VIP module receives the data sent by the main VIP module and the time when the slave VIP module feeds back a notification message of the received data to the main VIP module; the transmission mode is the transmission mode of sending data from the main VIP module to the slave VIP module.

[0135] In the disclosed embodiment, the preset delay time and / or transmission mode can be set in advance by the user, such as setting the delay time to 100 nanoseconds and setting the transmission mode to AxID fixed transmission (FIXED) mode or AxID incremental transmission (INCR) mode. The user can set a different delay time and / or transmission mode each time a test is performed based on a test case, such as setting the delay time to 100 nanoseconds and the transmission mode to AxID incremental transmission mode during the first test based on the test case, and setting the delay time to 100 nanoseconds and the transmission mode to AxID fixed transmission mode during the second test based on the test case, etc., to simulate various situations that may occur during the actual operation of the functional component.

[0136] In the disclosed embodiments, an electronic device utilizes multiple VIP modules based on test cases to simulate the data sending and receiving process between multiple functional components simulated by the multiple VIP modules with a preset delay time and / or transmission method. This can reproduce various scenarios in the actual operation of each functional component, discover and solve potential problems in advance, reduce the failure rate of the chip, and improve user experience and product quality.

[0137] In some embodiments, the connection relationships between the multiple VIP modules include multiple groups of connection relationships, each group of connection relationships is associated with a test case; the method further includes:

[0138] Determine a test case to be executed among the multiple test cases, and set the VIP module associated with the test case to be executed to an open state, and the VIP module associated with the test case other than the test case to be executed to a closed state;

[0139] The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0140] The test case to be executed is started, and the paths between the multiple functional components corresponding to the multiple VIP modules in the turned-on state are tested using the multiple VIP modules in the turned-on state.

[0141] In the embodiment of the present disclosure, the connection relationship between multiple VIP modules includes multiple groups of connection relationships, and each group of connection relationships is associated with a test case. It should be noted that the VIP modules associated with each test case are not exactly the same.

[0142] In the disclosed embodiment, multiple test cases can be executed in parallel or serially. The electronic device determines a test case to be executed among the multiple test cases, and sets the VIP module associated with the test case to be executed to an on state and the VIP module associated with the test case other than the test case to be executed to a off state.

[0143] In an embodiment of the present disclosure, the electronic device starts a test case to be executed, and uses multiple VIP modules in an on state to test paths between multiple functional components corresponding to the multiple VIP modules in the on state.

[0144] Figure 3This is a schematic diagram of a test case according to an exemplary embodiment, wherein the verification intellectual property module is a VIP module, the master device verification intellectual property module represents that the function of the functional component simulated by the verification intellectual property module on the chip is to send data to other functional components; the slave device verification intellectual property module represents that the function of the functional component simulated by the verification intellectual property module on the chip is to receive data sent by other functional components. L31 is a system-on-chip test environment, L32 is an advanced extensible interface protocol environment, L32 includes multiple verification intellectual property modules for simulating functional components to be tested on the chip, wherein the verification intellectual property module located in the advanced extensible interface protocol environment L32 represents that the bus interface protocol of the functional component simulated by the verification intellectual property module is the advanced extensible interface protocol. L33 is an advanced consistency extensible interface protocol environment, L33 includes multiple verification intellectual property modules for simulating functional components to be tested on the chip, wherein the verification intellectual property module located in the advanced consistency extensible interface protocol environment L33 represents that the bus interface protocol of the functional component simulated by the verification intellectual property module is the advanced consistency extensible interface protocol. L34 is an advanced peripheral bus protocol environment, L34 includes a plurality of verification intellectual property modules for simulating functional components to be tested on the chip, wherein the verification intellectual property module located in the advanced peripheral bus protocol environment L34 represents that the bus interface protocol of the functional components simulated by the verification intellectual property module is the advanced peripheral bus protocol. L35 is an advanced high-performance bus protocol environment, L35 includes a plurality of verification intellectual property modules for simulating functional components to be tested on the chip, wherein the verification intellectual property module located in the advanced high-performance bus protocol environment L35 represents that the bus interface protocol of the functional components simulated by the verification intellectual property module is the advanced high-performance bus protocol. L36 is the chip bus, and the verification intellectual property rights that communicate with each other are connected through the chip bus L36. The verification intellectual property modules associated with the test case to be executed are the master device verification intellectual property module 1L321 located in the advanced extensible interface protocol environment L32, and the slave device verification intellectual property module 1L341 located in the advanced peripheral bus protocol environment L34. The test case is used to test the path between the functional component corresponding to the master device verification intellectual property module 1L321 and the functional component corresponding to the slave device verification intellectual property module 1L341. As shown Figure 3 As shown, when testing the functional components corresponding to the intellectual property module 1L321 and the paths between the functional components corresponding to the slave device verification intellectual property module 1L341 based on the test case, only the master device verification intellectual property module 1L321 and the slave device verification intellectual property module 1L341 are turned on, and other verification intellectual property modules are kept closed.

[0145] In an embodiment of the present disclosure, each VIP module may also have an identifier, and each VIP module identifier represents the functional component corresponding to the VIP module. For example, each VIP module identifier may be the name of the functional component corresponding to the VIP module. When a test case is completed and an error occurs in the path between multiple VIP modules associated with the test case, the identifiers of the multiple VIP modules associated with the test case are displayed, allowing the user to quickly identify the functional component corresponding to the VIP module that experienced the error.

[0146] The embodiment of the present disclosure determines the test cases to be executed among multiple test cases, and sets the VIP modules associated with the test cases to be executed to an on state and the VIP modules associated with the test cases other than the test cases to be executed to a off state, starts the test cases to be executed, and uses the multiple VIP modules in the on state to test the paths between the multiple functional components corresponding to the multiple VIP modules in the on state. This can reduce the impact of other VIP modules not associated with the test case being turned on when testing the paths between the functional components associated with a test case, thereby affecting the test results. The method of the embodiment of the present disclosure can further improve the accuracy of the test and is highly intelligent.

[0147] In some embodiments, the multiple functional components include a data sending component and a data receiving component, the configuration information also includes an address range for the data receiving component to receive data, and the method further includes:

[0148] Randomly select a target address from the address range of the data receiving component;

[0149] The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes:

[0150] Based on the test case, the VIP module corresponding to the data sending component is utilized to send data to the target address of the VIP module corresponding to the data receiving component to test the path between the data sending component and the data receiving component.

[0151] In the embodiment of the present disclosure, the multiple functional components include a data sending component and a data receiving component. The configuration information also includes an address range for the data receiving component to receive data. For example, the address range for a certain data receiving component to receive data may be 1000-8000.

[0152] In the embodiment of the present disclosure, the electronic device randomly selects a target address from the address range of the data receiving component. For example, when the address range of the data receiving component for receiving data is 1000-8000, the electronic device can arbitrarily select an address from 1000-8000 to receive the test data, such as 2000-2500 as the target address.

[0153] In an embodiment of the present disclosure, based on a test case, the electronic device uses the VIP module corresponding to the data sending component to send data to the target address of the VIP module corresponding to the data receiving component to test the path between the data sending component and the data receiving component.

[0154] It should be noted that, in the embodiments of the present disclosure, VIP modules corresponding to different data sending components can be flexibly configured in test cases to access any address in the entire chip or access within a restricted address range, as required.

[0155] In the embodiments of the present disclosure, since data may be sent to any address in the address range of the data receiving component based on different transmission modes during the actual communication process of the functional component, in order to test that each address in the address range of the data receiving component can receive and store data, randomly selecting a target address and sending data to the target address can further improve the randomness of the test, so as to reduce the possibility of communication errors caused by errors in some addresses in the address range during the actual communication process of the functional component.

[0156] Figure 4 is a flowchart illustrating a testing method according to an exemplary embodiment. Figure 4 As shown, the following steps are included:

[0157] S41. Build a chip bus verification framework template library.

[0158] In the embodiment of the present disclosure, taking the chip bus verification framework template library as a preset template library as an example, the chip bus verification framework template library includes a test case set, a VIP module set, a test environment set, a virtual sequence set, etc.

[0159] S42. Collect information on the intellectual property module in the device under test and generate a configuration file.

[0160] In the embodiment of the present disclosure, the device under test is a chip, and the intellectual property module in the device under test is an example of a functional component to be tested in the chip. The configuration file is configuration information of the intellectual property module in the device under test.

[0161] S43. The framework template library reads the configuration file and generates an integrated bus verification framework of the test environment and test cases.

[0162] In the embodiment of the present disclosure, a test environment and test cases are generated based on a framework template library and a configuration file to generate a bus verification framework.

[0163] S44. Select a test case for simulation.

[0164] In the embodiment of the present disclosure, the test case may include one or more. When there is one test case, based on the test case, the path between the functional components associated with the test case is simulated in the test environment; when there are multiple test cases, the functional components associated with the multiple test cases are not exactly the same, and the corresponding test cases can be selected to test the paths between different functional components. When there are multiple test cases, the multiple test cases can be run in parallel or serially.

[0165] S45: Is it a performance test? If so, go to step S46; if not, go to step S47.

[0166] In the embodiment of the present disclosure, taking the performance test as a path performance test as an example, after selecting a test case, it is determined whether the test case is a performance test. If so, step S46 is executed; if not, step S47 is executed.

[0167] S46. Automatically collect performance data and conduct performance analysis.

[0168] In the embodiment of the present disclosure, taking the actual bus bandwidth as the performance data as an example, after performing simulation testing using a test case, the path performance data of the functional components during the simulation process can be automatically collected, and based on the path performance data, the path performance between the functional components can be analyzed.

[0169] S47 is a path test and data output comparison.

[0170] In the embodiment of the present disclosure, taking the path test as a path accuracy test as an example, if the test case is not for testing the path performance between functional components, then the test case is used to test the accuracy of the path between functional components, obtain the sent data and the received data, and compare them to determine whether the path is accurate.

[0171] The embodiment of the present disclosure pre-builds a chip bus verification framework template library, and automatically generates a test environment and test cases based on the configuration file and the framework template library, performs simulation based on the test cases, and automatically collects simulation data for analysis. On the one hand, it can improve the efficiency of generating the test environment and test cases; on the other hand, it does not require manual data collection for analysis, which can improve the accuracy and efficiency of data collection, thereby improving the accuracy of data analysis and having higher intelligence.

[0172] Figure 5 FIG. 5 is a block diagram of a testing device 500 according to an exemplary embodiment. Figure 5 As shown, the device mainly includes:

[0173] A first acquisition module 501 is configured to acquire configuration information of multiple functional components to be tested on a chip; wherein the configuration information includes a bus interface protocol of each functional component and a connection relationship between the multiple functional components;

[0174] Formation module 502 is configured to determine, from a preset template library, a verification intellectual property (VIP) module to simulate each functional component based on the bus interface protocol of each functional component in the configuration information, and to form a test environment based on the connection relationship between the simulated multiple VIP modules; wherein the connection relationship between the multiple VIP modules is the same as the connection relationship between the multiple functional components;

[0175] A determination module 503 is configured to determine, from the template library, test cases associated with the multiple VIP modules based on the connection relationship between the multiple VIP modules;

[0176] The testing module 504 is configured to test the paths between the multiple functional components using the multiple VIP modules based on the test case in the test environment.

[0177] In some embodiments, the test includes a path accuracy test between the multiple functional components; the test module 504 is also configured to simulate the data sending and receiving process between the multiple functional components based on the test case using the multiple VIP modules, and determine the accuracy of the path between the multiple functional components based on the consistency of the sent data and the received data.

[0178] In some embodiments, the test includes a path performance test between the multiple functional components; the test module 504 is also configured to utilize the multiple VIP modules to simulate the data sending and receiving process between the multiple functional components based on the test case, and determine the path performance between the multiple functional components based on the path parameters in the data sending and receiving process.

[0179] In some embodiments, the path parameter includes a bus bandwidth, the multiple VIP modules include a master VIP module for sending data and a slave VIP module for receiving data, the master VIP module is associated with one or more slave VIP modules, the configuration information also includes a data bit width and a clock frequency of a data sending component corresponding to the master VIP module, and the apparatus further includes:

[0180] a second determining module configured to determine a theoretical bus bandwidth between the master VIP module and a slave VIP module associated with the master VIP module based on a data bit width and a clock frequency of a data sending component corresponding to the master VIP module;

[0181] The test module 504 is also configured to determine the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to each slave VIP module associated with the master VIP module based on the theoretical bus bandwidth and the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module.

[0182] In some embodiments, the path parameters include bus bandwidth; the multiple VIP modules include multiple master VIP modules for sending data and slave VIP modules for receiving data; wherein, the slave VIP module is associated with the multiple master VIP modules; the test module 504 is also configured to determine the actual bus bandwidth between each master VIP module associated with the slave VIP module and the slave VIP module; determine the minimum bus bandwidth value among the multiple actual bus bandwidths of the multiple master VIP modules associated with the slave VIP module; based on the relationship between the minimum bus bandwidth value and the preset bus bandwidth threshold, determine the path performance between the data receiving component corresponding to the slave VIP module and each data sending component associated with the slave VIP module.

[0183] In some embodiments, the plurality of VIP modules include a master VIP module for sending data and a slave VIP module for receiving data; the apparatus further includes:

[0184] A second acquisition module is configured to acquire a preset delay time and / or transmission mode; wherein the delay time is the difference between the time when the slave VIP module receives the data sent by the master VIP module and the time when the slave VIP module feeds back a notification message of receiving the data to the master VIP module; and the transmission mode is the transmission mode in which the master VIP module sends data to the slave VIP module;

[0185] The test module 504 is further configured to utilize the multiple VIP modules based on the test case to simulate the data sending and receiving process between the multiple functional components simulated by the multiple VIP modules with the preset delay time and / or transmission method.

[0186] In some embodiments, the connection relationships between the multiple VIP modules include multiple groups of connection relationships, each group of connection relationships is associated with a test case; the apparatus further includes:

[0187] a setting module configured to determine a test case to be executed among the multiple test cases, and set the VIP module associated with the test case to be executed to an open state, and set the VIP module associated with the test case other than the test case to be executed to a closed state;

[0188] The test module 504 is further configured to start the test case to be executed, and use the multiple VIP modules in the enabled state to test the paths between the multiple functional components corresponding to the multiple VIP modules in the enabled state.

[0189] In some embodiments, the multiple functional components include a data sending component and a data receiving component, the configuration information also includes an address range for the data receiving component to receive data, and the apparatus further includes:

[0190] a selection module configured to randomly select a target address from the address range of the data receiving component;

[0191] The test module 504 is further configured to send data to the target address of the VIP module corresponding to the data receiving component based on the test case using the VIP module corresponding to the data sending component to test the path between the data sending component and the data receiving component.

[0192] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0193] Figure 6 This is a block diagram of an electronic device 600 according to an exemplary embodiment. For example, the electronic device 600 may be an integrated circuit test device, a user equipment (UE), a mobile device, a user terminal, a computing device, a cloud server, or other electronic device capable of forming a test environment for simulating the connection relationships between functional components on a chip.

[0194] Reference Figure 6 , the electronic device 600 may include one or more of the following components: a processing component 602 , a memory 604 , a power component 606 , a multimedia component 608 , an audio component 610 , an input / output (I / O) interface 612 , a sensor component 614 , and a communication component 616 .

[0195] The processing component 602 generally controls the overall operation of the electronic device 600, such as operations associated with at least one of display, phone calls, data communications, camera operation, and recording operations. The processing component 602 may include one or more processors 620 to execute instructions to perform all or part of the steps of the above-described method. In addition, the processing component 602 may include one or more modules to facilitate interaction between the processing component 602 and other components. For example, the processing component 602 may include a multimedia module to facilitate interaction between the multimedia component 608 and the processing component 602.

[0196] The memory 604 is configured to store various types of data to support operations on the electronic device 600. Examples of such data include at least one of the following: instructions for any application or method operating on the electronic device 600, contact data, phone book data, messages, pictures, and videos. The memory 604 can be implemented by any type of volatile or non-volatile storage device, or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk.

[0197] The power supply component 606 provides power to various components of the electronic device 600. The power supply component 606 may include at least one of the following: a power management system, one or more power supplies, and other components associated with generating, managing, and distributing power to the electronic device 600.

[0198] The multimedia component 608 includes a screen that provides an output interface between the electronic device 600 and the user. In some embodiments, the screen may include a liquid crystal display (LCD) and a touch panel (TP). If the screen includes a touch panel, the screen may be implemented as a touch screen to receive input signals from the user. The touch panel includes one or more touch sensors to sense touches, slides, and gestures on the touch panel. The touch sensor can not only sense the boundaries of a touch or slide action, but also detect the duration and pressure associated with the touch or slide operation. In some embodiments, the multimedia component 608 includes a front camera and / or a rear camera. When the electronic device 600 is in an operating mode, such as a shooting mode or a video mode, the front camera and / or the rear camera can receive external multimedia data. Each front camera and rear camera can be a fixed optical lens system or have focal length and optical zoom capabilities.

[0199] The audio component 610 is configured to output and / or input audio signals. For example, the audio component 610 includes a microphone (MIC), which is configured to receive external audio signals when the electronic device 600 is in an operating mode, such as a call mode, a recording mode, and a voice recognition mode. The received audio signal can be further stored in the memory 604 or transmitted via the communication component 616. In some embodiments, the audio component 610 also includes a speaker for outputting audio signals.

[0200] I / O interface 612 provides an interface between processing component 602 and peripheral interface modules, such as a keyboard, click wheel, and buttons. These buttons may include, but are not limited to, a home button, volume buttons, a start button, and a lock button.

[0201] The sensor assembly 614 includes one or more sensors for providing various aspects of the status assessment of the electronic device 600. For example, the sensor assembly 614 can detect the open / closed state of the electronic device 600, the relative positioning of components, such as the display and keypad of the electronic device 600. The sensor assembly 614 can also detect changes in the position of the electronic device 600 or a component thereof, the presence or absence of user contact with the electronic device 600, the orientation or acceleration / deceleration of the electronic device 600, and changes in the temperature of the electronic device 600. The sensor assembly 614 can include a proximity sensor configured to detect the presence of nearby objects without any physical contact. The sensor assembly 614 can also include an optical sensor, such as a complementary metal oxide semiconductor (CMOS) or charge coupled device (CCD) image sensor, for use in imaging applications. In some embodiments, the sensor assembly 614 can also include, but is not limited to, at least one of the following: an accelerometer, a gyroscope, a magnetic sensor, a pressure sensor, and a temperature sensor.

[0202] The communication component 616 is configured to facilitate communication between the electronic device 600 and other devices in a wired or wireless manner. The electronic device 600 can access a wireless network based on a communication standard, such as Wi-Fi, 4G, 5G, or a combination thereof. In an exemplary embodiment, the communication component 616 receives a broadcast signal or broadcast-related information from an external broadcast management system via a broadcast channel. In an exemplary embodiment, the communication component 616 also includes a near field communication (NFC) module to facilitate short-range communication. For example, the NFC module can be implemented based on radio frequency identification (RFID) technology, infrared data association (IrDA) technology, ultra-wideband (UWB) technology, Bluetooth (BT) technology and other technologies.

[0203] In an exemplary embodiment, the electronic device 600 may be implemented by one or more application specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field programmable gate arrays (FPGAs), controllers, microcontrollers, microprocessors, or other electronic components.

[0204] In an exemplary embodiment, a non-transitory computer-readable storage medium including instructions is further provided, such as a memory 604 including executable instructions or a computer program. The instructions or computer program can be executed by a processor 620 of the electronic device 600 to perform the above method. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a compact disc read-only memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0205] A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to perform any of the above-mentioned test methods of the embodiments of the present disclosure. For example, the method includes:

[0206] Obtaining configuration information of multiple functional components to be tested on the chip; wherein the configuration information includes a bus interface protocol of each functional component and a connection relationship between the multiple functional components;

[0207] Based on the bus interface protocol of each functional component in the configuration information, a verification intellectual property (VIP) module for simulating each functional component is determined from a preset template library, and a test environment is formed based on the connection relationship between the simulated multiple VIP modules; wherein the connection relationship between the multiple VIP modules is the same as the connection relationship between the multiple functional components;

[0208] Determining, from the template library, test cases associated with the multiple VIP modules based on the connection relationships between the multiple VIP modules;

[0209] In the test environment, based on the test case, the paths between the multiple functional components are tested using the multiple VIP modules.

[0210] The embodiments of the present disclosure provide a computer program product, which includes: a computer program or executable instructions, which are stored in a computer-readable storage medium. The processor of the electronic device reads the computer program or executable instructions from the computer-readable storage medium, and the processor executes the computer program or executable instructions, so that the electronic device performs any of the above-mentioned test methods of the embodiments of the present disclosure. Those skilled in the art will easily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the technical field that are not disclosed in the present disclosure. The description and embodiments are to be regarded as exemplary only, and the true scope and spirit of the present disclosure are indicated by the claims.

[0211] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A testing method, characterized in that: The method comprises: Obtaining configuration information of multiple functional components to be tested on the chip; wherein the configuration information includes a bus interface protocol of each functional component and a connection relationship between the multiple functional components; Based on the bus interface protocol of each functional component in the configuration information, a verification intellectual property (VIP) module for simulating each functional component is determined from a preset template library, and a test environment is formed based on the connection relationship between the simulated multiple VIP modules; wherein the connection relationship between the multiple VIP modules is the same as the connection relationship between the multiple functional components; Determining, from the template library, test cases associated with the multiple VIP modules based on the connection relationships between the multiple VIP modules; In the test environment, based on the test case, the paths between the multiple functional components are tested using the multiple VIP modules.

2. The method according to claim 1, characterized in that The testing includes testing the accuracy of paths between the plurality of functional components; The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes: Based on the test case, the data sending and receiving process between the multiple functional components is simulated using the multiple VIP modules, and based on the consistency of the sent data and the received data, the accuracy of the path between the multiple functional components is determined.

3. The method according to claim 1, characterized in that The test includes a path performance test between the plurality of functional components; The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes: Based on the test case, the data sending and receiving process between the multiple functional components is simulated using the multiple VIP modules, and based on the path parameters in the data sending and receiving process, the path performance between the multiple functional components is determined.

4. The method according to claim 3, characterized in that The path parameter includes a bus bandwidth, the multiple VIP modules include a master VIP module for sending data and a slave VIP module for receiving data, the master VIP module is associated with one or more slave VIP modules, the configuration information also includes a data bit width and a clock frequency of a data sending component corresponding to the master VIP module, and the method further includes: Determining a theoretical bus bandwidth between the master VIP module and a slave VIP module associated with the master VIP module based on a data bit width and a clock frequency of a data sending component corresponding to the master VIP module; The determining of the path performance between the plurality of functional components based on the path parameters during the data sending and receiving process includes: Based on the theoretical bus bandwidth and the actual bus bandwidth between the master VIP module and each slave VIP module associated with the master VIP module, the path performance between the data sending component corresponding to the master VIP module and the data receiving component corresponding to each slave VIP module associated with the master VIP module is determined.

5. The method according to claim 3, characterized in that The path parameter includes bus bandwidth; the multiple VIP modules include multiple master VIP modules for sending data and slave VIP modules for receiving data; wherein the slave VIP modules are associated with the multiple master VIP modules; The determining of the path performance between the plurality of functional components based on the path parameters during the data sending and receiving process includes: determining an actual bus bandwidth between each master VIP module associated with the slave VIP module and the slave VIP module; Determining a minimum bus bandwidth value among a plurality of actual bus bandwidths corresponding to a plurality of master VIP modules associated with the slave VIP module; Based on the relationship between the minimum bus bandwidth value and a preset bus bandwidth threshold, the path performance between the data receiving component corresponding to the slave VIP module and each data sending component associated with the slave VIP module is determined.

6. The method according to claim 3, characterized in that The plurality of VIP modules include a master VIP module for sending data and a slave VIP module for receiving data; the method further includes: Obtaining a preset delay time and / or transmission mode; wherein the delay time is the difference between the time when the slave VIP module receives the data sent by the master VIP module and the time when the slave VIP module feeds back a notification message of receiving the data to the master VIP module; the transmission mode is the transmission mode when the master VIP module sends data to the slave VIP module; The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes: Based on the test case, the multiple VIP modules are utilized to simulate the data sending and receiving process between the multiple functional components with the preset delay time and / or transmission mode.

7. The method according to any one of claims 1 to 6, characterized in that The connection relationships between the multiple VIP modules include multiple groups of connection relationships, each group of connection relationships is associated with a test case; the method further includes: Determine a test case to be executed among the multiple test cases, and set the VIP module associated with the test case to be executed to an open state, and the VIP module associated with the test case other than the test case to be executed to a closed state; The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes: The test case to be executed is started, and the paths between the multiple functional components corresponding to the multiple VIP modules in the turned-on state are tested using the multiple VIP modules in the turned-on state.

8. The method according to any one of claims 1 to 6, characterized in that The multiple functional components include a data sending component and a data receiving component, the configuration information also includes an address range for the data receiving component to receive data, and the method further includes: Randomly select a target address from the address range of the data receiving component; The testing of the paths between the multiple functional components using the multiple VIP modules based on the test case includes: Based on the test case, the VIP module corresponding to the data sending component is utilized to send data to the target address of the VIP module corresponding to the data receiving component to test the path between the data sending component and the data receiving component.

9. A testing device, characterized in that: The device comprises: A first acquisition module is configured to acquire configuration information of multiple functional components to be tested on the chip; wherein the configuration information includes a bus interface protocol of each functional component and a connection relationship between the multiple functional components; a formation module configured to determine, from a preset template library, a verification intellectual property (VIP) module for simulating each functional component based on a bus interface protocol of each functional component in the configuration information, and to form a test environment based on a connection relationship between the simulated plurality of VIP modules; wherein the connection relationship between the plurality of VIP modules is the same as the connection relationship between the plurality of functional components; a first determining module configured to determine, from the template library, test cases associated with the multiple VIP modules based on the connection relationships between the multiple VIP modules; The test module is configured to test the paths between the multiple functional components using the multiple VIP modules based on the test case under the test environment.

10. An electronic device, characterized in that: include: processor; memory for storing computer programs or instructions; The processor executes the computer program or instructions to implement the steps of the testing method according to any one of claims 1 to 8.

11. A non-transitory computer-readable storage medium storing a computer program or instruction, characterized in that: When the computer program or instructions in the storage medium are executed by a processor, the steps of the testing method according to any one of claims 1 to 8 are implemented.

12. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instructions are executed by a processor, the steps of the testing method according to any one of claims 1 to 8 are implemented.

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