Multi-input logic gate in-memory operational circuit based on 2T-2C ferroelectric storage unit

Abstract

The invention designs and provides a multi-input logic gate operation circuit and method based on a 2T-2C ferroelectric storage unit, and aims at solving the bottleneck of a traditional calculation framework and meeting the requirement of in-memory calculation for efficient multi-input logic. According to the circuit, a majority decision logic principle is applied, and an N input logic gate is realized by combining (2N-1) 2T-2C ferroelectric storage units. Wherein N units receive actual logic variables, and the remaining (N-1) units are preset to be in a fixed logic state ('0' or '1') according to a target logic function ('AND gate' or 'OR gate'). According to the design, function expansion is carried out by utilizing most of logic characteristics which are inherent formed by a small number of 2T-2C units. According to the method, multi-input AND and OR operation can be directly realized in the in-memory computing architecture efficiently and flexibly, the advantages of non-volatility, low power consumption and the like of a ferroelectric memory are inherited, and the integration level and the performance of logic operation are improved.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits and relates to a multi-input logic gate in-memory operation circuit based on a 2T-2C ferroelectric memory cell. Background Art

[0002] In digital systems, logic gates are the cornerstone of performing basic Boolean operations. Multi-input logic gates (MILGs), logic units capable of processing more than two input signals, are crucial for building complex computational functions. As applications such as artificial intelligence and big data increasingly demand computational complexity and parallelism, efficiently implementing MILGs directly within in-memory computing (IMC) architectures has become a key research direction for improving system performance and energy efficiency.

[0003] However, the efficient and reliable implementation of MILGs in IMC arrays based on emerging non-volatile memories (NVMs) faces significant challenges at the device, circuit, and system levels. Intrinsic device non-idealities, such as variability, noise, limited endurance and retention characteristics, and write defects, pose a serious threat to MILGs that rely on precise analog values ​​or multi-valued states. These effects are amplified in scenarios involving multi-input summation or comparison. At the circuit level, as the number of fan-in inputs increases, sensing margins decrease, parasitic effects increase, and the overhead and complexity of peripheral control and sensing circuits (such as ADCs / DACs) increase. Furthermore, each NVM technology (e.g., ReRAM, PCM, MRAM, FeFET, FRAM) has its own unique physical properties and limitations (e.g., low TMR for MRAM, resistance drift for PCM, high variability for ReRAM, and Vth control challenges for FeFETs), which necessitates that MILG designs be deeply coupled with specific memory technologies.

[0004] Currently, directly and efficiently implementing N-input logic functions (especially when N>2), rather than relying on the traditional cascade of two-input logic gates, remains a critical issue that needs to be addressed in the field of IMC. Ferroelectric memory cells, with their non-volatility, low power consumption, high speed, high durability, excellent CMOS compatibility, and relatively stable device characteristics, provide an attractive platform for building high-performance, high-reliability MILG-IMCs. Through innovative 2T-2C structural cell design and the utilization of majority logic principle circuit schemes, MILGs based on ferroelectric memory cells are expected to overcome the many obstacles faced by other NVM technologies in implementing complex parallel logic, thereby significantly improving the overall performance and flexibility of in-memory computing systems.

[0005] Existing technologies primarily focus on implementing basic two-input logic gates. For more complex multi-input logic gates (e.g., N-input AND gates or N-input OR gates, where N>2), existing solutions typically rely on decomposing these multi-input operations into a series of cascaded two-input logic gate operations. While feasible, this cascade approach significantly increases the overall latency of the operation, as each two-input logic operation requires one or more clock cycles to complete and may require storing temporary results in intermediate steps. This not only increases control complexity but may also partially offset the performance gains of in-memory computing. Therefore, current in-memory computing technologies based on ferroelectric memory cells still have limitations in directly and efficiently implementing multi-input logic functions, lacking a universal mechanism that can complete N-input logic operations within one or a few operation cycles.

[0006] This invention proposes, for the first time, a multi-input logic gate in-memory arithmetic circuit based on a 2T-2C ferroelectric memory cell and its method. This circuit utilizes the principle of majority logic to efficiently implement N-input AND and N-input OR logic operations directly within the memory array, thereby reducing the number of computation steps, lowering latency, and improving the overall performance and flexibility of the in-memory computing system. Therefore, the multi-input logic gate in-memory arithmetic circuit based on a 2T-2C ferroelectric memory cell proposed in this invention possesses advantages such as high efficiency, high flexibility, high reliability, high tolerance, and low power consumption, and is expected to be applied in artificial intelligence chips and AI neural networks. Summary of the Invention

[0007] This paper designs and proposes a multi-input logic gate in-memory operation circuit based on 2T-2C ferroelectric memory cells and its method. This circuit utilizes the principle of majority logic to efficiently implement N-input AND and N-input OR logic operations directly within the memory array, thereby reducing the number of operations and latency, and improving the overall performance and flexibility of the in-memory computing system.

[0008] The core idea of ​​the present invention is to use a 2T-2C ferroelectric memory cell array to implement a configurable N-input majority decision logic gate, and by presetting specific inputs of the majority decision logic gate, it is converted into an N-input "AND gate" or N-input "OR gate".

[0009] Majority Logic (MAJ) is defined as follows: for a set of binary inputs, if the number of logical "1s" is greater than the number of logical "0s," the output is a logical "1"; if the number of logical "0s" is greater than the number of logical "1s," the output is a logical "0." When the number of logical "1s" and logical "0s" is equal (which can only occur when the total number of inputs is even), the output can be defined based on the specific design. However, in the typical application of the present invention (using a majority gate with an odd number of total inputs), this situation does not affect the core functionality.

[0010] The present invention uses K input majority decision logic M (X1, X2, ..., X K ). When the number of logical "1"s among the K inputs is greater than K / 2, the output is logical "1", otherwise the output is logical "0". The multi-input logic gate in-memory operation circuit proposed by the present invention is based on a 2T-2C ferroelectric memory cell structure. Each 2T-2C cell contains two transistors (T) and two ferroelectric capacitors (C), one of which (the calculation capacitor) is connected to the bit line (BL) and the other (the reference capacitor) is connected to the complementary bit line (BLN). When writing data, the calculation capacitor and the reference capacitor store complementary polarization states.

[0011] To implement a K-input majority logic, K 2T-2C ferroelectric memory cells are selected. The calculated capacitances of these cells are all connected to the same bit line BL, and their reference capacitances are all connected to the same complementary bit line BLN. Assume that storing a logic "1" corresponds to contributing a higher charge (or voltage) on BL, and storing a logic "0" corresponds to contributing a lower charge (or voltage). When the word lines (WL) of these K cells are activated simultaneously, the charge (or resulting voltage change) corresponding to the data (logic "1" or "0") stored in the calculated capacitances of these cells accumulates on the bit line BL. Similarly, the charge corresponding to the complementary data stored in the reference capacitances accumulates on the complementary bit line BLN.

[0012] Since the calculation unit and the reference unit store complementary data, if the input is an input X of the majority logic gate, i is "1", then the corresponding calculated capacitance C BL(i) Contributes a "high" charge unit, and its reference capacitance C BLN(i) Contributes a "low" charge unit (relative to the complementary value of "1" "0"). Conversely, if the input X i If it is "0", then C BL(i) Contributing "low" charge, C BLN(i) Contributes a "high" charge.

[0013] Therefore, if the number of logical "1s" (N1) among the K inputs is greater than the number of logical "0s" (N0), the total equivalent charge (or voltage) on bit line BL will be higher than the total equivalent charge (or voltage) on the complementary bit line BLN. The latch-type sense amplifier connected to BL and BLN compares the voltage difference between the two bit lines and pulls the higher voltage end to the power supply voltage VDD and the lower voltage end to ground (GND). Therefore, if N1 > N0, the BL output is VDD (logical "1"); if N0 > N1, the BL output is GND (logical "0"). This directly implements the function of K-input majority logic.

[0014] It's worth noting that the practical number of inputs, K, in a majority logic gate is limited by physical factors, such as the total capacitance of the bit lines, the clarity of the charge contribution from individual cells, and the sensitivity and response speed of the sense amplifiers. As K increases, the ratio of the absolute charge difference required to distinguish between the majority and minority relative to the total background charge may decrease, increasing the accuracy requirements of the sensing circuit.

[0015] In order to realize an N-input AND gate (Y=A1·A2·...·A N ), the present invention sets the total number of inputs K of the majority decision logic gate to 2N-1. The specific configuration is as follows: the N input terminals of the (2N-1) input majority logic gate are connected to the N data input signals A1, A2, ..., A N The remaining (2N-1)-N=(N-1) inputs are fixed to logic "0". Therefore, the logical expression of the N-input "AND gate" can be expressed as:

[0016] Y=M(A1,A2,...,A N ,0,…,0)(The number of 0 is N-1) (1)

[0017] Logical analysis: The total number of inputs is K = 2N-1. If and only if all data inputs A1, A2, ..., A N When all are logic "1", the number of logic "1" in the total (2N-1) inputs is N, and the number of logic "0" is (N-1). Since N>N-1 (for N≥1), the output of most logic gates is logic "1". If any data input A i If the input is a logic "0," the maximum number of logic "1s" is (N-1) (when the other N-1 data inputs are all "1"), while the number of logic "0s" is at least (N-1) (from the fixed "0") + 1 (from the "0" data input) = N. In this case, the number of logic "1s" (≤N-1) is less than the number of logic "0s" (≥N), and the output of most logic gates is logic "0." This behavior is exactly the same as the truth table for an N-input AND gate.

[0018] For example, to implement a four-input AND gate Y = A·B·C·D, use a 2×4-1=7-input majority logic gate. Its input configuration is M(A,B,C,D,0,0,0). When A, B, C, and D are all "1," the inputs are (1,1,1,1,0,0,0). The number of logical "1s" is 4, and the number of logical "0s" is 3. Because 4>3, the output is "1." When at least one of A, B, C, and D is "0," for example, A = 0, B = C = D = 1, the inputs are (0,1,1,1,0,0,0). The number of logical "1s" is 3, and the number of logical "0s" is 4. Because 3<4, the output is "0."

[0019] In order to realize an N-input OR gate (Y=A1+A2+...+A N ), the present invention also sets the total number of inputs K of the majority decision logic gate to 2N-1. The specific configuration is as follows: the N input terminals of the (2N-1) input majority logic gate are connected to the N data input signals A1, A2, ..., A N The remaining (N-1) inputs are fixed to logic "1". Therefore, the logical expression of the N-input "OR gate" can be expressed as:

[0020] Y=M(A1,A2,...,A N ,1,…,1)(The number of 1 is N-1) (1)

[0021] Logical analysis: The total number of inputs is K = 2N-1. When all data are input into A1, A2, ..., A N When all are logic "0", the number of logic "0" in the total (2N-1) inputs is N, and the number of logic "1" is (N-1) (from the fixed "1"). Since N>N-1 (for N≥1), the output of most logic gates is logic "0". If any data input A i If the input is a logic "1," the number of logic "1s" is at least (N-1) (from the fixed "1") + 1 (from the data input that is "1") = N. At this point, the number of logic "0s" is at most (N-1) (when the other N-1 data inputs are all "0"). Because the number of logic "1s" (≥N) is greater than the number of logic "0s" (≤N-1), the output of most logic gates is a logic "1." This behavior is exactly the same as the truth table for an N-input OR gate.

[0022] For example, to implement a four-input OR gate Y = A + B + C + D, use a 2 × 4 - 1 = 7-input majority logic gate. Its input configuration is M(A, B, C, D, 1, 1, 1). When A, B, C, and D are all "0," the inputs are (0, 0, 0, 0, 1, 1, 1). The number of logical "1s" is 3, and the number of logical "0s" is 4. Because 3 < 4, the output is "0." When at least one of A, B, C, and D is "1," for example, A = 1, B = C = D = 0, the inputs are (1, 0, 0, 0, 1, 1, 1). The number of logical "1s" is 4, and the number of logical "0s" is 3. Because 4 > 3, the output is "1."

[0023] This approach uses a single majority logic operation to process N inputs and N-1 control bits in parallel, significantly reducing the number of operations and latency compared to the traditional approach, which requires N-1 cascades of two-input AND gates. Although the number of units involved in a single operation increases from 3 (for a two-input AND gate, such as M(A,B,0)) to (2N-1), its parallel nature provides performance advantages, especially for larger values ​​of N. This design represents a trade-off between unit resources and operational parallelism, increasing the number of units processed in parallel in exchange for an overall improvement in computational speed.

[0024] This symmetric implementation, by varying the logic values ​​of the (N-1) fixed control inputs ("0" for an AND gate, "1" for an OR gate) while maintaining the core (2N-1)-input majority logic operation mechanism, fully demonstrates the versatility of the majority logic framework for in-memory computing. This means that a general (2N-1)-input majority logic computation module (composed of (2N-1) 2T-2C units) can be dynamically configured to perform N-input AND operations or N-input OR operations simply by pre-programming the corresponding logic values ​​into the (N-1) "control" units. This reconfigurability provides powerful support for building flexible and efficient in-memory computing processors.

[0025] Beneficial effects of the present invention:

[0026] This paper designs and proposes a multi-input logic gate in-memory arithmetic circuit based on a 2T-2C ferroelectric memory cell, capable of performing N-input AND and N-input OR logic operations. Compared to other in-memory arithmetic cells, this multi-input logic gate in-memory arithmetic circuit offers advantages such as high efficiency, flexibility, reliability, robustness, and low power consumption. It is expected to promote the development of in-memory computing architectures and be applied to artificial intelligence chips and AI neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a structural diagram of a multi-input logic gate in-memory operation circuit.

[0028] Figure 2 It is a structural diagram of a circuit that implements two-input AND or OR in-memory operation.

[0029] Figure 3 It is a structural diagram of a three-input AND or OR in-memory operation circuit.

[0030] Figure 4 It is the waveform diagram of the simulation result of Example 1.

[0031] Figure 5 It is the waveform diagram of the simulation result of Example 2.

[0032] Figure 6 It is the waveform diagram of the simulation result of Example 3.

[0033] Figure 7 4 is a waveform diagram of the simulation result of Example 4.

[0034] Figure 8 4 is a waveform diagram of the simulation result of Example 5.

[0035] Figure 9 4 is a waveform diagram of the simulation result of Example 6.

[0036] Figure 10 4 is a waveform diagram of the simulation result of Example 7.

[0037] Figure 11 4 is a waveform diagram of the simulation result of Example 8.

[0038] Figure 12 4 is a waveform diagram of the simulation result of Example 9.

[0039] Figure 13 4 is a waveform diagram of the simulation result of Example 10.

[0040] Figure 14 1 is a waveform diagram of the simulation result of Example 11.

[0041] Figure 15 4 is a waveform diagram of the simulation result of Example 12. DETAILED DESCRIPTION

[0042] N-input AND circuit configuration and operation: Select (2N-1) 2T-2C ferroelectric memory cells. Pre-program N cells into data inputs A1,...,A N The remaining (N-1) ferroelectric memory cells are pre-programmed with logic "0." Subsequently, the word lines of these (2N-1) cells are activated simultaneously, and the voltage difference between BL and BLN is sensed by the sense amplifier to obtain the result of the N-input AND operation.

[0043] N-input OR circuit configuration and operation: Select (2N-1) 2T-2C ferroelectric memory cells. Pre-program N cells with data inputs A1,...,A N The remaining (N-1) ferroelectric memory cells are pre-programmed with logic "1." Subsequently, the word lines of these (2N-1) cells are activated simultaneously, and the voltage difference between BL and BLN is sensed by the sense amplifier to obtain the result of the N-input OR operation.

[0044] In order to make the purpose, technical solutions and advantages of the present invention more clear, the beneficial effects of the present invention will be further described below through twelve specific implementation plans:

[0045] Example 1:

[0046] The logic operation of "0 and 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses three 2T-2C ferroelectric memory cells A, B, C and a latch-type sensitive amplifier, such as Figure 2 shown.

[0047] The specific operation process is as follows: write 000 to the three 2T-2C ferroelectric units A, B, and C respectively, then turn on the three word lines of A, B, and C at the same time, and apply the PL pulse signal to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation result on BL and BLN. When C is 0, the "A and B" operation is performed. After the calculation, the BL line is low and the BLN is high. The calculation result is 0, which is consistent with the theoretical result of the "0 and 0" operation. The simulated waveform is shown in the figure below. Figure 4 shown.

[0048] Example 2:

[0049] The logic operation of "0 or 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses three 2T-2C ferroelectric memory cells A, B, C and a latch-type sense amplifier, such as Figure 2 shown.

[0050] The specific operation process is as follows: write 001 to the three 2T-2C ferroelectric units A, B, and C respectively, then turn on the three word lines of A, B, and C at the same time, and apply the PL pulse signal to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation result on BL and BLN. When C is 1, the "A or B" operation is performed. After the calculation, the BL line is low and the BLN is high. The calculation result is 0, which is consistent with the theoretical result of the "0 or 0" operation. The simulated waveform is shown in the figure below. Figure 5 shown.

[0051] Example 3:

[0052] The logic operation of "1 and 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses three 2T-2C ferroelectric memory cells A, B, C and a latch-type sensitive amplifier, such as Figure 2 shown.

[0053] The specific operation process is as follows: write 100 to the three 2T-2C ferroelectric units A, B, and C respectively, then turn on the three word lines A, B, and C at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation results on BL and BLN. When C is 0, the "A and B" operation is performed. After the calculation, the BL line is low and the BLN is high. The calculation result is 0, which is consistent with the theoretical result of the "1 and 0" operation. The simulated waveform is shown in the figure below. Figure 6 shown.

[0054] Example 4:

[0055] The logic operation of "1 or 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses three 2T-2C ferroelectric memory cells A, B, C and a latch-type sensitive amplifier, such as Figure 2 shown.

[0056] The specific operation process is as follows: write 101 to the three 2T-2C ferroelectric units A, B, and C respectively, then turn on the three word lines A, B, and C at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation results on BL and BLN. When C is 1, the "A or B" operation is performed. After the calculation, the BL line is high and the BLN is low. The calculation result is 1, which is consistent with the theoretical result of the "1 or 0" operation. The simulated waveform is shown in the figure below. Figure 7 shown.

[0057] Embodiment 5:

[0058] The logic operation of "1 and 1" is performed in the calculation circuit of the ferroelectric memory. The circuit uses three 2T-2C ferroelectric memory cells A, B, C and a latch-type sensitive amplifier, such as Figure 2 shown.

[0059] The specific operation process is as follows: write 110 to the three 2T-2C ferroelectric units A, B, and C respectively, then turn on the three word lines A, B, and C at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation results on BL and BLN. When C is 0, the "A and B" operation is performed. After the calculation, the BL line is high and the BLN is low. The calculation result is 1, which is consistent with the theoretical result of the "1 and 1" operation. The simulated waveform is shown in the figure below. Figure 8 shown.

[0060] Example 6:

[0061] The logic operation of "1 or 1" is performed in the calculation circuit of the ferroelectric memory. The circuit uses three 2T-2C ferroelectric memory cells A, B, C and a latch-type sensitive amplifier, such as Figure 2 shown.

[0062] The specific operation process is as follows: write 111 to the three 2T-2C ferroelectric units A, B, and C respectively, then turn on the three word lines A, B, and C at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation results on BL and BLN. When C is 1, the "A or B" operation is performed. After the calculation, the BL line is high and the BLN is low. The calculation result is 1, which is consistent with the theoretical result of the "1 or 1" operation. The simulated waveform is shown in the figure below. Figure 9 shown.

[0063] Embodiment seven:

[0064] The logic operation of "1 and 1 and 1" is performed in the calculation circuit of the ferroelectric memory. The circuit uses five 2T-2C ferroelectric memory cells A, B, C, D, E and a latch-type sensitive amplifier, such as Figure 3 shown.

[0065] The specific operation process is as follows: write 11100 to the five 2T-2C ferroelectric units A, B, C, D, and E respectively, then turn on the five word lines A, B, C, D, and E at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation results on BL and BLN. When D and E are both 0, the "A and B and C" operation is performed. After the calculation, the BL line is high and the BLN is low. The calculation result is 1, which is consistent with the theoretical result of the "1 and 1 and 1" operation. The simulated waveform is shown in the figure below. Figure 10 shown.

[0066] Embodiment 8:

[0067] The logic operation of "0 or 0 or 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses five 2T-2C ferroelectric memory cells A, B, C, D, E and a latch-type sense amplifier, such as Figure 3 shown.

[0068] The specific operation process is as follows: write 00011 to the five 2T-2C ferroelectric units A, B, C, D, and E respectively, then turn on the five word lines A, B, C, D, E, and F at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sensitive amplifier enable signal, and get the calculation results on BL and BLN. When D and E are 1, the "A or B or C" operation is performed. After the calculation, the BL line is low and the BLN is high. The calculation result is 0, which is consistent with the theoretical result of the "0 or 0 or 0" operation. The simulated waveform is shown in the figure below. Figure 11 shown.

[0069] Embodiment 9:

[0070] The logic operation of "1 and 1 and 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses five 2T-2C ferroelectric memory cells A, B, C, D, E and a latch-type sensitive amplifier, such as Figure 3 shown.

[0071] The specific operation process is as follows: write 11000 to the five 2T-2C ferroelectric units A, B, C, D, and E respectively, then turn on the five word lines A, B, C, D, and E at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation results on BL and BLN. When D and E are 0, the "A and B and C" operation is performed. After the calculation, the BL line is low and the BLN is high. The calculation result is 0, which is consistent with the theoretical result of the "1 and 1 and 0" operation. The simulated waveform is shown in the figure below. Figure 12 shown.

[0072] Embodiment 10:

[0073] The logic operation of "1 or 1 or 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses five 2T-2C ferroelectric memory cells A, B, C, D, E and a latch-type sensitive amplifier, such as Figure 3 shown.

[0074] The specific operation process is as follows: write 11011 to the five 2T-2C ferroelectric units A, B, C, D, and E respectively, then turn on the five word lines A, B, C, D, and E at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sensitive amplifier enable signal, and get the calculation results on BL and BLN. When D and E are 1, the "A or B or C" operation is performed. After the calculation, the BL line is high and the BLN is low. The calculation result is 1, which is consistent with the theoretical result of the "1 or 1 or 0" operation. The simulated waveform is shown in the figure below. Figure 13 shown.

[0075] Example 11:

[0076] The logic operation of "1 or 0 or 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses five 2T-2C ferroelectric memory cells A, B, C, D, E and a latch-type sense amplifier, such as Figure 3 shown.

[0077] The specific operation process is as follows: write 10011 to the five 2T-2C ferroelectric units A, B, C, D, and E respectively, then turn on the five word lines A, B, C, D, and E at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sensitive amplifier enable signal, and get the calculation results on BL and BLN. When D and E are 1, the "A or B or C" operation is performed. After the calculation, the BL line is high and the BLN is low. The calculation result is 1, which is consistent with the theoretical result of the "1 or 0 or 0" operation. The simulated waveform is shown in the figure below. Figure 14 shown.

[0078] Example 12:

[0079] The logic operation of "1 and 0 and 0" is performed in the calculation circuit of the ferroelectric memory. The circuit uses five 2T-2C ferroelectric memory cells A, B, C, D, E and a latch-type sensitive amplifier, such as Figure 3 shown.

[0080] The specific operation process is as follows: write 10000 to the five 2T-2C ferroelectric units A, B, C, D, and E respectively, then turn on the five word lines A, B, C, D, and E at the same time, and apply PL pulse signals to make them participate in the calculation, then turn on the sense amplifier enable signal, and get the calculation results on BL and BLN. When D and E are 0, the "A and B and C" operation is performed. After the calculation, the BL line is low and the BLN is high. The calculation result is 0, which is consistent with the theoretical result of the "1 and 0 and 0" operation. The simulated waveform is shown in the figure below. Figure 15 shown.

[0081] The above-described embodiments merely express the implementation methods of the present invention, but should not be understood as limiting the scope of the patent of the present invention. It should be pointed out that for those skilled in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all fall within the scope of protection of the present invention.

Claims

1. A multi-input logic gate operation circuit based on a 2T-2C ferroelectric memory cell, characterized in that: The circuit includes at least (2N-1) 2T-2C ferroelectric memory cells, where N is the number of logic gate input variables to be implemented and N≥2; each of the 2T-2C ferroelectric memory cells includes a pair of ferroelectric capacitors and corresponding selection transistors for storing complementary logic values, and is connected to a common plate line (PL), each independent word line (WL) and a shared bit line pair (BL / BLN); a sensitive amplifier is connected to the shared bit line pair (BL / BLN); wherein, when performing an N-input logic operation, (2N-1) cells are selected from the at least (2N-1) 2T-2C ferroelectric memory cells to participate in the operation, wherein N cells are used to store the N input logic variables and the remaining (N-1) cells pre-store fixed logic values; by simultaneously activating the word lines of the (2N-1) selected cells, a voltage signal corresponding to the input logic combination is generated on the shared bit line pair based on charge superposition, and the final N-input logic operation result is determined by the sensitive amplifier according to the majority decision logic principle.

2. The circuit according to claim 1, wherein: When implementing the N-input AND gate function, the (N-1) 2T-2C ferroelectric memory cells that pre-store fixed logic values ​​are all set to store logic "0". By simultaneously activating the word lines of the (2N-1) selected cells, a voltage signal corresponding to the input logic combination is generated on the shared bit line pair based on charge superposition. The final N-input "AND" logic operation result is determined by the sense amplifier according to the majority decision logic principle.

3. The circuit according to claim 1, wherein: When implementing an N-input OR gate, the (N-1) pre-stored fixed logic values ​​of the 2T-2C ferroelectric memory cells are all set to store a logic "1." By simultaneously activating the word lines of these (2N-1) selected cells, a voltage signal corresponding to the input logic combination is generated on the shared bit line pair based on charge superposition. The sense amplifier then determines the final N-input OR logic result using majority logic.

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