Non-volatile memory erase scheme

Abstract

The invention relates to a non-volatile memory erase scheme. Methods, systems, and devices provide techniques for erasing data in a memory device. The memory device includes a plurality of memory blocks. Each of the plurality of memory blocks includes a plurality of word line segments. Each of the plurality of word line segments includes one or more word lines forming a subset of word lines in the memory block. The memory device further includes a memory controller configured to perform: receiving an erase command for erasing data in the memory block; and in response to receiving the erase command, causing one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different periods such that when data erase begins at a first word line segment, data erase does not start at another word line segment.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to U.S. Provisional Application No. 63 / 564,952, filed on March 13, 2024, entitled “NON-VOLATILE MEMORY ERASE SCHEME,” the contents of which are incorporated by reference in their entirety for all purposes. Technical Field

[0003] The present disclosure relates to one or more systems for memory, including techniques for erasing data in memory devices. Background Art

[0004] Memory devices are widely used to store information in devices such as computers, user devices, wireless communication devices, cameras, digital displays, and others. Information is stored by programming memory cells within the memory device to various states. For example, a binary memory cell can be programmed to one of two supported states, typically represented by a logic 1 or a logic 0. In some examples, a single memory cell can support more than two states, either of which can be stored. To access stored information, a memory device can read (e.g., sense, detect, retrieve, determine) a state from a memory cell. To store information, a memory device can write (e.g., program, set, assign) a state to a memory cell. Information can also be erased from a memory cell and new information can be stored in the memory cell.

[0005] There are various types of memory devices, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase change memory (PCM), self-selecting memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described in terms of either a volatile configuration or a non-volatile configuration. Memory cells configured in a non-volatile configuration can maintain a stored logic state for an extended period of time, even in the absence of external power. Memory cells configured in a volatile configuration lose their stored state when disconnected from external power. Summary of the Invention

[0006] According to one aspect of the present disclosure, a memory device is provided. The memory device includes: a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of word line segments, wherein each of the plurality of word line segments includes one or more word lines forming a subset of the word lines in the memory block; and a memory controller configured to: receive an erase command for erasing data in the memory block; and, in response to receiving the erase command, cause one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different time periods, such that when data erasure begins at a first word line segment, data erasure does not begin at another word line segment.

[0007] According to another aspect of the present disclosure, a system is provided. The system includes: a processor; a memory device coupled to the processor, the memory device including: a plurality of memory blocks, wherein each of the plurality of memory blocks includes a plurality of word line segments, wherein each of the plurality of word line segments includes one or more word lines forming a subset of the word lines in the memory block; and a memory controller configured to: receive an erase command for erasing data in the memory block; and, in response to receiving the erase command, cause one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different time periods, such that when data erasure begins at a first word line segment, data erasure does not begin at another word line segment.

[0008] According to another aspect of the present disclosure, a memory device is provided. The memory device includes: a plurality of memory blocks, wherein each of the plurality of memory blocks includes one or more word line groups, wherein each of the one or more word line groups includes a plurality of word line segments including a plurality of word lines; and a memory controller configured to: prepare for electrical isolation of a memory pillar portion associated with a target word line group; electrically isolate the memory pillar portion associated with the target word line group from one or more memory pillar portions associated with one or more other word line groups; boost a voltage of the isolated memory pillar portion associated with the target word line group; and perform an erase operation for the target word line group using a voltage that is the same as or less than an erase voltage used for other word line groups in the memory block.

[0009] According to another aspect of the present disclosure, a system is provided. The system includes a processor; a memory device coupled to the processor, the memory device including: a plurality of memory blocks, wherein each of the plurality of memory blocks includes one or more word line groups, wherein each of the one or more word line groups includes a plurality of word line segments including a plurality of word lines; and a memory controller configured to: prepare for electrical isolation of a memory pillar portion associated with a target word line group; electrically isolate the memory pillar portion associated with the target word line group from one or more memory pillar portions associated with one or more other word line groups; boost a voltage of the isolated memory pillar portion associated with the target word line group; and perform an erase operation for the target word line group using a voltage that is the same as or less than an erase voltage used for other word line groups in the memory block. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and 1B Examples of host systems and memory systems supporting techniques for erasing data in memory devices according to examples disclosed herein are described.

[0011] Figure 1C is a block diagram of a memory device in communication with a memory system controller of a memory system according to examples disclosed herein.

[0012] Figures 2A to 2C is an illustrative schematic diagram of a portion of a memory cell array in a memory device according to examples disclosed herein.

[0013] Figure 2D An example of a memory device including multiple memory cell blocks according to examples disclosed herein is described.

[0014] Figure 3 is a block diagram of an example device for implementing one or more systems and for performing one or more methods described herein according to examples disclosed herein.

[0015] Figure 4 is a diagram illustrating an example of a voltage waveform for an erase pulse for a word line and one or more memory lines in a conventional manner.

[0016] Figure 5 is a diagram illustrating an example of voltage waveforms for reducing latency of erase operations in a memory device according to some embodiments.

[0017] Figure 6 is a diagram illustrating another example of a voltage waveform for reducing latency of an erase operation in a memory device according to some embodiments.

[0018] Figure 7The description shows a flow chart of an example method for reducing latency of erase operations in a memory device according to some embodiments.

[0019] Figure 8 and 9 The description shows a flow chart showing an example method for ramping word lines of different word line segments in different time periods, according to some embodiments.

[0020] Figure 10 The description shows a flow chart showing another example method for ramping word lines of different word line segments in different time periods, according to some embodiments.

[0021] Figure 11 is a diagram illustrating an example of a memory block including one or more word line groups according to some embodiments.

[0022] Figures 12A to 12C is a diagram illustrating an example method for reducing a maximum erase voltage in an erase operation in a memory device according to some embodiments.

[0023] Figure 13 is a diagram illustrating examples of voltage waveforms for performing erase operations on multiple word line segments in different time periods according to some embodiments.

[0024] Figure 14 The description shows a flow chart of an example method for reducing a maximum erase voltage in an erase operation in a memory device according to some embodiments.

[0025] Figure 15 The description shows a flowchart of an example method for preparing for electrical isolation of memory pillar portions, according to some embodiments.

[0026] Figure 16 The description shows a flow chart of an example method for electrically isolating memory pillar portions, according to some embodiments.

[0027] Figure 17 The description shows a flow chart of an example method for boosting the voltage of an isolated memory pillar portion according to some embodiments.

[0028] Figure 18 The description shows a flow chart of an example method for performing erase operations of a target group of word lines using word line segmentation, according to some embodiments. DETAILED DESCRIPTION

[0029] An erase operation is one of the operations commonly performed on a memory device. Typically, an erase operation is performed on a memory block, which is the smallest unit of an erase operation. A memory block may include multiple word line segments. Each of the word line segments may include one or more word lines. Conventionally, to erase a memory block, an erase pulse is applied such that the voltage of all word lines in the memory block remains at a low voltage, while the memory lines associated with the memory block are ramped up to an erase voltage (V era ). The erase voltage then remains level while the erase operation occurs and then ramps down during the recovery phase of the erase operation. During the erase pulse for the erase operation, the ramp-up period may be a sufficiently long period. No actual erase operation may occur until the ramp-up period is completed. Therefore, when the erase operation is performed block by block, this may result in a significant erase delay. The slope during the erase operation is limited by the gate induced drain leakage (GIDL) capability and load. GIDL generally refers to the leakage current flowing from the drain to the source of a transistor (such as a MOSFET) induced by the gate voltage when the transistor is in the off state. Each of the multiple memory blocks may include a large number of word lines (such as hundreds of word lines), so the load is quite large. Therefore, the erase operation will have a significant delay.

[0030] The long delay of the erase operation is usually not desirable. For example, when the memory controller issues a pause command, the erase operation is suspended. When the pause command is received, the erase operation cannot be completed and the erase pulse ramps down to resume. Typically, the erase pulse has a required minimum flat top period so that it does not ramp down immediately after receiving the pause command. After the erase pulse ramps down and other operations (such as reading, writing) are performed, the erase pulse needs to ramp up again to continue the interrupted erase operation. The ramping up of the erase pulse again causes a significant delay. In addition, if the overall delay of the erase operation is very long, then it increases the chance that another pause command can be received during the erase operation, and therefore increases the chance that the erase operation is interrupted again. Therefore, the long delay of the erase operation reduces the overall efficiency of the memory device operation.

[0031] According to various examples described in this disclosure, a memory controller uses a word line segmentation method to cause one or more erase pulses to be applied to multiple word line segments, causing word lines of different word line segments of a memory block to ramp up during different periods. Consequently, a large number of word lines can be divided into multiple word line segments. This reduces the load on the word line driver to ramp up the voltage of the word line. Consequently, the duration of the ramp-up period can be reduced, thereby reducing the latency of the erase operation and improving quality of service (QoS).

[0032] As described above, GIDL can occur in a memory device or any semiconductor device. A memory device or other semiconductor device may be a three-dimensional (3D) device having an increased number of layers or levels. A 3D device may have a higher capacity than a 2D device. In a typical 3D memory device, for example, multiple layers are stacked together with one or more memory pillars disposed vertically in between. The memory pillars may serve as the channel region of the memory device. The multiple layers or levels of a memory device may form a group or layer. The layers of a memory device may be processed together (e.g., patterned together) when forming their associated memory pillars. A layer or level of a memory device may have one or more word lines or groups of word lines. Each layer may have one or more word line segments. A word line segment may have fewer or more word lines than the number of word lines in a layer. For example, a layer may have two word line segments distributed across one or more layers. In some cases, an erase operation may be performed on a group of word lines (e.g., a layer) rather than an entire memory block. By not applying the erase operation to the entire memory block, the erase operation may be performed more quickly.

[0033] During the erase operation of a memory device, GIDL may introduce many positively charged electron holes (or simply holes), which may enter the memory pillars of the memory block. The erase operation is affected by the GIDL effect, which causes electron holes to enter the memory pillars. For a 3D memory device having many layers forming multiple word line groups or layers, some portions of the memory pillars (such as interface portions between word line groups or layers and positioned away from the bit lines or common source (SRC) lines) may have a weaker GIDL effect than other groups or layers. This may be caused by the processing of the device, as the doping levels of certain portions of the memory pillars may vary due to process variations. In these portions of the memory pillars, the GIDL effect may be weak. During an erase operation, a high erase voltage (such as Vera=20V) is applied to the bit line or SRC line and portions of the memory pillars close to the bit line or SRC line may also have the same high voltage (such as 20V), while other portions further away from the bit line or SRC line may have a lower voltage (such as 18V) due to the weaker GIDL effect. When a portion of the memory pillar has a voltage higher than the erase voltage (V era ) When the voltage is low, there may not be enough voltage difference to perform an erase operation. In order to perform an erase operation, the bit line voltage will need to be increased, but doing so will cause reliability problems.

[0034] In the present disclosure, a memory controller prepares for electrical isolation of memory pillar portions associated with a target word line group, electrically isolates the memory pillar portions associated with the target word line group, and raises the voltage of the isolated memory pillar portions. Thus, there is no need to increase the bit line voltage to be greater than the erase voltage to compensate for voltage loss in a particular memory pillar portion caused by a weaker GIDL effect. The target word line group can then perform an erase operation using a voltage that is the same as or less than the erase voltage. The disclosed method and structure thus mitigate or eliminate the effects of the weaker GIDL effect, reduce errors in erase operations, and enhance the reliability of the memory device.

[0035] Figure 1A An example of a system 100 supporting techniques for erasing data in a memory device according to examples disclosed herein is illustrated. The system 100 includes a host system 105 coupled to a memory system 110. The system 100 can be included in a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (such as an airplane, drone, train, car, or other transportation), an Internet of Things (IoT)-enabled device, an embedded computer (such as an embedded computer included in a vehicle, industrial equipment, or a networked commercial device), or any other computing device that includes a memory and a processing device.

[0036] The memory system 110 may be or include any device or set of devices, wherein the device or set of devices includes at least one memory array. For example, the memory system 110 may be or include a universal flash storage (UFS) device, an embedded multimedia controller (eMMC) device, a flash device, a universal serial bus (USB) flash device, a secure digital (SD) card, a solid-state drive (SSD), a hard disk drive (HDD), a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), or a non-volatile DIMM (NVDIMM), among other devices.

[0037] System 100 may include a host system 105 that may be coupled to memory system 110. In some examples, this coupling may include an interface with a host system controller 106, which may be an example of a controller or control component configured to cause host system 105 to perform various operations according to the examples described herein. Host system 105 may include one or more devices and, in some cases, may include a processor chipset and a software stack executed by the processor chipset. Host system 105 may be comprised of, for example, Figure 3300 is implemented as shown in FIG. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to or included in the host system 105), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a Peripheral Component Interconnect Express (PCIe) controller, a Serial Advanced Technology Attachment (SATA) controller). For example, the host system 105 may use the memory system 110 to write data to the memory system 110 and read data from the memory system 110. Although Figure 1A One memory system 110 is shown in FIG. 1 , but the host system 105 may be coupled to any number of memory systems 110 .

[0038] The host system 105 can be coupled to the memory system 110 via at least one physical host interface. In some cases, the host system 105 and the memory system 110 can be configured to communicate via the physical host interface using an associated protocol (e.g., to exchange or otherwise transfer control, address, data, and other signals between the memory system 110 and the host system 105). Examples of physical host interfaces can include, but are not limited to, a SATA interface, a UFS interface, an eMMC interface, a PCIe interface, a USB interface, a Fibre Channel interface, a Small Computer System Interface (SCSI), a Serial Attached SCSI (SAS), a Double Data Rate (DDR) interface, a Graphics Double Data Rate (GDDR) interface, a DIMM interface (e.g., a DDR-capable DIMM slot interface), an Open NAND Flash Interface (ONFI), and a Low Power Double Data Rate (LPDDR) interface. In some examples, one or more such interfaces can be included in or otherwise supported between the host system controller 106 of the host system 105 and the memory system controller 115 of the memory system 110. In some examples, the host system 105 may be coupled to the memory system 110 via a respective physical host interface of each memory device 130 included in the memory system 110 or via a respective physical host interface of each type of memory device 130 included in the memory system 110 (e.g., the host system controller 106 may be coupled to the memory system controller 115).

[0039] The memory system 110 may include a memory system controller 115 and one or more memory devices 130. The memory device 130 may include one or more memory arrays of any type of memory cells, such as non-volatile memory cells, volatile memory cells, or any combination thereof. Figure 1A, two memory devices 130-a and 130-b are shown in the example of , but memory system 110 may include any number of memory devices 130. Furthermore, if memory system 110 includes more than one memory device 130, different memory devices 130 within memory system 110 may include the same or different types of memory cells.

[0040] The memory system controller 115 can be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and can be an example of a controller or control component configured to cause the memory system 110 to perform various operations according to the examples described herein. The memory system controller 115 can also be coupled to and communicate with the memory devices 130 to perform operations such as reading data, writing data, erasing data, or refreshing data, and other such operations at the memory devices 130, which can be collectively referred to as access operations. In some cases, the memory system controller 115 can receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within the one or more memory devices 130). For example, the memory system controller 115 can receive commands or operations from the host system 105 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and one or more memory devices 130 (e.g., in response to or otherwise associated with commands from the host system 105). For example, the memory system controller 115 may convert responses associated with the memory devices 130 (e.g., data packets or other signals) into corresponding signals for the host system 105.

[0041] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling operations, garbage collection operations, error control operations (e.g., error detection operations or error correction operations), encryption operations, cache operations, media management operations, background refresh, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the memory device 130.

[0042] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memory, or a combination thereof. The hardware may include circuitry having dedicated (e.g., hard-coded) logic to perform the operations attributed herein to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry such as a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), a digital signal processor (DSP), or any other suitable processor or processing circuitry.

[0043] The memory system controller 115 may also include local memory 120. In some cases, the local memory 120 may include read-only memory (ROM) or other memory that may store operating code (e.g., executable instructions) that may be executed by the memory system controller 115 to perform the functions attributed herein to the memory system controller 115. In some cases, the local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that may be used by the memory system controller 115, for example, for internal storage or computations related to the functions attributed herein to the memory system controller 115.

[0044] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase change memory (PCM), self-select memory, other chalcogenide-based memory, ferroelectric random access memory (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM), or any combination thereof. Additionally or alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include RAM memory cells, such as dynamic RAM (DRAM) memory cells and synchronous DRAM (SDRAM) memory cells.

[0045] In some examples, the memory devices 130 may include (e.g., on the same semiconductor die or within the same package) a local controller 135 that may perform operations on one or more memory cells of the respective memory devices 130. The local controller 135 may operate in conjunction with the memory system controller 115 or may perform one or more functions attributed herein to the memory system controller 115. For example, Figure 1AAs described in the examples of the present disclosure (e.g., Figure 1C In the example shown in FIG, local controller 135 is disposed on the same semiconductor die as the memory array (e.g., array 104), and separate memory system controller 115 is disposed on a different die. In other examples, some portions of memory device 130 may be disposed on a first die, and other portions of memory device 130 may be disposed on a second die different from the first die. For example, the first die may include memory cell array 104 and its associated circuitry, such as column decoder 111 and row decoder 108. The second die may include logic circuitry, power circuitry, or other circuitry of device 130. Thus, the second die may include system controller 115, I / O control 112, etc. In this example, the first die does not have a local controller, and the second die includes system controller 115. The first and second dies may be hybrid-bonded together using, for example, through-hole vias (TSVs) to electrically connect them. The first and second dies may also be wafer-bonded using flip-chip bonding techniques, etc. In this disclosure, both the memory system controller 115 and the local controller 135 may be referred to as memory controllers or simply as the first memory controller and the second memory controller. It should be understood that although they may be different controllers, unless otherwise specified, certain operations disclosed herein may be caused or performed by either or both memory controllers.

[0046] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a die 160 (e.g., a memory die). For example, in some cases, memory device 130 may be a package that includes one or more die 160. In some examples, die 160 may be a piece of electronic-grade semiconductor cut from a wafer (e.g., a silicon die cut from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding memory blocks 170, where each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0047] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as single-level cells (SLC). Additionally or alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information, which may be referred to as multi-level cells (MLC) when configured to each store two bits of information, triple-level cells (TLC) when configured to each store three bits of information, quad-level cells (QLC) when configured to each store four bits of information, or more generally, multi-level memory cells. Multi-level memory cells may provide greater storage density relative to SLC memory cells, but in some cases may involve narrower read or write margins or greater complexity for supporting circuitry.

[0048] In some cases, a plane 165 may refer to several groups of memory blocks 170, and in some cases, concurrent operations may be performed on different planes 165. For example, concurrent operations may be performed on memory cells within different blocks 170, as long as the different blocks 170 are in different planes 165. In some cases, individual memory blocks 170 may be referred to as physical blocks, and a virtual block 180 may refer to a group of blocks 170 within which concurrent operations may occur. For example, concurrent operations may be performed on blocks 170-a, 170-b, 170-c, and 170-d within planes 165-a, 165-b, 165-c, and 165-d, respectively, and blocks 170-a, 170-b, 170-c, and 170-d may be collectively referred to as a virtual block 180. In some cases, a virtual block may include blocks 170 from different memory devices 130 (e.g., blocks in one or more planes including memory device 130-a and memory device 130-b). In some cases, blocks 170 within a virtual block may have the same block address within their respective planes 165 (e.g., block 170-a may be "block 0" of plane 165-a, block 170-b may be "block 0" of plane 165-b, and so on). In some cases, performing concurrent operations in different planes 165 may be subject to one or more restrictions, such as performing concurrent operations on memory cells in different pages 175 that have the same page address within their respective planes 165 (e.g., related to command decoding, page address decoding circuitry, or other circuitry shared across planes 165).

[0049] In some cases, block 170 may include memory cells organized into rows (pages 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., be coupled to a common word line), and memory cells in the same string may share a common digit line (which may alternatively be referred to as a bit line) (e.g., be coupled to a common digit line). Example memory cell structures are shown in more detail below using illustrative schematics.

[0050] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first granularity (e.g., at a page granularity or portions thereof) but can be erased at a second granularity (e.g., at a block granularity). That is, a page 175 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently programmed or read (e.g., concurrently programmed or read as part of a single program or read operation), and a memory block 170 can be the smallest unit of memory (e.g., a group of memory cells) that can be independently erased (e.g., concurrently erased as part of a single erase operation). Furthermore, in some cases, a NAND memory cell can be erased before it can be rewritten with new data. Thus, for example, in some cases, a used page 175 cannot be updated until the entire block 170 containing the page 175 is erased.

[0051] In some cases, an L2P (logical to physical) mapping table may be maintained and data may be marked as valid or invalid at a page granularity level, and a page 175 may contain valid data, invalid data, or no data. Invalid data may be data that may be outdated because a newer or updated version of the data is stored in a different page 175 of the memory device 130. Invalid data may have been previously programmed to an invalid page 175 but may no longer be associated with a valid logical address, such as a logical address referenced by the host system 105. Valid data may be the latest version of this data stored on the memory device 130. A page 175 that contains no data may be a page 175 that has never been written to or has been erased.

[0052] In some cases, memory system 110 may utilize memory system controller 115 to provide a managed memory system, which may include, for example, one or more memory arrays and associated circuitry in combination with a local (e.g., on-die or in-package) controller, such as local controller 135. An example of a managed memory system is a managed NAND (MNAND) system.

[0053] The system 100 may include any number of non-transitory computer-readable media that support techniques for logical-to-physical table compression. For example, the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135) may include or otherwise have access to one or more non-transitory computer-readable media that store instructions (e.g., firmware, logic, code) for performing the functions attributed herein to the host system 105, the memory system 110, or the memory device 130. For example, such instructions, when executed by the host system 105 (e.g., host system controller 106), the memory system 110 (e.g., memory system controller 115), or the memory device 130 (e.g., local controller 135), may cause the host system 105, the memory system 110, or the memory device 130 to perform the associated functions described herein.

[0054] In some cases, memory system 110 may compress the L2P map to expand the number of physical addresses mapped by the L2P map. For example, if a group of consecutive entries of an uncompressed L2P map include consecutive physical addresses, memory system 110 may compress the consecutive entries into a single entry that includes the starting physical address of the consecutive physical addresses. Additionally, memory system 110 may include an indication of a starting logical address corresponding to the starting physical address in the compressed entry. To identify a physical address within the compressed entry, memory system 110 may use the indication to determine an offset between a logical address corresponding to the physical address (e.g., a logical address included in a read command for data stored at the physical address) and the starting physical address, and may apply the offset to the starting physical address to determine the physical address. Compressing the L2P map may allow the L2P map to cover an expanded range of the physical address space without increasing the size of the L2P map.

[0055] Figure 1B An example of a system diagram 101 illustrating communication between a host system 105 and a memory system 110 using a kernel and firmware according to examples disclosed herein is shown. System diagram 101 may include memory system 110, kernel 107, and application 109. Memory system 110 may include firmware 119. Firmware 119 may be provided by a controller and / or other circuitry (e.g., a processor) of the memory system. Figure 1A 10 and / or local controller 135). In some examples, as described herein, system 123 may include memory system 110 and kernel 107. Additionally, host system 105 may include kernel 107 and application 109.

[0056] As described above, the memory system 110 may include multiple memory devices configured to store and retrieve data, including non-volatile memory devices and volatile memory devices (such as local memory 120). Firmware 119 may refer to the firmware stored in Figure 1A 10 (e.g., non-volatile memory devices within the memory system 110) and / or the memory array within the local memory 120 shown in FIG. 10. The firmware 119 may provide low-level control functions for the memory system 110. For example, the firmware 119 may serve as an interface between the memory system 110 and other components of the system 123, and the host system 105 may issue access operations to the memory system 110 by interfacing with the firmware 119. In some examples, the firmware 119 may be or be included within or implemented by the memory system controller 115, as described herein with reference to FIG. Figure 1A Description. In some examples, the memory system 110 may store a logical-to-physical mapping that maps logical addresses to physical addresses within a non-volatile memory device (e.g., in a logical-to-physical table). To perform a memory access operation, the memory system 110 may move a portion of the logical-to-physical mapping corresponding to one or more logical addresses (e.g., as indicated by the kernel 107) from a non-volatile memory device to a volatile memory device.

[0057] The kernel 107 may serve as an interface between the host system 105 and components associated with the host system 105, such as the operating system of the host system 105. Furthermore, the kernel 107 may perform resource allocation and file management, among other operations, for the host system 105. For example, an application 109 running within the host system 105 may access information stored within the memory system 110 by issuing a command to the kernel 107 indicating a file to be accessed. The kernel 107 may store mapping information associated with the file. For example, a file may be associated with a file name and may correspond to a range of logical block addresses. The kernel 107 may store mapping information (e.g., a mapping table) that tracks the logical block addresses corresponding to files on the host system 105. In some examples, the application 109 may issue an access command to the kernel 107 indicating the file name, offset, and length associated with the file to be accessed, and the kernel 107 may retrieve one or more logical block addresses corresponding to the file to be accessed. The kernel 107 may then communicate with the firmware 119 to indicate the one or more logical block addresses to the memory system 110, and the memory system 110 may perform access operations based on the one or more logical block addresses.The memory system 110 may communicate the access information to the kernel 107 (eg, via the firmware 119).

[0058] In some examples, kernel 107 may communicate with firmware 119 using information units, such as UFS Protocol Information Units (UPIUs). For example, kernel 107 may issue or receive commands, responses, data, or other information via information units exchanged with firmware 119. An information unit may refer to a data packet that may contain a header segment and one or more transaction-specific fields. In some examples, an information unit may additionally include one or more extended header segments, one or more data segments, or a combination thereof. The header segment of an information unit may indicate information associated with the destination of the information unit, the source of the information unit, a function request, whether additional data or parameters will be transmitted, whether the additional data or parameters are included within the information unit or will be sent in the next information unit, or any combination thereof. Transaction-specific fields may be used for additional fields depending on the operation associated with the information unit. The data segment may be used to include data to be transferred from one device to another.

[0059] In some examples, a command information unit (e.g., a command UPIU) may be an example of an information unit associated with the transmission of a command (e.g., a SCSI command) and may instruct a device to perform a certain operation indicated by the command information unit. For example, the command information unit may include a block descriptor (e.g., a command descriptor block) that may indicate information related to the operation indicated by the command information unit. In some examples, the kernel 107 may transmit the command information unit to the memory system 110 to indicate to the memory system 110 the operation to be performed by the memory system 110.

[0060] In some examples, to perform an access operation, the memory system 110 may load an L2P map associated with the information to be accessed. For example, the memory system 110 may transfer a portion of a logical-to-physical map associated with the information to be accessed from a non-volatile memory device (e.g., NAND memory) of the memory system 110 to a volatile memory device (e.g., SRAM) of the memory system 110. In another example, the host system 105 may notify the memory system 110 of a logical block address range corresponding to an upcoming access operation (e.g., before issuing an access command). The memory system 110 may use the logical block address range to load (e.g., preload, prefetch) the associated portion of the L2P map (e.g., from the non-volatile memory device to the volatile memory device) before receiving an access command instructing the memory system 110 to perform the access operation. Additionally, after the host system 105 issues an access command, the memory system 110 may issue a response to the host system 105 more quickly because the memory system 110 has already loaded the relevant portion of the L2P map associated with the access operation.

[0061] The above description of system diagram 101 is an illustrative example of communication between host system 105 and memory system 110 using kernel 107, application 109, and firmware 119. It should be understood that additional communication methods including function calls, commands, responses, messages, etc. can be implemented using host system 105 and memory system 110 and / or additional systems or components.

[0062] Figure 1C is in accordance with an embodiment with a memory system (e.g. Figure 1A and 1B A simplified block diagram of a memory device 130 communicating with a memory system controller 115 of a memory system 110. Figure 1C As shown in FIG and described in more detail below, memory device 130 includes a memory cell array 104 that is logically arranged into rows and columns. Memory cells of a logical row are typically connected to the same access line (e.g., a word line), while memory cells of a logical column are typically selectively connected to the same data line (e.g., a bit line). A single access line can be associated with more than one logical row of memory cells and a single data line can be associated with more than one logical column. Memory cells of at least a portion of memory cell array 104 ( Figure 1C ) can be programmed into one of at least two target data states for storing any number of bits of information.

[0063] Continue to refer Figure 1C , row decoding circuitry 108 and column decoding circuitry 111 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 112 for managing the input of commands, addresses, and data to memory device 130, as well as the output of data and status information from memory device 130. Address registers 144 communicate with I / O control circuitry 112 and row decoding circuitry 108 and column decoding circuitry 111 to latch address signals prior to decoding. Row decoding circuitry 108 and column decoding circuitry 111 may be referred to simply as row decoder 108 and column decoder 111, respectively. Command register 124 communicates with I / O control circuitry 112 and local controller 135 to latch incoming commands.

[0064] A memory controller (e.g., a local controller 135 within the memory device 130) controls access to the memory cell array 104 in response to commands and generates status information for the external memory system controller 115. That is, the local controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the memory cell array 104. The local controller 135 communicates with the row decoding circuitry 108 and the column decoding circuitry 111 to control the row decoding circuitry 108 and the column decoding circuitry 111 according to addresses.

[0065] Local controller 135 also communicates with cache registers 118 and data registers 121. In some embodiments, one or more cache registers 118 may collectively form at least a portion of a cache buffer. Cache registers 118, under the direction of local controller 135, latch or buffer incoming or outgoing data to temporarily store data while memory cell array 104 is busy writing or reading other data, respectively. During a programming operation (e.g., a write operation), data may be transferred from cache register 118 to data register 121 for transmission to memory cell array 104; then, the new data may be latched into cache register 118 from I / O control circuitry 112. During a read operation, data may be transferred from cache register 118 to I / O control circuitry 112 for output to memory system controller 115; then, the new data may be transferred from data register 121 to cache register 118. In some embodiments, cache register 118 and / or data register 121 may form at least a portion of page buffer 152 of memory device 130. Page buffer 152 may further include a sensing device, such as a sense amplifier, for sensing the data state of a memory cell in memory cell array 104, for example, by sensing the state of a data line connected to the memory cell. Status register 122 may communicate with I / O control circuitry 112 and local media controller 135 to latch status information for output to memory system controller 115.

[0066] like Figure 1C , memory device 130 receives various control signals from memory system controller 115 via local controller 135 via control link 132. For example, the control signals may include chip enable signal CE#, command latch enable signal CLE, address latch enable signal ALE, write enable signal WE#, read enable signal RE#, and write protect signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received via control link 132. In one embodiment, memory device 130 receives command signals (which represent commands), address signals (which represent addresses), and data signals (which represent data) from memory system controller 115 via multiplexed input / output (I / O) bus 134 and outputs the data to memory system controller 115 via I / O bus 134.

[0067] For example, a command may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then may be written into command register 124. An address may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] of I / O bus 134 and then may be written into address register 144. Data may be received at I / O control circuitry 112 via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device and then may be written into cache register 118. The data may then be written into data register 121 for programming memory cell array 104.

[0068] In an embodiment, cache register 118 may be omitted and data may be written directly to data register 121. Data may also be output via input / output (I / O) pins [7:0] for an 8-bit device or input / output (I / O) pins [15:0] for a 16-bit device. Although reference may be made to I / O pins, these may include any conductive node, such as a conventional conductive pad or conductive bump, that provides an electrical connection to memory device 130 by an external device (e.g., memory system controller 115). Although the above description uses a 16-bit I / O bus 134 as an example, it should be understood that bus 134 may be configured for any number of bits (e.g., 64 bits).

[0069] It will be appreciated by those skilled in the art that additional circuitry and signals may be provided, and Figure 1C The memory device 130 has been simplified. It should be recognized that the reference Figure 1C The functionality of the various block components described is not necessarily separated into distinct components or component portions of an integrated circuit device. For example, a single component or component portion of an integrated circuit device may be adapted to perform Figure 1C Alternatively, one or more components or component parts of an integrated circuit device may be combined to perform Figure 1C Additionally, while specific I / O pins are described according to general conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0070] Figures 2A to 2B FIG. 2 is an example schematic diagram of a portion of a memory cell array 200A, such as a NAND memory array. The memory cell array 200A may be a reference array according to an embodiment of the present invention. Figure 1C 1. An example of a memory array 104 of a memory device 130 is depicted. Memory array 200A includes access lines (e.g., word lines 2020 through 202 N) and data lines (eg, bit lines 2040 to 204 M ). The word lines 202 may be connected to global access lines (eg, global word lines) in a many-to-one relationship ( Figure 2A For some embodiments, memory array 200A may be formed over a semiconductor, which may be doped to have a conductivity type, such as p-type conductivity, such as for forming a p-well, or n-type conductivity, such as for forming an n-well.

[0071] The memory array 200A may be arranged into rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column may include a string of memory cells (eg, nonvolatile memory cells) connected in series, such as NAND strings 2060-206 M Each NAND string 206 can be connected (eg, selectively connected) to a common source (SRC) 216 and can include memory cells 2080-208 N The memory cells 208 may represent non-volatile memory cells for data storage. The memory cells 208 of each NAND string 206 may be connected in series to a select gate 210 (eg, a field effect transistor) (eg, select gates 2100 to 2101). M One of the transistors (eg, which may be a source select transistor, often referred to as a select gate source) and a select gate 212 (eg, a field effect transistor) (eg, select gates 2120 to 212 M One of the select gates 2100 to 210 is connected to the drain select transistor 2100. M The gates 2120 to 2121 may be connected in common to a select line 214 (eg, a source select line (SGS)). M 2 and 3. The select gates 210 and 212 may be commonly connected to a select line 215 (e.g., a drain select line (SGD)). Although depicted as conventional field effect transistors, the select gates 210 and 212 may utilize a similar (e.g., identical) structure as the memory cell 208. The select gates 210 and 212 may represent a plurality of select gates connected in series, wherein each select gate in the series is configured to receive the same or an independent control signal.

[0072] The source of each select gate 210 can be connected to a common source 216. The drain of each select gate 210 can be connected to a memory cell 2080 of a corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to a memory cell 2080 of a corresponding NAND string 2060. Thus, each select gate 210 can be configured to selectively connect a corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to a select line 214.

[0073] The drain of each select gate 212 can be connected to the bit line 204 of the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to the bit line 2040 of the corresponding NAND string 2060. The source of each select gate 212 can be connected to the memory cell 208 of the corresponding NAND string 206. N For example, the source of the select gate 2120 may be connected to the memory cell 208 of the corresponding NAND string 2060. N Thus, each select gate 212 can be configured to selectively connect a corresponding NAND string 206 to a corresponding bit line 204 . The control gate of each select gate 212 can be connected to a select line 215 .

[0074] Figure 2A The memory array 200A in can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, where the common source 216, NAND strings 206, and bit lines 204 extend in substantially parallel planes. Alternatively, Figure 2A The memory array 200A in FIG. 2 can be a three-dimensional memory array, for example, where the NAND strings 206 can extend substantially perpendicular to a plane containing the common source 216 and can extend substantially parallel to a plane containing the bit lines 204 .

[0075] The typical structure of the memory cell 208 includes a data storage structure 234 (e.g., a floating gate, a charge trap, and the like) that can determine the data state of the memory cell (e.g., by a change in threshold voltage) and a control gate 236, such as Figure 2A 2. The data storage structure 234 may include both conductive and dielectric structures, with the control gate 236 typically formed of one or more conductive materials. In some cases, the memory cell 208 may further have a defined source / drain (e.g., source) 230 and a defined source / drain (e.g., drain) 232. The memory cell 208 has its control gate 236 connected to (and in some cases forming) the word line 202.

[0076] A column of memory cells 208 may be one NAND string 206 or several NAND strings 206 that are selectively connected to a given bit line 204. A row of memory cells 208 may be the memory cells 208 that are commonly connected to a given word line 202. A row of memory cells 208 may, but need not, include all of the memory cells 208 that are commonly connected to a given word line 202. Rows of memory cells 208 may typically be divided into one or more groups of physical pages of memory cells 208, and a physical page of memory cells 208 typically includes every other memory cell 208 that is commonly connected to a given word line 202. For example, a row of memory cells 208 may be commonly connected to a word line 202. NThe memory cells 208 selectively connected to the even bit lines 204 (eg, bit lines 2040, 2042, 2044, etc.) may be a physical page of memory cells 208 (eg, even memory cells) and are commonly connected to the word line 202. N And the memory cells 208 selectively connected to the odd bit lines 204 (eg, bit lines 2041 , 2043 , 2045 , etc.) may be another physical page of memory cells 208 (eg, odd memory cells).

[0077] Despite Figure 2A The bit lines 2043 to 2045 are not explicitly depicted in the figure, but it is obvious from the figure that the bit lines 204 of the memory cell array 200A can be numbered consecutively from bit line 2040 to bit line 204. M . Other groupings of memory cells 208 commonly connected to a given word line 202 may also define a physical page of memory cells 208. For a particular memory device, all of the memory cells commonly connected to a given word line may be considered a physical page of memory cells. A portion (which may still be an entire row in some embodiments) of a physical page of memory cells (e.g., an upper page or lower page of memory cells) that is read during a single read operation or programmed during a single program operation may be considered a logical page of memory cells. A block of memory cells may include those memory cells that are configured to be erased together, such as those connected to word lines 2020 through 202. N All memory cells of a common word line 202 (e.g., all NAND strings 206 that share a common word line 202). Unless explicitly distinguished, references herein to a page of memory cells refer to memory cells of a logical page of memory cells. A logical page may or may not be the same as a physical page. Although Figure 2A The examples are discussed in conjunction with NAND flash, but the embodiments and concepts described herein are not limited to a particular array architecture or structure, but may include other structures (such as SONOS, phase change, ferroelectric, etc.) and other architectures (such as AND arrays, NOR arrays, etc.).

[0078] Figure 2B Can be used for reference Figure 1B Another schematic diagram of a portion of a memory cell array 200B in a memory device (eg, as part of memory cell array 104) is depicted. Figure 2B Like numbered elements in FIG. 1 correspond to those in FIG. 1 and FIG. 2 . Figure 2A Provide a description. Figure 2BAdditional details are provided for one example of a three-dimensional NAND memory array structure. The three-dimensional NAND memory array 200B can incorporate a vertical structure that can include semiconductor pillars, where a portion of the pillars can serve as channel regions for memory cells of a NAND string 206. The NAND strings 206 can each be selectively connected to bit lines 2040 through 204 through select transistors 212 (e.g., which can be drain select transistors, often referred to as select gate drains). M The NAND strings 206 are connected to a common source 216 through a select transistor 210 (e.g., which may be a source select transistor, often referred to as a select gate source). Multiple NAND strings 206 may be selectively connected to the same bit line 204. A subset of the NAND strings 206 may be selected by biasing select lines 2150 to 2155. K Each word line 202 is connected to its corresponding bit line 204 to selectively activate a particular select transistor 212 located between each NAND string 206 and the bit line 204. The select transistors 210 can be activated by biasing the select line 214. In some embodiments, each sub-block or string of memory cells has a separate select line 214 from the other sub-blocks or strings. In some embodiments, a pair of sub-blocks share a single select line 214. Each word line 202 can be connected to multiple rows of memory cells in the memory array 200B. The rows of memory cells commonly connected to each other by a particular word line 202 can be collectively referred to as a tier.

[0079] The three-dimensional NAND memory array 200B may include multiple stacked layers of memory cell hierarchies connected using vertical channels (e.g., semiconductor pillars). For example, the number of layers in the three-dimensional NAND memory array 200B may be 32, 48, 64, 96, 112, or any other number of layers. In some examples, groups of layers may be collectively referred to as layers. Layers in a three-dimensional NAND memory array may be processed together (e.g., etched together to form a portion of a semiconductor pillar). A memory device having a three-dimensional NAND memory array may provide more memory cells on a single chip than a memory device formed with a two-dimensional NAND array, and thus provide higher storage capacity. Furthermore, in a memory device having a three-dimensional NAND memory array, the transistors in the memory cells are spaced apart, thereby reducing interference and electron leakage.

[0080] As described above, memory cells can be grouped into memory blocks. Figure 2C Depicts the grouping of NAND strings 206 into memory cell blocks 250, such as memory cell blocks 2500 through 250. L. A memory cell block 250 can be a grouping of memory cells 208 that can be erased together in a single erase operation. A group of memory cells that can be erased together is also referred to as an erase block. Each memory cell block 250 can represent those NAND strings 206 that are typically associated with a single select line 215 (e.g., select line 2150). The common source 216 of a memory cell block 2500 can be the same as the common source 216 of the memory cell block 250. L For example, each memory cell block 2500 to 250 L The access line 202 and the select lines 214 and 215 of one memory cell block 250 may not be directly connected to the memory cell blocks 2500 to 2500, respectively. L The access line 202 and select lines 214 and 215 of any other memory cell block in the memory cell block.

[0081] Bit lines 2040 to 204 M The buffer portion 240 may be connected (eg, selectively connected) to the buffer portion 240, which may be part of the page buffer 152 of the memory device 130. The buffer portion 240 may correspond to a memory plane (eg, memory cell blocks 2500 to 250 L Buffer portion 240 may include sensing circuitry (which may include sense amplifiers) for sensing the data value indicated on the corresponding bit line 204.

[0082] Figure 2D is a block diagram of a portion of an example memory cell array 260. The memory cell array 260 may be used as a reference. Figure 1C 1. The memory cell array 260 is depicted as having four memory planes 261 (eg, memory planes 261a through 261d). Each of the memory planes 261 may correspond to Figure 1A Each memory plane 261 can communicate with a corresponding buffer portion 240 that can collectively form a page buffer 262. The page buffer 262 can be used to implement Figure 1C 1. Although four memory planes 261 are depicted, other numbers of memory planes 261 may collectively communicate with the page buffers 262. Each memory plane 261 is depicted as including L+1 memory cell blocks 250 (e.g., memory cell blocks 2500 to 2501). L ).

[0083] Continue to refer Figure 1C and 2A To 2C, during a true erase operation (during which the memory cells are actually erased), the local controller 135 (eg, using the erase operation manager 137) may cause the common source voltage line (eg, SRC 216 ( Figure 2A )) Select gate 2100 to 210 M (SGS transistor) is turned on by the erase pulse ramping to the erase voltage (V ERA ). Ramping to this high bias erase voltage and then recovering from this voltage ramp requires a significant amount of time. Concurrently, the erase operation manager 137 may cause the selection gates 2120 to 212 m ( Figure 2A ) is disconnected to select gates 2120 to 212 m The drain of the bit line 2040 to 204 is able to float, which causes the bit line 2040 to 204 M Also floated. In addition, the erase operation manager 137 can Figure 2A ) is coupled to ground (eg, 0 volts) or word line 202 is held at a low voltage. This set of voltage levels at memory array 200A can produce an erase potential that causes memory cells 2080-208 N is erased, for example, by forcing electrons to exit through the body of each memory cell and off the floating bit lines 2040 to 204 M In other embodiments, the selection gates 2100 to 210 M disconnected, causing the SRC line 216 to float, while the select gates 2120 to 212 M When turned on, the voltage of the bit line is ramped to Vera. As mentioned earlier, in 3D NAND, one of the channel region, pillar, or bit line can also be ramped to cause the erase of the attached memory cell. Therefore, for simplicity herein, reference to a "memory line" should be understood as reference to any of the SRC line or bit line in 2D NAND or any of the channel, pillar, or bit line in 3D NAND. In some embodiments, one or more sub-blocks (including physical blocks) of memory cells are erased during the same true erase operation. A block of memory cells can generally be understood to include four or more sub-blocks, where each sub-block includes a separate string of memory cells.

[0084] A high-level block diagram of an example device 300 that can be used to implement the systems, devices, and methods described herein is provided in Figure 3 It will be understood that the various systems, apparatus, and methods described herein can be implemented using analog and / or digital circuitry or using one or more computers utilizing well-known computer processors, memory systems, storage devices, computer software, and other components. Typically, a computer includes a processor for executing instructions and one or more memory devices for storing instructions and data. A computer may also include or be coupled to one or more mass storage devices, such as one or more magnetic disks, internal hard disks and removable disks, magneto-optical disks, optical disks, and the like.

[0085] The various systems, devices, and methods described herein can be implemented using computers operating in a client-server relationship. Typically, in such a system, a client computer is remotely located from a server computer and interacts via a network. The client-server relationship can be defined and controlled by computer programs running on the respective client and server computers. Examples of client computers can include desktop computers, workstations, laptop computers, cellular smartphones, tablet computers, or other types of computing devices.

[0086] The various systems, devices, and methods described herein can be implemented using a computer program product tangibly embodied in an information carrier (e.g., in a non-transitory machine-readable storage device) for execution by a programmable processor; and the method processes and steps described herein (including one or more of at least some of the steps in Figures 1 to 18) can be implemented using one or more computer programs that can be executed by such a processor. A computer program is a set of computer program instructions that can be used directly or indirectly in a computer to perform a specific activity or cause a specific result. A computer program can be written in any form of programming language (including compiled or interpreted languages), and it can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0087] like Figure 3 As shown in FIG, apparatus 300 may be used to implement a system comprising, coupled to, or utilizing a memory system (e.g., Figure 1A A host system (eg, a memory system 110) Figure 1A The device 300 can be used to execute the operations of the controller (e.g., to execute an operating system to execute the corresponding Figure 1A operation of the host system controller 106 and / or local controller 135).

[0088] In some embodiments, the apparatus 300 includes a processor 310 operatively coupled to a data storage device 320 and a main memory device 330. The processor 310 controls the overall operation of the apparatus 300 by executing computer program instructions 324 that define such operation. The instructions 324 include instructions for implementing the controller (e.g., Figure 1A The computer program instructions 324 may be stored in a data storage device 320 or other computer readable medium and loaded into a main memory device 330 when execution of the computer program instructions is desired. For example, the processor 310 may be used to implement one or more components and systems described herein, such as the host system controller 106 and / or the local controller 135 ( Figure 1A1-18 ). Thus, at least some of the method steps of Figures 1-18 may be defined by computer program instructions 324 stored in the main memory device 330 and / or the data storage device 320 and controlled by the processor 310 executing the computer program instructions 324. For example, the computer program instructions 324 may be implemented as computer executable code programmed by one skilled in the art to perform the algorithms defined by the method steps discussed herein in conjunction with at least some of Figures 1-18 . Thus, by executing the computer program instructions, the processor 310 executes the algorithms defined by the method steps of these aforementioned figures to perform operations (e.g., reading, programming, erasing, etc.). The device 300 also includes one or more network interfaces 380 for communicating with other devices via a network. The device 300 may also include one or more input / output devices 390 (e.g., a display, keyboard, mouse, speaker, buttons, etc.) that enable user interaction with the device 300.

[0089] The processor 310 may include both general-purpose and special-purpose microprocessors and may be the sole processor of the apparatus 300 or one of multiple processors. The processor 310 may include one or more central processing units (CPUs) and one or more graphics processing units (GPUs). For example, a GPU may operate separately from and / or multitask with one or more CPUs to accelerate processing, such as for the various image processing applications described herein. The processor 310, the data storage device 320, and / or the main memory device 330 may include, be supplemented by, or be incorporated into one or more application-specific integrated circuits (ASICs) and / or one or more field-programmable gate arrays (FPGAs).

[0090] The data storage device 320 and the main memory device 330 each include a tangible, non-transitory computer-readable storage medium. The data storage device 320 and the main memory device 330 may each include a high-speed random access memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM), double data rate synchronous dynamic random access memory (DDR RAM), or other random access solid-state memory devices), and may include non-volatile memory, such as one or more magnetic disk storage devices (e.g., internal hard disk and removable disk), magneto-optical disk storage devices, optical disk storage devices, flash memory devices (NAND memory devices, NOR memory devices), semiconductor memory devices (e.g., erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), compact disk read-only memory (CD-ROM), digital versatile disk read-only memory (DVD-ROM) disks), or other non-volatile solid-state storage devices. For example, the data storage device 320 may use the memory system 110 ( Figure 1A) implementation. In some examples, the data storage device 320 and the main memory device 330 may include one or more memory devices 130 ( Figure 1A ).

[0091] Input / output devices 390 may include peripheral devices such as printers, scanners, display screens, etc. For example, input / output devices 390 may include a display device such as a cathode ray tube (CRT), a plasma or liquid crystal display (LCD) monitor for displaying information to a user, a keyboard, and a pointing device (such as a mouse or trackball) through which a user can provide input to apparatus 300.

[0092] Any or all of the functionality of the systems and devices discussed herein may be performed by processor 310 and / or incorporated into a device or system, such as system 100. Furthermore, system 100 and / or device 300 may utilize one or more neural networks or other deep learning techniques performed by processor 310 or other systems or devices discussed herein.

[0093] Those skilled in the art will recognize that actual computer or computer system implementations may have other structures and may contain other components, and Figure 3 is a high-level representation of some of this computer's components for illustration purposes.

[0094] Figure 4 is a diagram illustrating an example of a typical voltage waveform for an erase pulse 400 for a word line and one or more memory lines (eg, memory pillars). Figure 1A The memory device 130 shown in FIG. 1 includes a plurality of memory blocks (e.g. Figure 1A Each of the plurality of memory blocks includes a plurality of word lines (e.g., Figures 2A to 2C The word lines shown in 2020 to 202 N ) and one or more memory lines associated with a plurality of word lines. As described above, a memory line refers to any of an SRC line or a bit line in a 2D NAND or any of a channel, a pillar, or a bit line in a 3D NAND.

[0095] like Figure 4 As shown in FIG, in a conventional manner, during an erase operation of a memory block having multiple word lines, the voltages of the multiple word lines (V wl ) is maintained at a first voltage V1 during the erase pulse 400. The first voltage V1 is a low voltage. In some embodiments, the first voltage may be a ground voltage (e.g., 0 volts) or a small positive or negative voltage. In contrast, during the erase pulse 400, one or more memory lines (V mlThe voltage waveform of the memory line includes a ramp-up period 410, a plateau period 420, and a ramp-down period 430. During the ramp-up period 410, the voltage of the memory line is ramped from the first voltage V1 to the erase voltage V era As described above, the erase voltage V era It is a high voltage that provides a sufficiently high voltage bias to the memory cell string to cause the memory cell to be erased. Figure 4 As shown in FIG, the first voltage V1 is greater than the erase voltage V era is much lower so that when an erase operation is performed, a sufficiently high voltage bias exists between the plurality of word lines and one or more memory lines associated with the plurality of word lines. Therefore, once the memory line is ramped to the erase voltage V era , the data stored in the memory cells attached to the memory lines are erased during the plateau period 420. After the memory cells are erased, one or more memory lines can be quickly discharged to recover. Figure 4 As shown in FIG, during the ramp-down period 430, the voltage (V ml ) quickly ramps down to the first voltage V1.

[0096] like Figure 4 As shown in FIG, the ramp-up period 410 is a relatively long period in which there is no actual erase operation. For example, for a 2ms long erase pulse 400, the ramp-up period 410 may be about 500us. The slope is limited by the gate induced drain leakage (GIDL) capability and the load. The GIDL effect is a band-to-band tunneling effect. For semiconductor devices, when the band bending at the oxide interface is greater than or equal to the energy band gap of the drain material, electrons in the valence band of the n-type drain tunnel through the thinned band gap into the conduction band, and the remaining holes flow into one or more memory pillars. As shown in FIG. Figure 4 Display, V GIDL is the difference between the voltage of the bit line and the voltage of the SGD line (i.e., V GIDL =V BL -V SGD ) or the difference between the voltages of the SRC line and the SGS line (i.e., V GIDL =V SRC -V SGS ).like Figure 4 Assume that the voltage of the bit line / SRC line (V BL / SRC ) and the voltages of the SGD and SGS lines both start at the same low voltage (e.g., 0V), then there is no difference between them. GIDL When the voltage of the bit line / SRC line increases and reaches the threshold voltage (given by Figure 4 V in GIDL), GIDL current is generated and the memory pillar is charged. Thereafter, the voltage of the SGD and SGS lines begins to increase at the same or similar rate or slope as the voltage of the bit line / SRC line, thereby maintaining GIDL current generation. Figure 4 The slope of the period 410 is related to the voltage V BL / SRC The slope of the erase voltage V is the same or similar. As described above, each of the plurality of memory blocks may include a large number of word lines (e.g., several hundred word lines). Therefore, the load may be considerable. Therefore, one or more memory lines associated with the large number of word lines are ramped up to the erase voltage V era A large amount of time is required, which results in a significant erase delay when the erase operation is applied block by block. Therefore, there is a need to reduce the delay of the erase operation to improve the quality of service (QoS).

[0097] Figure 5 is a diagram illustrating an example of a voltage waveform for reducing the latency of an erase operation in a memory device according to some embodiments. Figure 1A The memory device 130 shown in FIG. 1 includes a plurality of memory blocks (e.g. Figure 1A 170 shown in FIG. 170). Each of the plurality of memory blocks includes a plurality of word line segments. Each of the plurality of word line segments includes one or more word lines that form a subset of the word lines in the memory block. Figure 5 In some embodiments shown in FIG, a plurality of word line segments are divided into two word line segments, such as a first word line segment and a second word line segment. In some embodiments, the plurality of word line segments are divided into four word line segments, eight word line segments, or any other number of word line segments. Thus, a large number of word lines (e.g., hundreds of word lines) can be divided into a plurality of word line segments so that the number of word lines in a word line segment is relatively small, thereby reducing the load of ramping.

[0098] The memory device further includes a memory controller (eg, a memory controller) configured to control voltages of the plurality of word lines and one or more memory lines associated with the plurality of word lines to perform an erase operation. Figure 1A and 1C The memory controller receives an erase command (e.g., from a host system) for erasing data in a memory block. In response to receiving the erase command, the memory controller causes one or more erase pulses to be applied to the plurality of word line segments. Figure 5 As shown in FIG, the memory controller causes word lines of different word line segments to ramp up during different periods, so that when data erasure begins at the first word line segment, data erasure does not begin at the second word line segment. Similarly, when data erasure begins at the second word line segment, data erasure does not begin at the first word line segment. Thus, data erasure can be performed in an alternating manner. Consequently, reducing the load shortens the ramp-up period, thereby reducing the latency of the erase operation.

[0099] In some embodiments, to erase multiple word line segments, the memory controller may apply multiple erase pulses. The memory controller causes each of the multiple erase pulses to be applied to a corresponding word line segment in the multiple word line segments in a sequential manner. In any of the different time periods, data erasure occurs only at one word line segment in the multiple word line segments. Figure 5 , there are two erase pulses, for example, a first erase pulse and a second erase pulse. During the first erase pulse, data erase occurs at the first word line segment. During the second erase pulse, data erase occurs at the second word line segment.

[0100] like Figure 5 As shown in the left side of FIG, during the first erase pulse, the memory controller maintains the word line of the first word line segment at a first voltage V1 (section 510). The first voltage V1 is a low voltage, such as Figure 5 As shown in the figure, below the erase voltage V era In some embodiments, the first voltage may be a ground voltage (eg, 0 volts), a small positive or negative voltage.

[0101] like Figure 5 As shown in section 511 of FIG, during the ramp-up period of the first erase pulse, the memory controller causes one or more memory lines associated with the plurality of word line segments to move toward the erase voltage V era Ramp up. Erase voltage V era is a sufficiently high voltage for erasing data in the memory block. The memory controller also causes the word lines of the second word line segment to ramp toward the second voltage V2 (section 512). Figure 5 As shown in FIG. 1 , the second voltage V2 is a voltage higher than the first voltage V1. In some embodiments, the second voltage may or may not be equal to the erase voltage V era .like Figure 5 , the ramping of the word lines of the second word line segment (segment 512) can be performed together with the ramping of one or more memory lines (segment 511). In this ramping scheme, the load on the word lines using only the first word line segment is less than the load on the word lines using both the first and second word line segments. As a result, the ramping period is reduced, thereby reducing the latency of the erase operation. For example, for a large number of word lines split into two word line segments (e.g., hundreds of word lines in each of multiple memory blocks), the ramping period can be reduced from 500 μs to 300 μs. When the same number of word lines is split into four word line segments, the ramping period can be reduced to approximately 200 μs. When eight word line segments are used, the ramping period can be reduced to approximately 150 μs, and so on.

[0102] like Figure 5 As shown in FIG, during the plateau period of the first erase pulse, the memory controller maintains one or more memory lines associated with the plurality of word line segments at approximately an erase voltage Vera For at least a threshold period (segment 513), data erasure begins at the first word line segment. Figure 5 , during the flat-top period, the memory controller also maintains the word line of the second word line segment at about a second voltage V2 (segment 514). Because there is no sufficiently high voltage bias in the word line of the second word line segment, data erasure does not start at the second word line segment.

[0103] like Figure 5 , during the ramp-down period of the first erase pulse, the memory controller causes one or more memory lines associated with the plurality of word line segments to ramp down (segment 515). The memory controller also causes the word lines of the second word line segment to ramp down (segment 516). As a result, the one or more memory lines and the word lines of the second word line segment are discharged and recovered.

[0104] like Figure 5 As shown in the right side of FIG, during the second erase pulse, the memory controller maintains the word lines of the second word line segment at the first voltage V1 (section 520). Similarly, during the ramp-up period of the second erase pulse, the memory controller causes one or more memory lines associated with the plurality of word line segments to ramp toward the erase voltage V era The memory controller then causes the word lines of the first word line segment to ramp toward the second voltage V2 (section 522). Figure 5 As shown in FIG, in some embodiments, the ramping of the word line of the first word line segment (segment 522) can be performed together with the ramping of one or more memory lines (segment 521). Similarly, the load on the word line using only the second word line segment is less than the load on the word line using both the first and second word line segments. As a result, the ramping period is reduced, thereby reducing the latency of the erase operation.

[0105] Similar to Figure 5 On the left side of the second erase pulse, during the plateau period of the second erase pulse, the memory controller maintains one or more memory lines associated with the plurality of word line segments at approximately an erase voltage V era The memory controller maintains the word line of the first word line segment at approximately the second voltage V2 for at least a threshold period (segment 523), causing data erasure to begin at the second word line segment. The memory controller also maintains the word line of the first word line segment at approximately the second voltage V2 during the plateau period (segment 524). Because there is no sufficiently high voltage bias in the word line of the first word line segment, data erasure does not begin at the first word line segment.

[0106] like Figure 5 , during the ramp-down period of the second erase pulse, the memory controller causes one or more memory lines associated with the plurality of word line segments to ramp down (section 525). The memory controller also causes the word lines of the first word line segment to ramp down (section 526). As a result, the one or more memory lines and the word lines of the first word line segment are discharged and recovered.

[0107] Figure 6 is a diagram illustrating another example of a voltage waveform for reducing the latency of an erase operation in a memory device according to some embodiments. Figure 5 The memory device in the memory device (eg Figure 1A The memory device 130 shown in FIG. 1 includes a plurality of memory blocks (e.g. Figure 1A 170 shown in FIG. 170). Each of the plurality of memory blocks includes a plurality of word line segments. Each of the plurality of word line segments includes one or more word lines that form a subset of the word lines in the memory block. Figure 6 In some embodiments shown in FIG, a plurality of word line segments are divided into two word line segments, such as a first word line segment and a second word line segment. In some embodiments, a plurality of word line segments are divided into four word line segments, eight word line segments, or any other number of word line segments. Two word line segments are used for illustration, but the same or similar methods or principles can be applied to other numbers of word line segments.

[0108] The memory device further includes a memory controller (eg, a memory controller) configured to control voltages of the plurality of word lines and one or more memory lines associated with the plurality of word lines to perform an erase operation. Figure 1A and 1C In response to receiving the erase command, the memory controller receives an erase command for erasing data in the memory block. Figure 6 As shown in FIG, the memory controller causes one erase pulse to be applied to multiple word line segments. Figure 6 , during one erase pulse, the first and second word line segments are ramped up at different time periods, so that when data erasure starts at the first word line segment, data erasure does not start at the second word line segment. Similarly, when data erasure starts at the second word line segment, data erasure does not start at the first word line segment.

[0109] Specifically, if Figure 6 As shown in FIG. 6 , during an erase pulse, the memory controller first maintains the word line of the first word line segment at a first voltage V1 (section 601). The first voltage V1 is a low voltage, such as Figure 6 As shown in the figure, below the erase voltage V era In some embodiments, the first voltage may be a ground voltage (eg, 0 volts) or a small positive or negative voltage. Figure 6 As shown in FIG, during the erase pulse ramp-up period, the memory controller causes one or more memory lines associated with a plurality of word line segments to move toward the erase voltage V era Ramp up (section 602). Erase voltage V erais a sufficiently high voltage for erasing data in the memory block. The memory controller also causes the word lines of the second word line segment to ramp toward a second voltage V2 (section 603). The second voltage V2 is a higher voltage than the first voltage V1. In some embodiments, the second voltage may or may not be equal to the erase voltage V era .like Figure 6 As shown in FIG, the ramping of the word lines of the second word line segment can be performed together with the ramping of one or more memory lines. In this scheme, the load on the word lines using only the first word line segment is less than the load on the word lines using both the first and second word line segments. As a result, the ramping period is reduced, thereby reducing the latency of the erase operation. For example, for a large number of word lines split into two word line segments (e.g., hundreds of word lines in each of multiple memory blocks), the ramping period can be reduced from 500 μs to 300 μs.

[0110] like Figure 6 As shown in FIG, during the erase pulse plateau period, the memory controller maintains one or more memory lines associated with a plurality of word line segments at approximately an erase voltage V era (Section 604) causes data erasure to begin at the first word line segment. During the erase pulse plateau period, while the word line of the first word line segment remains at the first voltage V1, the memory controller causes the word line of the second word line segment to ramp down toward a third voltage V3 (Section 605). The third voltage V3 is a voltage higher than the first voltage V1 and lower than the second voltage V2. During this period, data erasure occurs only at the first word line segment. In contrast, because there is no sufficiently high voltage bias in the word line of the second word line segment, data erasure does not begin at the second word line segment.

[0111] like Figure 6 As shown in FIG, the memory controller further causes the voltage of the word line of the first word line segment to ramp up toward the third voltage V3 (section 606). Then, the memory controller causes the word line of the second word line segment to continue to ramp down toward approximately the first voltage V1 (section 607). In this scheme, in order to quickly ramp down the word line of the second word line segment (e.g., Figure 6 , the slope of segment 607 is much steeper than the slope of segment 605), charge stored between the word line of the first word line segment and the one or more memory lines moves between the word line of the second word line segment and the one or more memory lines.

[0112] like Figure 6 , after the voltage of the word line of the second word line segment is ramped down to about the first voltage V1, the memory controller causes the word line of the second word line segment to remain at about the first voltage V1 (section 608), so that data erasure begins at the second word line segment. In some embodiments, the memory controller also causes the voltage of the word line of the first word line segment to ramp down toward about the first voltage V1 (section 609). Figure 6As shown in FIG, due to charge movement, the slope of the word line ramp down (segment 609) for the first word line segment can be the same as the slope of the word line ramp down (segment 605) for the second word line segment. Figure 6 As shown in section 610 of FIG, the memory controller maintains the word lines of the second word line segment at about the first voltage V1 so that data erasure can again occur at the first word line segment. As shown in section 604, during the erase pulse plateau period of one erase pulse, the memory controller can maintain one or more memory lines associated with the plurality of word line segments at about the erase voltage V era for a sufficient period of time to complete erasing the data at the first word line segment and the second word line segment.

[0113] Finally, during the erase pulse ramp-down period, the memory controller causes one or more memory lines associated with the plurality of word line segments to ramp down (section 611). Thus, the one or more memory lines are discharged and recovered.

[0114] Figure 7 A flow chart illustrating an example method 700 for reducing latency of erase operations in a memory device according to some embodiments is shown. Figure 1A The memory device 130 shown in FIG. 1 includes a plurality of memory blocks (e.g. Figure 1A 170 shown in FIG. 17 ). Each of the plurality of memory blocks includes a plurality of word line segments. Each of the plurality of word line segments includes one or more word lines that form a subset of the word lines in the memory block. In some embodiments, the plurality of word line segments are divided into two word line segments, four word line segments, eight word line segments, or any number of word line segments.

[0115] The memory device further includes a memory controller (eg, a memory controller) configured to control voltages of the plurality of word lines and one or more memory lines associated with the plurality of word lines to perform an erase operation. Figure 1A and 1C ). In block 710 of method 700, the memory controller receives an erase command (eg, from a host system) for erasing data in a memory block.

[0116] In block 720 of method 700, in response to receiving an erase command, the memory controller causes one or more erase pulses to be applied to a plurality of word line segments. The memory controller causes word lines of different word line segments of a memory block to ramp up in different time periods, such that when data erasure begins at a first word line segment, data erasure does not begin at another word line segment. Thus, a large number of word lines (e.g., hundreds of word lines) are segmented into a plurality of word line segments, and when word lines of different word line segments are ramped up in different time periods, the load on each ramp is reduced. Thus, reducing the load shortens the ramping period, thereby reducing the latency of the erase operation.

[0117] In some embodiments, the one or more erase pulses include a plurality of erase pulses. The memory controller causes the plurality of erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different time periods. The memory controller causes each of the plurality of erase pulses to be applied to a corresponding word line segment of the plurality of word line segments in a sequential manner such that data erasure occurs at only one word line segment of the plurality of word line segments in any of the different time periods.

[0118] In some embodiments, the one or more erase pulses include a plurality of erase pulses. The memory controller causes a first erase pulse of the plurality of erase pulses to be applied to two or more word line segments of the plurality of word line segments, such that erasure of data in the two or more word line segments begins in the first erase pulse. After applying the first erase pulse, the memory controller further applies one or more additional erase pulses to one or more other word line segments of the plurality of word line segments, such that erasure of data in the one or more other word line segments begins in the corresponding one or more additional erase pulses.

[0119] In some embodiments, the one or more erase pulses include a single erase pulse. The memory controller causes the single erase pulse to be applied to the plurality of word line segments so that the word lines of different word line segments of the memory block are ramped up during different time periods. During the single erase pulse, the memory controller causes the memory lines of the plurality of word line segments to be ramped up toward an erase voltage. The erase voltage is a sufficiently high voltage for erasing data in the memory block. During any of the different time periods during which the word lines of the different word line segments are ramped up, the memory controller causes the word line of only one of the plurality of word line segments to remain at a first voltage. The first voltage is a low voltage that is lower than the erase voltage. In some embodiments, the first voltage may be a ground voltage (e.g., 0 volts), a small positive or negative voltage, or both. The memory controller causes the word lines of the other word line segments of the plurality of word line segments to be ramped up toward a second voltage that is higher than the first voltage.

[0120] Figure 8 and 9 A flow chart illustrating an example method 720 for ramping word lines of different word line segments in different time periods is shown, according to some embodiments. Figure 8 and 9 Box 720 is Figure 7 In block 720, the memory controller causes one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different time periods. Figure 8 and 9 As shown in FIG, the plurality of word line segments include a first word line segment and a second word line segment. In some embodiments, the number of the plurality of word line segments is greater than 2. Figure 8 and 9, a memory controller causes each of a plurality of erase pulses to be applied to a corresponding word line segment of a plurality of word line segments in a sequential manner such that, in any of the different time periods, data erasure occurs at only one word line segment of the plurality of word line segments. Figure 8 and 9 , the one or more erase pulses include a first erase pulse and a second erase pulse. During the first erase pulse, data erase occurs only at the first word line segment. During the second erase pulse, data erase occurs only at the second word line segment.

[0121] Figure 8 An example method 800 for applying a first erase pulse of one or more erase pulses to a plurality of word line segments is described in accordance with some embodiments. In block 810 of method 800, during the first erase pulse, a memory controller maintains a word line of a first word line segment of the plurality of word line segments at a first voltage. The first voltage is a low voltage. In some embodiments, the first voltage can be ground (e.g., 0 volts), a small positive voltage, or a small negative voltage.

[0122] In block 820 of method 800, a memory controller causes one or more memory lines associated with the plurality of word line segments to ramp toward an erase voltage. The erase voltage is a sufficiently high voltage for erasing data in a memory block. The first voltage is lower than the erase voltage.

[0123] In block 830 of method 800, the memory controller causes the word line of the second word line segment to ramp toward a second voltage. The second voltage is a voltage higher than the first voltage. In some embodiments, the second voltage may or may not be equal to the erase voltage. The ramping of the word line of the second word line segment is performed in conjunction with the ramping of one or more memory lines. In this approach, the load on the word line using only the first word line segment is reduced compared to the load on both word lines using both word line segments. As a result, the ramping period is reduced, thereby reducing the latency of the erase operation.

[0124] In block 840 of method 800, the memory controller maintains one or more memory lines associated with the plurality of word line segments at approximately an erase voltage for at least a threshold period such that data erasure begins at a first word line segment. During the threshold period, the memory controller also maintains word lines of a second word line segment at approximately a second voltage. Because there is no sufficiently high voltage bias in the word lines of the second word line segment, data erasure does not begin at the second word line segment.

[0125] In block 850 of method 800, the memory controller causes one or more memory lines associated with the plurality of word line segments to ramp down. Thus, the one or more memory lines are discharged and recovered.

[0126] In block 860 of method 800, the memory controller causes the word lines of the second word line segment to ramp down. Thus, the word lines of the second word line segment discharge and recover.

[0127] Figure 9 An example method 900 is described for applying a second erase pulse of one or more erase pulses to a plurality of word line segments in accordance with some embodiments. In block 910 of method 900, a memory controller maintains a word line of a second word line segment of the plurality of word line segments at approximately a first voltage during the second erase pulse.

[0128] In block 920 of method 900, a memory controller causes one or more memory lines associated with the plurality of word line segments to be ramped toward an erase voltage.

[0129] At block 930 of method 900, the memory controller causes the word line of the first word line segment to ramp toward the second voltage. The ramping of the word line of the first word line segment is combined with the ramping of one or more memory lines associated with the plurality of word line segments. Similarly, the load on the word line using only the second word line segment is less than the load on both word lines using both word line segments. Thus, the ramping period is reduced, thereby reducing the latency of the erase operation.

[0130] In block 940 of method 900, the memory controller maintains one or more memory lines associated with the plurality of word line segments at approximately an erase voltage for at least a threshold period, such that data erasure begins at the second word line segment. During the threshold period, the memory controller also maintains the word lines of the first word line segment at approximately a second voltage. Similarly, because there is no sufficiently high voltage bias in the word lines of the first word line segment, data erasure does not begin at the first word line segment.

[0131] In block 950 of method 900, the memory controller causes one or more memory lines associated with the plurality of word line segments to ramp down. Thus, the one or more memory lines are discharged and recovered.

[0132] In block 960 of method 900, the memory controller causes the word lines of the first word line segment to ramp down. Thus, the word lines of the first word line segment discharge and recover.

[0133] Figure 10 A flow chart illustrating another example method 720 for applying one or more erase pulses to multiple word line segments to ramp word lines of different word line segments in different periods is shown, in accordance with some embodiments. Figure 10 Box 720 is Figure 7 The memory controller causes one or more erase pulses to be applied to the plurality of word line segments to ramp up word lines of different word line segments of the memory block in different time periods. Figure 10 An example method 1000 is described for applying the same erase pulse of one or more erase pulses to multiple word line segments. Figure 10, the plurality of word line segments include a first word line segment and a second word line segment. In some embodiments, to erase data in a memory block, the plurality of word line segments are divided into 2 word line segments, 4 word line segments, 8 word line segments, or any number of word line segments.

[0134] In block 1010 of method 1000, during a same erase pulse in one or more erase pulses, a memory controller first maintains a word line of a first word line segment of a plurality of word line segments at a first voltage. The first voltage is a low voltage. In some embodiments, the first voltage can be ground (e.g., 0 volts) or a small positive or negative voltage.

[0135] In block 1020 of method 1000, a memory controller causes one or more memory lines associated with the plurality of word line segments to ramp toward an erase voltage. The erase voltage is a sufficiently high voltage for erasing data in a memory block. The first voltage is lower than the erase voltage.

[0136] In block 1030 of method 1000, the memory controller causes the word line of the second word line segment to ramp toward a second voltage. The second voltage is a voltage higher than the first voltage. In some embodiments, the second voltage may or may not be equal to the erase voltage. The ramping of the second word line segment is combined with the ramping of one or more memory lines associated with the plurality of word line segments. In this approach, the load on the word line using only the first word line segment is reduced compared to the load on both word lines using both word line segments. As a result, the ramping period is reduced, thereby reducing the latency of the erase operation.

[0137] In block 1040 of method 1000, while maintaining one or more memory lines associated with the plurality of word line segments at approximately an erase voltage such that data erase begins at a first word line segment, a memory controller causes word lines of a second word line segment to ramp down toward a third voltage. The third voltage is a voltage that is higher than the first voltage and lower than the second voltage.

[0138] In block 1050 of method 1000, the memory controller causes the word lines of the first word line segment to ramp up toward a third voltage. The memory controller also causes the word lines of the second word line segment to continue to ramp down toward approximately the first voltage. In this scheme, to quickly ramp down the word lines of the second word line segment, charge stored between the word lines of the second word line segment and one or more memory lines is moved between the word lines of the first word line segment and the one or more memory lines.

[0139] In block 1060 of method 1000 , the memory controller maintains the word line of the second word line segment at approximately the first voltage such that data erasure begins at the second word line segment.

[0140] At block 1070 of method 1000, the memory controller causes word lines of the first word line segment to ramp down toward approximately the first voltage. In some embodiments, the slope of ramping the word lines of the first word line segment from the third voltage to the first voltage is the same as the slope of ramping the word lines of the second word line segment from the second voltage to the third voltage.

[0141] In block 1080 of method 1000 , the memory controller maintains a word line of a first word line segment at approximately a first voltage such that data erasure begins at the first word line segment.

[0142] In block 1090 of method 1000, the memory controller causes one or more memory lines associated with the plurality of word line segments to ramp down. Thus, the one or more memory lines are discharged and recovered.

[0143] In some embodiments, during the same erase pulse, the memory controller holds one or more memory lines associated with the plurality of word line segments at about an erase voltage for a sufficient period to complete erasure of data at the first and second word line segments.

[0144] As described above, weak GIDL effects in 3D memory devices can lead to erroneous erase operations or affect the reliability of the memory device. Techniques for lifting isolated memory pillar portions to mitigate or eliminate weak GIDL effects in memory blocks are now described. Figure 11 1 is a diagram illustrating an example of a memory block 1100 including one or more word line groups according to some embodiments. Figure 11 As shown in FIG, a memory block 1100 includes a bit line 1101, a common source (SRC) line 1102, one or more memory pillars 1103, a drain select (SGD) line 1104, and a source select (SGS) line 1105. Figure 11 , memory block 1100 further includes a plurality of word lines 1106. The plurality of word lines 1106 can form one or more word line groups in memory block 1100. Figure 11 Only three word line groups 1110, 1120, and 1130 in the memory block 1100 are illustrated, but it should be understood that more or fewer word line groups may be included. The memory block 1100 further includes one or more interface word lines 1121 positioned between two adjacent word line groups. Figure 11 , interface word line 1121 is positioned between groups 1110 and 1120 or between groups 1120 and 1130. In some cases, word line groups 1106 may be collectively referred to as layers. Layers in a three-dimensional NAND memory array may be processed together (e.g., etched together to form part of a semiconductor pillar). Figure 11As shown in FIG, the three word line groups 1110, 1120, and 1130 may also be referred to as the top level 1110, the middle level 1120, and the bottom level 1130, respectively. Thus, the memory pillar includes three memory pillar portions 1112, 1122, and 1132 associated with the three word line groups 1110, 1120, and 1130, respectively. Figure 11 In the embodiment, a level corresponds to a word line group, but a word line group may include more or fewer word lines in a level. That is, within a word line group, there may be pillar portions that are not formed in the same etching process. In some embodiments, each of the word line groups further includes a plurality of word line segments. In some embodiments, a word line segment may include more or fewer word lines than in a word line group. Figure 11 , the word line group (middle level 1120) further includes two word line segments 1123 and 1124. When the memory block 1100 performs an erase operation, different voltages may be applied to different word line groups. The erase operation may be performed on different word line groups or segments in different time periods.

[0145] The memory block 1100 further includes a memory controller (eg, Figure 1A and 1C 1102). As described above, the erase operation is affected by GIDL. GIDL can introduce many holes with positive charge, and they can be introduced into the memory pillar 1103. As described above, the interface portion of the memory pillar 1103 (such as the portion associated with the interface word line 1121) can have a weaker GIDL effect (such as due to doping process variations during manufacturing). The weaker GIDL effect in the interface portion of the memory pillar 1103 can cause the voltage of some portions of the memory pillar (such as the memory pillar portion 1122 associated with the intermediate level 1120) to be lower than the voltage applied to the bit line 1101 or the SRC line 1102, which makes the erase operation less effective. For example, the memory controller sets the erase voltage V to 20V. era is applied to the bit line 1101 and the SRC line 1102. However, the memory pillar portion of the memory pillar 1103 having electron holes can only obtain a voltage of 18V, which is lower than the applied erase voltage V of 20V. era Therefore, there is no high enough voltage to perform the erase operation. One way to handle the weak GIDL effect in the interface portion is to apply an increased voltage to the bit line 1101 and the SRC line 1102. The increased voltage is higher than the erase voltage V eraThe maximum erase voltage is often increased to compensate for voltage losses in certain memory pillar sections. However, this leads to other problems, such as the inability of memory devices with small dimensions or feature sizes to withstand such high voltages. Therefore, a method is needed to reduce the maximum erase voltage to accommodate the current small dimensions of memory devices while still enabling proper erase operations.

[0146] Figures 12A to 12C A diagram illustrating an example method for reducing the maximum erase voltage in an erase operation in a memory device according to some embodiments is shown. Figure 1A The memory device 130 shown in FIG. 1 includes a plurality of memory blocks (e.g. Figure 1A The memory block 170 shown in FIG. Figure 11 The memory device further includes a memory controller (eg, a memory block 1100) configured to control voltages in each of the plurality of memory blocks to perform erase operations. Figure 1A and 1C local controller 135 shown in FIG. Figures 12A to 12C Display and Figure 11 The same memory block 1100 shown in FIG.

[0147] Figures 12A to 12C A method for boosting the voltage of the memory pillar portion 1122 associated with the middle level is described. Boosting the voltage of the memory pillar portion 1122 reduces the maximum erase voltage required to properly perform an erase operation. In one embodiment, a memory controller receives an erase operation command for erasing data in a memory block 1100. In response to receiving the erase operation command, the memory controller selects a target word line group for (1) preparing for isolation ( Figure 12A (2) electrically isolating the memory pillar portion associated with the target word line group ( Figure 12B (3) raising the voltage of the memory pillar portion associated with the target word line group ( Figure 12C After raising the voltage of the isolated memory pillar portion associated with the target word line group, the target word line group may perform an erase operation by using a voltage that is the same as or less than the erase voltage ( Figure 13 ), thereby reducing the maximum erase voltage in the erase operation.

[0148] The above steps are now described in more detail. Figure 12A, the memory controller selects word line group 1120 (e.g., corresponding to the middle level) as the target word line group. Word line groups 1110 and 1130 are other word line groups adjacent to target word line group 1120. Memory pillar portion 1122 is a memory pillar portion associated with target word line group 1120. In some embodiments, the memory controller may also select top level 1110 or bottom level 1130 as the target word line group.

[0149] Figure 12A A diagram illustrating an example of preparing for electrical isolation of memory pillar portions associated with target word line group 1120 according to some embodiments is shown. Figure 12A As shown in the figure, the memory controller erases the voltage V era is applied to the bit line 1101 and the SRC line 1102. For example, the erase voltage V era Therefore, the memory pillar 1103 receives an erase voltage V of 20V. era The memory controller will invert the voltage V inv The reverse voltage V is applied to the word lines of the other word line groups 1110 and 1130 adjacent to the target word line group 1120. In some embodiments, the reverse voltage V inv Sufficiently greater than the erase voltage V era This causes the channel inversion in the other word line groups 1110 and 1130. For example, the inversion voltages V inv It can be 25V. Figure 12A As shown in FIG, because other word line groups 1110 and 1130 (such as V inv = 25V) and the memory pillar 1103 (eg V era =20V) is greater than the threshold voltage, so electrons are induced in the memory pillar portions 1112 and 1132 (eg, channel regions) associated with the other word line groups 1110 and 1130, respectively, thereby inducing channel inversion.

[0150] like Figure 12A As shown in FIG. 1 , the interface word line 1121 is positioned between the target word line group 1120 and the other word line groups 1110 or 1130. The memory controller further sets the first interface voltage V if1 Applied to one or more interface word lines 1121. The first interface voltage V if1 Sufficiently smaller than the erase voltage V era To supply holes to the memory pillar portion 1122 of the target word line group 1120. For example, the first interface voltage V if1 The memory controller sets the first target word line voltage V t1is applied to the word lines of the target word line group (middle level) 1120. For example, the first target word line voltage V t1 Can be 0V. Figure 12A As shown in FIG, due to the target word line group 1120 (V t1 =0V) and memory pillar 1103 (V era =20V) creates a strong electric field. Thus, holes are induced and localized in the memory pillar portions 1122 (eg, the channel regions) associated with the target word line group 1120.

[0151] Steering Figure 12B , which shows a diagram illustrating an example of electrically isolating a memory pillar portion 1122 associated with a target word line group 1120 from memory pillar portions 1112 and 1132 according to some embodiments. Figure 12B As shown in the figure, the memory controller will deplete the voltage V d is applied to the word lines of the other word line groups 1110 and 1130. In some embodiments, the depletion voltage V d is sufficient to cause channel depletion in the other word line groups 1110 and 1130. For example, the depletion voltages V d When channel depletion occurs, the electrons in the memory pillar portions 1112 and 1132 are depleted, as shown in FIG. Figure 12B Channel depletion prevents electrons in the bit line 1101 or SRC line 1102 from moving into the memory pillar 1103.

[0152] The memory controller further sets the second interface voltage V if2 Applied to the interface word line 1121. In some embodiments, the second interface voltage V if2 is sufficient to cause channel depletion or inversion in the interface word line 1121. For example, the second interface voltage V if2 It can be 25V. Figure 12B , electrons are depleted in the memory pillar portions 1112 and 1132 associated with the other word line groups 1110 and 1130, respectively. Channel depletion or inversion in the interface word line 1121 also prevents holes from migrating out of the memory pillar portion 1122. Thus, the memory pillar portion 1122 associated with the target word line group 1120 is electrically isolated from the memory pillar portions 1112 and 1132 associated with the other word line groups 1110 and 1130, respectively.

[0153] In some embodiments, the isolated memory pillar portion 1122 associated with the target word line group 1120 forms at least a portion of an npnp structure having one or more of the following: other memory pillar portions 1112 and 1132, bit lines 1101, SRC lines 1102, and interface word lines 1121. For example, the memory controller selects word line group 1120 (e.g., the middle level) as the target word line group. In this scheme, bit lines 1101 and SRC lines 1102 are n-type. To prevent electrons in bit lines 1101 or SRC lines 1102 from migrating into memory pillars 1103, memory pillar portions 1112 and 1132 are depleted or p-type. To prevent holes in memory pillar portion 1122 from migrating out, the pillar portion of one or more interface word lines 1121 is depleted or n-type. The isolated memory pillar portion 1122 associated with the target word line group 1120 is p-type. Then, the voltage of the memory pillar portion 1122 can be raised to the same as or even greater than the erase voltage (eg, the voltage applied to the bit line 1101 or the SRC line 1102). Figure 11 and 12A In 12C, an npnp structure is formed by bit line 1101, memory pillar portion 1112, the pillar portion of interface word line 1121, and pillar portion 1122. Similarly, an npnp structure is also formed by SRC line 1102, memory pillar portion 1132, the pillar portion of interface word line 1121, and pillar portion 1122.

[0154] After isolation, the memory pillar portions 1122 associated with the target word line group 1120 can be elevated. Figure 12C A diagram illustrating an example method of boosting the voltage of an isolated memory pillar portion 1122 associated with a target word line group 1120 is shown in accordance with some embodiments. Figure 12C As shown in FIG. 1 , the target word line group 1120 further includes a plurality of word line segments 1123 and 1124. In some embodiments, word lines of different word line segments may have different voltages. Figure 12C As shown in FIG, the memory controller sets the second target word line voltage V t2 The memory controller maintains the word line of word line segment 1124 at the first target word line voltage V t1 In some embodiments, the second target word line voltage V t2 is greater than the first target word line voltage V t1 For example, the second target word line voltage V t2 can be 8V, and the first target word line voltage V t1 is 0V. By setting the second target word line voltage V t2The voltage of the memory pillar portion 1122 applied to some of the word lines of the target word line group 1120 may be raised to the same as or even greater than the erase voltage. For example, if the erase voltage V era If the voltage of the memory pillar portion 1122 is 20V, then the voltage of the memory pillar portion 1122 can be 20V, 22V or even higher. Using the boosted voltage, the memory controller can properly perform the erase operation of the target word line group 1120 without increasing the erase voltage. For example, the erase operation can use the same or less than the erase voltage V era The erase operation is performed at a voltage of , thereby reducing the maximum erase voltage in the erase operation.

[0155] Figure 13 A diagram illustrating an example of performing erase operations on multiple word line segments in different time periods by boosting the voltage at the memory pillar portions of a target word line group according to some embodiments is shown. Figure 1A The memory device 130 shown in FIG. 1 includes a plurality of memory blocks (e.g. Figure 1A The memory block 170 shown in FIG. Figure 11 Each of the plurality of memory blocks includes one or more word line groups (e.g., Figure 11 and 12A 12C). Each of the one or more word line groups includes a plurality of word lines ( Figure 11 and 12A to a plurality of word line segments (e.g., word line 1106 shown in FIG12C) Figure 11 and 12C The one or more word line groups include a target word line group (e.g., Figures 12A to 12C 1120) and one or more other word line groups adjacent to the target word line group (e.g. Figures 12A to 12C Groups 1110 and 1130 in FIG. Figure 13 As shown in FIG, the target word line group includes a first word line segment (eg, Figure 12C 1123 in the segment) and the second word line segment (e.g. Figure 12C 1124 in the figure).

[0156] The memory device further includes a memory controller (eg, a memory controller configured to control the voltages of the memory pillar portions and word line segments during erase pulses. Figure 1A and 1C In some embodiments, as shown in FIG. Figure 13As shown in FIG, at least one or more of the steps are performed during the erase pulse period. These steps include preparing for electrical isolation of the memory pillar portions associated with the target word line group, electrically isolating the memory pillar portions associated with the target word line group, raising the voltage of the isolated memory pillar portions, and performing an erase operation. Figure 13 As shown in FIG. 1 , the erase pulse includes an erase pulse ramp-up and word line group preparation period, an electrical isolation period, an erase pulse flat top and voltage increase period, and an erase pulse ramp-down period.

[0157] During the erase pulse ramp-up and word line group preparation period, the memory controller applies an erase voltage to one or more bit lines and one or more common source (SRC) lines of the target word line group and one or more other word line groups in order to prepare the target word line group and one or more other word line groups for electrical isolation. Figure 13 As shown in the figure, the erase voltage V era is a high enough voltage for erasing data in a memory block. The memory controller further sets the first target word line voltage V t1 applied to the word lines of the target word line group. Figure 13 As shown in FIG, the memory controller causes the word lines of the first word line segment and the second word line segment to be at a first target word line voltage V t1 (Section 1301). The first voltage V t1 is a low voltage. For example, the first target word line voltage V t1 =0V. Figure 13 As shown in FIG, during the erase pulse ramp-up and preparation word line group period, the voltage of the memory pillar associated with one or more word line groups is moved toward the erase voltage V era Ramp up (section 1302).

[0158] Still refer to Figure 13 During the electrical isolation period, the voltage of the memory pillar is at the erase voltage V era (Section 1303). During the erase pulse plateau and voltage boost period, the memory controller increases the second target word line voltage V t2 applied to a word line of at least one word line segment of a target word line group. Figure 13 In some embodiments shown in FIG, the second target word line voltage V t2 is greater than the first target word line voltage V t1 For example, the second target word line voltage V t2 is 8V, and the first target word line voltage V t1 is 0V. Figure 13, the memory controller performs erase operations on the first word line segment and the second word line segment in different time periods. When the second word line segment is used to increase the voltage of the isolated memory pillar portion associated with the target word line group, the memory controller performs an erase operation on the first word line segment (segment 1304). When the first word line segment is used to increase the voltage of the isolated memory pillar portion associated with the target word line group, the memory controller performs an erase operation on the second word line segment (segment 1305). Figure 13 and as above combined Figure 12C Description, during the erase pulse flat top and voltage rise period, the voltage of the memory pillar is raised to a value higher than the erase voltage V era Therefore, the memory controller can use the same or lower erase voltage V era The voltage (eg, the second target word line voltage V t2 ) performs an erase operation on the target word line group. Figure 13 As shown in FIG, the second target word line voltage V t2 Less than the erase voltage V era . Figure 13 It is further shown that the memory controller can perform erase operations on both the first and second word line segments in the target word line group during the flat top and voltage boost periods (section 1306). Figure 13 , during the erase pulse ramp-down period, the memory controller causes the memory pillar to ramp down (section 1307). Figure 13 While an erase operation using two word line segments is described, it should be understood that the same or similar erase operation can be performed using more word line segments. For example, if there are three word line segments, one segment can be used to boost the voltage in the memory pillar portion associated with the target word line group while the erase operation is performed on the other one or two segments.

[0159] Figure 14 A flowchart 1400 is shown representing an example method for reducing the maximum erase voltage in an erase operation in a memory device according to some embodiments. Figure 1A The memory device 130 shown in FIG. 1 includes a plurality of memory blocks (e.g. Figure 1A 170 shown in FIG. ). Each of the plurality of memory blocks includes one or more word line groups. Each of the one or more word line groups includes a plurality of word line segments including a plurality of word lines. In some embodiments, the one or more word line groups of a memory block include a top level, a middle level, and a bottom level.

[0160] The memory device further includes a memory controller (eg, Figure 1A and 1C1400 ). In some embodiments, the one or more word line groups include a target word line group and one or more other word line groups adjacent to the target word line group. In some embodiments, the target word line group includes multiple word line segments in a top level, a middle level, or a bottom level. In block 1410 of method 1400 , the memory controller prepares for electrical isolation of memory pillar portions associated with the target word line group.

[0161] In block 1420 of method 1400, the memory controller electrically isolates memory pillar portions associated with the target word line group from one or more memory pillar portions associated with one or more other word line groups.

[0162] In block 1430 of method 1400, the memory controller boosts the voltage of the isolated memory pillar portion associated with the target word line group.

[0163] In block 1440 of method 1400, the memory controller performs an erase operation for the target word line group using an erase voltage that is the same as or less than an erase voltage used for one or more memory pillar portions associated with one or more other word line groups in the memory block.

[0164] In some embodiments, at least one or more of the following steps are performed during the erase pulse period: preparing for electrical isolation of the memory pillar portions associated with the target word line group, electrically isolating the memory pillar portions associated with the target word line group, increasing the voltage of the isolated memory pillar portions, and performing an erase operation.

[0165] In some embodiments, method 1400 may include Figure 14 Additional steps not shown in the flowchart are described. For example, before preparing for electrical isolation of the memory pillar portions associated with the target word line group, the memory controller receives an erase operation command for erasing data in the memory block. In response to receiving the erase operation command, the memory controller selects the target word line group for boosting the voltage of the isolated memory pillar portions associated with the target word line group.

[0166] Figure 15 A flow chart illustrating an example method 1410 for preparing for electrical isolation of memory pillar portions is shown, according to some embodiments. Figure 15 Box 1410 is Figure 14 Same block 1410 in . The memory controller prepares for electrical isolation of the memory pillar portions associated with the target word line group.

[0167] In block 1510 of method 1410, the memory controller applies an erase voltage to one or more bit lines and one or more SRC lines of the target word line group and one or more other word line groups.The erase voltage is a high voltage used to erase data in a memory block.

[0168] In block 1520 of method 1410, the memory controller applies an inversion voltage to word lines of one or more other word line groups. In some embodiments, the inversion voltage is sufficiently greater than the erase voltage to cause channel inversion in the other word line groups.

[0169] In block 1530 of method 1410, the memory controller applies a first interface voltage to one or more interface word lines positioned between the target word line group and one or more other word line groups. In some embodiments, the first interface voltage is sufficiently less than the erase voltage to supply holes to the memory pillar portions of the target word line group.

[0170] In block 1540 of method 1410 , the memory controller applies a first target word line voltage to word lines of the target word line group.

[0171] Figure 16 A flow chart illustrating an example method 1420 for electrically isolating memory pillar portions is shown in accordance with some embodiments. Figure 16 Box 1420 is Figure 14 The memory controller electrically isolates the memory pillar portion associated with the target word line group from one or more memory pillar portions associated with one or more other word line groups. In some embodiments, the isolated memory pillar portion associated with the target word line group forms at least a portion of an npnp structure having one or more of the following: the other memory pillar portions, the bit lines, the SRC lines, and the interface word lines.

[0172] In block 1610 of method 1420, the memory controller applies a depletion voltage to word lines of one or more other word line groups. In some embodiments, the depletion voltage is sufficient to cause channel depletion in the other word line groups.

[0173] In block 1620 of method 1420, the memory controller applies a second interface voltage to one or more interface word lines positioned between the target word line group and one or more other word line groups. In some embodiments, the second interface voltage is sufficient to cause channel depletion or inversion in the interface word lines.

[0174] Figure 17 A flow chart illustrating an example method 1430 for boosting the voltage of an isolated memory pillar portion is shown, according to some embodiments. Figure 17 Box 1430 is Figure 14Same block 1430 in . The memory controller boosts the voltage of the isolated memory pillar portion associated with the target word line group.

[0175] In block 1710 of method 1430, the memory controller applies a second target word line voltage to a word line of at least one word line segment of a target word line group. In some embodiments, the second target word line voltage is greater than the first target word line voltage.

[0176] Figure 18 A flow chart illustrating an example method 1440 for performing erase operations of a target group of word lines using word line segmentation is shown, according to some embodiments. Figure 18 Box 1440 is Figure 14 The memory controller performs an erase operation for the target word line group using a voltage that is the same as or less than an erase voltage for other word line groups in the memory block. The target word line group includes a first word line segment and a second word line segment. Figure 18 An example method 1800 is illustrated for performing erase operations for a first word line segment and a second word line segment in different time periods.

[0177] In block 1810 of method 1800 , a memory controller performs an erase operation of a first word line segment while a second word line segment is used to boost a voltage of an isolated memory pillar portion associated with a target word line group.

[0178] In block 1820 of method 1800, the memory controller performs an erase operation of the second word line segment while the first word line segment is used to boost the voltage of the isolated memory pillar portion associated with the target word line group.

[0179] It should be noted that the described techniques include possible implementations, and that operations and blocks may be rearranged, reordered, or otherwise modified and that other implementations are possible. Furthermore, portions from two or more of the methods may be combined.

[0180] The information and signals described herein may be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, or signaling symbols that may be referenced throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or any combination thereof. Some figures may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0181] The terms "electronic communication," "conductive contact," "connection," and "coupling" may refer to a relationship between components that supports the flow of signals between the components. Components are said to be in electronic communication (or in conductive contact or connected or coupled) with each other if any conductive path exists between the components that can support the flow of signals between the components at any time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact or connected or coupled) with each other may be open or closed based on the operation of the device that includes the connected components. The conductive path between the connected components may be a direct conductive path between the components, or the conductive path between the connected components may be an indirect conductive path that may include intermediate components (such as switches, transistors, or other components). In some examples, the flow of signals between the connected components may be interrupted for a period of time, for example, using one or more intermediate components (such as switches or transistors).

[0182] The term "coupled" (e.g., "electrically coupled") may refer to a condition that transitions from an open-circuit relationship between components (where signals cannot currently pass between the components via a conductive path) to a closed-circuit relationship between the components (where signals can pass between the components via a conductive path). If a component, such as a controller, couples other components together, the component causes a change that allows signals to flow between the other components via a conductive path that previously prevented signal flow.

[0183] The term "isolation" refers to a relationship between components where signals are no longer able to flow between them. If an open circuit exists between the components, the components are isolated from each other. For example, if a switch located between two components is open, the components separated by the switch are isolated from each other. If a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using the conductive path that previously allowed signal flow.

[0184] The terms "if," "when," "based on," or "based at least in part on" may be used interchangeably. In some instances, if the terms "if," "when," "based on," or "based at least in part on" are used to describe a connection between conditional actions, conditional processes, or portions of processes, the terms may be interchangeable.

[0185] The term "in response to" may refer to a condition or action occurring at least in part, if not entirely, as a result of a preceding condition or action. For example, a first condition or action may be performed and a second condition or action may occur at least in part as a result of the preceding condition or action occurring (whether directly after the first condition or action or after one or more other intermediate conditions or actions occurring after the first condition or action).

[0186] The devices discussed herein, including memory arrays, can be formed on a semiconductor substrate, such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some examples, the substrate is a semiconductor wafer. In some other examples, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or a subregion of the substrate, can be controlled by doping with various chemical species, including but not limited to phosphorus, boron, or arsenic. Doping can be performed by ion implantation during the initial formation or growth of the substrate, or by any other doping method.

[0187] The switch components or transistors discussed herein may represent field-effect transistors (FETs) and include three-terminal devices comprising a source, a drain, and a gate. The terminals can be connected to other electronic components via conductive materials (e.g., metals). The source and drain can be conductive and may include heavily doped (e.g., degenerate) semiconductor regions. The source and drain can be separated by a lightly doped semiconductor region or channel. If the channel is n-type (i.e., the majority carriers are electrons), the FET may be referred to as an n-type FET. If the channel is p-type (i.e., the majority carriers are holes), the FET may be referred to as a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. If a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor gate, the transistor can be "switched on" or "activated." If a voltage less than the transistor's threshold voltage is applied to the transistor gate, the transistor can be "off" or "deactivated."

[0188] The description set forth herein, in conjunction with the accompanying drawings, describes example configurations and does not represent all examples that may be implemented or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, instance, or illustration" rather than "preferred" or "advantageous over other examples." The "Detailed Description" includes specific details to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0189] In the accompanying drawings, similar components or features may have the same reference label. Furthermore, various components of the same type may be distinguished by following the reference label with a hyphen and a second label that distinguishes the similar components. If only the first reference label is used in the specification, the description applies to any of the similar components having the same first reference label, regardless of the second reference label.

[0190] The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Figure 3 If the functionality is implemented in software executed by a processor 310 (e.g., a processor 310), the functionality may be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and implementations are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the described functionality may be implemented using software executed by a processor, hardware, firmware, hardwiring, or a combination of any of these. Features implementing the functionality may also be physically located at various locations, including being distributed such that portions of the functionality are implemented at different physical locations.

[0191] As used herein (including in the claims), "or" used in a list of items (e.g., a list of items preceded by a phrase such as "at least one of ..." or "one or more of ...") indicates an inclusive list, so that, for example, a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Moreover, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, an exemplary step described as "based on condition A" could be based on both condition A and condition B without departing from the scope of this disclosure. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "based at least in part on."

[0192] The description herein is provided to enable one skilled in the art to make or use the present disclosure. Various modifications of the present disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present disclosure. Therefore, the present disclosure is not limited to the examples and designs described herein, but should be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A memory device comprising: a plurality of memory blocks, wherein each of the plurality of memory blocks comprises a plurality of word line segments, wherein each of the plurality of word line segments comprises one or more word lines forming a subset of the word lines in the memory block; and A memory controller configured to perform: receiving an erase command for erasing data in the memory block; In response to receiving the erase command, one or more erase pulses are applied to the multiple word line segments to ramp up word lines of different word line segments of the memory block in different time periods so that when data erase starts at a first word line segment, data erase does not start at another word line segment. 2 . The memory device of claim 1 , wherein in order to erase data in the memory block, the plurality of word line segments are divided into 2 word line segments, 4 word line segments, or 8 word line segments.

3. The memory device of claim 1 , wherein causing the one or more erase pulses to be applied to the plurality of word line segments to ramp word lines in different word line segments of the memory block for different periods of time comprises: During a first erase pulse of the one or more erase pulses: maintaining a word line of the first word line segment of the plurality of word line segments at a first voltage lower than an erase voltage used to erase the data in the memory block; causing one or more memory pillars or bit lines associated with the plurality of word line segments to ramp toward the erase voltage; and The word lines of a second word line segment are caused to ramp toward a second voltage higher than the first voltage while the one or more memory pillars or bit lines associated with the plurality of word line segments are ramped.

4. The memory device of claim 3 , wherein the memory controller is further configured to perform, during the first erase pulse of the one or more erase pulses: maintaining the one or more memory pillars or bit lines associated with the plurality of word line segments at about the erase voltage for at least a threshold period such that data erasure begins at the first word line segment; causing the one or more memory pillars or bit lines associated with the plurality of word line segments to ramp down; and The word line of the second word line segment is caused to ramp down.

5. The memory device of claim 4 , wherein the memory controller is further configured to perform, during a second erase pulse of the one or more erase pulses: maintaining the word line of the second word line segment of the plurality of word line segments at approximately the first voltage; causing the one or more memory pillars or bit lines associated with the plurality of word line segments to ramp toward the erase voltage; and The word line of the first word line segment is caused to ramp toward the second voltage, which is higher than the first voltage, while the one or more memory pillars or bit lines associated with the plurality of word line segments are ramped.

6. The memory device of claim 5 , wherein the memory controller is further configured to perform: maintaining the one or more memory pillars or bit lines associated with the plurality of word line segments at about the erase voltage for at least the threshold period such that data erasure begins at the second word line segment; causing the one or more memory pillars or bit lines associated with a plurality of word line segments to be ramped down; and The word line of the first word line segment is caused to ramp down.

7. The memory device of claim 1 , wherein causing the one or more erase pulses to be applied to the plurality of word line segments to ramp word lines in different word line segments of the memory block for different periods of time comprises during a same erase pulse in the one or more erase pulses: maintaining a word line of the first word line segment of the plurality of word line segments at a first voltage lower than an erase voltage used to erase the data in the memory block; causing one or more memory pillars or bit lines associated with the plurality of word line segments to ramp toward the erase voltage; causing word lines of a second word line segment to ramp toward a second voltage higher than the first voltage while the one or more memory pillars or bit lines associated with the plurality of word line segments are ramped; causing the word lines of the second word line segment to ramp down toward a third voltage higher than the first voltage while maintaining the one or more memory pillars or bit lines associated with the plurality of word line segments at about the erase voltage such that data erase begins at the first word line segment; causing the word line of the first word line segment to ramp toward the third voltage; and The word line of the second word line segment is caused to continue ramping down toward approximately the first voltage.

8. The memory device of claim 7, wherein the memory controller is further configured to perform: maintaining the word line of the second word line segment at approximately the first voltage so that data erasure begins at the second word line segment; causing the word line of the first word line segment to ramp down toward approximately the first voltage; maintaining the word line of the first word line segment at about the first voltage so that data erasure begins at the first word line segment; and The one or more memory pillars or bit lines associated with the plurality of word line segments are caused to ramp down.

9. The memory device of claim 8, wherein the memory controller is further configured to, during the same erase pulse of the one or more erase pulses: The one or more memory pillars or bit lines associated with the plurality of word line segments are maintained at about the erase voltage for a sufficient period to complete erasure of data at the first and second word line segments.

10. The memory device of claim 1 , wherein the one or more erase pulses comprises a plurality of erase pulses, and wherein causing the plurality of erase pulses to be applied to the plurality of word line segments to cause word lines of different word line segments of the memory block to be ramped up in different time periods comprises: Each of the plurality of erase pulses is caused to be applied to a corresponding word line segment of the plurality of word line segments in a sequential manner such that data erasure occurs at only one word line segment of the plurality of word line segments in any of the different time periods.

11. The memory device of claim 1 , wherein the one or more erase pulses comprises a plurality of erase pulses, and wherein causing the plurality of erase pulses to be applied to the plurality of word line segments to ramp word lines of different word line segments of the memory block in different time periods comprises: causing a first erase pulse to be applied to two or more word line segments of the plurality of word line segments such that erasure of data of the two or more word line segments begins in the first erase pulse; and One or more additional erase pulses are caused to be applied to one or more other word line segments of the plurality of word line segments after applying the first erase pulse so that erasure of data of the one or more other word line segments begins in the respective one or more additional erase pulses.

12. The memory device of claim 1 , wherein the one or more erase pulses comprise a single erase pulse, and wherein causing the single erase pulse to be applied to the plurality of word line segments to ramp word lines of different word line segments of the memory block in different periods comprises, during the single erase pulse: causing memory pillars or bit lines of the plurality of word line segments to ramp toward an erase voltage for erasing the data in the memory block; During any of the different time periods during which word lines of different word line segments are ramped up, maintaining a word line of only one of the plurality of word line segments at a first voltage lower than the erase voltage, and Word lines of other word line segments of the plurality of word line segments are caused to ramp toward a second voltage that is higher than the first voltage.

13. The memory device of claim 12, wherein a number of the plurality of word line segments is greater than 2.

14. A system comprising: processor; a memory device coupled to the processor, the memory device comprising: a plurality of memory blocks, wherein each of the plurality of memory blocks comprises a plurality of word line segments, wherein each of the plurality of word line segments comprises one or more word lines forming a subset of the word lines in the memory block; and A memory controller configured to perform: receiving an erase command for erasing data in the memory block; In response to receiving the erase command, one or more erase pulses are applied to the multiple word line segments to ramp up word lines of different word line segments of the memory block in different time periods so that when data erase starts at a first word line segment, data erase does not start at another word line segment.

15. A memory device comprising: a plurality of memory blocks, wherein each of the plurality of memory blocks comprises one or more word line groups, wherein each of the one or more word line groups comprises a plurality of word line segments comprising a plurality of word lines; A memory controller configured to perform: preparing electrical isolation of memory pillar portions associated with the target word line group; electrically isolating the memory pillar portion associated with the target word line group from one or more memory pillar portions associated with one or more other word line groups; boosting a voltage of the isolated memory pillar portion associated with the target word line group; and An erase operation for the target word line group is performed using a voltage that is the same as or less than an erase voltage for other word line groups in the memory block.

16. The memory device of claim 15, wherein one or more word line groups of the memory block include a top level, a middle level, and a bottom level.

17. The memory device of claim 16, wherein the target word line group comprises a plurality of word line segments in the top level, the middle level, or the bottom level.

18. The memory device of claim 15, wherein preparing electrical isolation of memory pillar portions associated with the target word line group comprises: applying an erase voltage to the target word line group and one or more bit lines and one or more common source (SRC) lines of the one or more other word line groups; applying an inversion voltage to word lines of the one or more other word line groups; applying a first interface voltage to one or more interface word lines positioned between the target word line group and the one or more other word line groups; and A first target word line voltage is applied to the word lines of the target word line group.

19. The memory device of claim 18, wherein: The inversion voltage is sufficiently greater than the erase voltage to cause channel inversion in the one or more other word line groups; and The first interface voltage is sufficiently less than the erase voltage to supply holes to the memory pillar portions of the target word line group.

20. The memory device of claim 18, wherein electrically isolating the memory pillar portion associated with the target word line group from the one or more memory pillar portions associated with the one or more other word line groups comprises: applying a depletion voltage to the word lines of the one or more other word line groups; and A second interface voltage is applied to the one or more interface word lines positioned between the target word line group and the one or more other word line groups.

21. The memory device of claim 20, wherein: The depletion voltage is sufficient to cause channel depletion in the one or more other word line groups; and The second interface voltage is sufficient to cause channel depletion or inversion in the one or more interface word lines.

22. The memory device of claim 20, wherein boosting the voltage of the isolated memory pillar portion associated with the target word line group comprises: A second target word line voltage is applied to a word line of at least one word line segment of the target word line group.

23. The memory device of claim 22, wherein the second target word line voltage is greater than the first target word line voltage.

24. The memory device of claim 15, wherein the memory controller is further configured, prior to preparing for electrical isolation of memory pillar portions associated with the target word line group: receiving an erase operation command for erasing data in the memory block; and In response to receiving the erase operation command, the target word line group is selected for boosting the voltage of the isolated memory pillar portion associated with the target word line group.

25. The memory device of claim 15, wherein the target word line group includes a first word line segment and a second word line segment, and wherein performing the erase operation on the target word line group comprises: The erase operations of the first word line segment and the second word line segment are performed in different time periods.

26. The memory device of claim 25, wherein performing erase operations on the first word line segment and the second word line segment in different time periods comprises: performing the erase operation of the first word line segment while the second word line segment is used to boost the voltage of the isolated memory pillar portion associated with the target word line group; and The erase operation of the second word line segment is performed while the first word line segment is used to boost the voltage of the isolated memory pillar portion associated with the target word line group.

27. A memory device according to claim 15, wherein at least one or more of the following steps are performed within an erase pulse period: preparing electrical isolation of memory pillar portions associated with the target word line group, electrically isolating the memory pillar portions associated with the target word line group, increasing the voltage of the isolated memory pillar portions, and performing the erase operation.

28. The memory device of claim 15, wherein the isolated memory pillar portions associated with the target word line group form at least a portion of an npnp structure having one or more of: other memory pillar portions, bit lines, SRC lines, and interface word lines.

29. A system comprising: processor; a memory device coupled to the processor, the memory device comprising: a plurality of memory blocks, wherein each of the plurality of memory blocks comprises one or more word line groups, wherein each of the one or more word line groups comprises a plurality of word line segments comprising a plurality of word lines; A memory controller configured to perform: preparing electrical isolation of memory pillar portions associated with the target word line group; electrically isolating the memory pillar portion associated with the target word line group from one or more memory pillar portions associated with one or more other word line groups; boosting the voltage of the isolated memory pillar portion associated with the target word line group; and An erase operation for the target word line group is performed using a voltage that is the same as or less than an erase voltage for other word line groups in the memory block.

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