Power semiconductor device with non-rectangular semiconductor die for enhanced mechanical robustness and reduced stress concentration and electric field concentration

Abstract

A semiconductor device includes a semiconductor die including a substrate having a hexagonal crystal structure. The first and second sides of the semiconductor die extend along respective first and second crystal axes of the hexagonal crystal structure of the substrate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application serial number 18 / 107,537, filed on February 9, 2023, the entire contents of which are hereby incorporated by reference herein. Technical Field

[0003] The present invention relates to semiconductor devices, and more particularly to power semiconductor devices having a semiconductor die having a non-rectangular shape. Background Art

[0004] Semiconductor devices are often used in applications where the semiconductor device must pass large current levels in its "on" state and block high voltages in its reverse blocking or "off" state. For example, there is a need for a metal oxide semiconductor field effect transistor ("MOSFET") that can pass tens or even hundreds of amperes in its on state and block hundreds or even thousands of volts in its reverse blocking state. In order to support large current densities and block such high voltages, power MOSFETs and other power semiconductor devices, such as power junction barrier Schottky diodes ("JBS"), insulated gate bipolar junction transistors ("IGBT"), junction field effect transistors ("JFET"), gate controlled thyristors, etc., typically have a vertical structure with at least one contact on each of two opposing sides of a thick semiconductor layer structure. As used herein, the term "semiconductor layer structure" refers to a structure comprising one or more semiconductor layers (such as a semiconductor substrate and / or a semiconductor epitaxial layer).

[0005] The semiconductor layer structure of a power semiconductor device typically includes an "active area" having one or more functional semiconductor devices having a junction such as a pn junction. The active area acts as a main junction for blocking voltage during reverse bias operation and providing current flow during forward bias operation. The power semiconductor device may also have an edge termination structure, such as a series of guard rings or junction termination extensions ("JTE"), in the termination area of ​​the semiconductor layer structure. The edge termination structure can be designed to reduce the accumulation of electric field concentrations that would otherwise naturally occur along the edge of the semiconductor die during device operation. When the semiconductor die is viewed in a plan view, the termination area can surround the active area. In this article, a "plan view" of a semiconductor die refers to a view of the semiconductor die taken along an axis perpendicular to the center of the main surface of the semiconductor layer structure of the semiconductor die. The plan view is typically a view of the top surface of the semiconductor die.

[0006] A plurality of power semiconductor devices are typically formed on a wafer, which refers to a relatively large substrate that is typically formed of a semiconductor material such as 4H silicon carbide. A plurality of semiconductor epitaxial layers are grown on the wafer or otherwise formed on the wafer to form a semiconductor layer structure. Each power semiconductor device grown on the wafer will typically have an active area and its own edge termination. After the semiconductor layer structure is formed and additional process steps (e.g., deposition of a metal layer) are completed, the resulting structure can be diced to separate the individual edge-terminated power semiconductor dies. Each power semiconductor die can have a unit cell structure, wherein the active area of ​​each power semiconductor die includes a plurality of individual "unit cell" devices electrically connected in parallel. The power semiconductor die can then be packaged to provide a plurality of power semiconductor devices.

[0007] In very high power applications, power semiconductor devices are often formed in wide bandgap semiconductor material systems (in this article, the term "wide bandgap semiconductor" encompasses any semiconductor with a bandgap of at least 1.4 eV), such as, for example, silicon carbide, which has a number of advantageous properties, such as high electric field breakdown strength, high thermal conductivity, high electron mobility, high melting point, and high saturation electron drift velocity. Compared to devices formed in other semiconductor materials (such as, for example, silicon), electronic devices formed in silicon carbide can have the ability to operate at higher temperatures, at higher power densities, at higher speeds, at higher power levels, and / or at higher radiation densities.

[0008] Silicon carbide-based power devices offer several performance benefits, including high voltage blocking, low on-resistance, high current carrying capacity, fast switching speeds, low switching losses, and the ability to withstand high junction temperatures. These characteristics lead to a significant potential increase in power density, which is the power handled per area or volume. Summary of the Invention

[0009] According to some embodiments of the present invention, a semiconductor device is provided, which includes a semiconductor die, which includes a substrate having a hexagonal crystal structure, wherein a first side and a second side of the semiconductor die extend along a first crystal axis and a second crystal axis of the hexagonal crystal structure of the substrate, respectively.

[0010] In some embodiments, the first side and the second side intersect to define an obtuse interior angle.

[0011] In some embodiments, the semiconductor die comprises at least five sides when viewed in plan view. In some embodiments, the semiconductor die has a hexagonal shape when viewed in plan view. In some embodiments, the semiconductor die has an irregular polygonal shape when viewed in plan view. In some embodiments, the semiconductor die has a hexagonal shape with beveled corners when viewed in plan view.

[0012] In some embodiments, the semiconductor die includes a MOSFET including an active region including a plurality of unit cell transistors.

[0013] In some embodiments, a gate runner of a MOSFET includes a first segment and a second segment connected at an obtuse angle. In some embodiments, the first segment and the second segment of the gate runner each extend along a periphery of an active area. In some embodiments, a gate pad of the MOSFET is located at a center of the active area, and the gate runner includes a plurality of additional segments extending outward from the gate pad.

[0014] In some embodiments, the gate runner of the MOSFET includes a first segment and a second segment connected at an angle between 115° and 125°.

[0015] In some embodiments, the semiconductor die has a polygonal shape when viewed in plan view, wherein corners of the polygonal shape define interior angles exceeding 90°.

[0016] In some embodiments, the substrate includes a silicon carbide substrate or a gallium nitride substrate.

[0017] According to further embodiments of the present invention, there is provided a semiconductor device comprising a semiconductor die comprising at least five sides when viewed in plan view.

[0018] In some embodiments, the semiconductor die includes a semiconductor layer having a hexagonal crystal structure.

[0019] In some embodiments, the semiconductor die has a hexagonal shape when viewed in plan view.

[0020] In some embodiments, the semiconductor die has an irregular hexagonal shape when viewed in plan view.

[0021] In some embodiments, the semiconductor die has a hexagonal shape with chamfered corners when viewed in plan view.

[0022] In some embodiments, at least three of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0023] In some embodiments, all of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0024] In some embodiments, the semiconductor die includes a MOSFET including an active area containing a plurality of unit cell transistors, and a gate runner of the MOSFET includes a first segment and a second segment connected at an obtuse angle. In some embodiments, the obtuse angle is 120 degrees. In some embodiments, the first segment and the second segment of the gate runner each extend along a periphery of the active area. In some embodiments, the gate pad of the MOSFET is located at the center of the active area, and the gate runner includes a plurality of additional segments extending radially outward from the gate pad.

[0025] In some embodiments, the semiconductor die has a polygonal shape when viewed in plan view, wherein corners of the polygonal shape define interior angles exceeding 90°.

[0026] In some embodiments, the semiconductor layer includes a silicon carbide substrate or a gallium nitride substrate.

[0027] According to additional embodiments of the present invention, there is provided a semiconductor device including a semiconductor die having a polygonal shape with corners defining internal angles exceeding 90° when viewed in plan view.

[0028] In some embodiments, the semiconductor die includes a semiconductor layer having a hexagonal crystal structure.

[0029] In some embodiments, the polygonal shape is a hexagon. In some embodiments, the polygonal shape is an irregular hexagonal shape.

[0030] In some embodiments, at least two sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer. In some embodiments, all sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0031] In some embodiments, a semiconductor die includes a MOSFET having an active area including a plurality of unit cell transistors, and a gate runner of the MOSFET includes a first segment and a second segment connected at an obtuse angle. In some embodiments, the obtuse angle is 120°. In some embodiments, the first segment and the second segment of the gate runner each extend along a periphery of the active area. In some embodiments, the gate pad of the MOSFET is located at the center of the active area, and the gate runner includes a plurality of additional segments extending radially outward from the gate pad.

[0032] In some embodiments, the semiconductor layer includes a silicon carbide substrate or a gallium nitride substrate.

[0033] According to further embodiments of the present invention, there is provided a semiconductor device including a semiconductor die having a polygonal shape with chamfered corners when viewed in plan view.

[0034] In some embodiments, the semiconductor die includes a semiconductor layer having a hexagonal crystal structure.

[0035] In some embodiments, the polygonal shape has six major sides, and the chamfered corners include six chamfered corners.

[0036] In some embodiments, at least two of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the substrate. In some embodiments, all of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

[0037] In some embodiments, the semiconductor die includes a MOSFET including an active area containing a plurality of unit cell transistors, and a gate runner of the MOSFET includes a first segment and a second segment connected at an obtuse angle. In some embodiments, the obtuse angle is 120 degrees. In some embodiments, the first segment and the second segment of the gate runner each extend along a periphery of the active area. In some embodiments, the gate pad of the MOSFET is located at the center of the active area, and the gate runner includes a plurality of additional segments extending radially outward from the gate pad.

[0038] According to another embodiment of the present invention, a semiconductor device is provided that includes a semiconductor die, a semiconductor layer structure including an active region, and a gate runner located on the semiconductor layer structure and including a first segment and a second segment connected at an obtuse angle.

[0039] In some embodiments, the obtuse angle is an angle of 120°.

[0040] In some embodiments, the first segment and the second segment of the gate runner each extend along a periphery of the active region.

[0041] In some embodiments, the gate runner further includes a third segment and a fourth segment, and when viewed in plan view, the first to fourth segments define first to fourth sides of a hexagon, respectively.

[0042] In some embodiments, the gate pad of the MOSFET is located in the center of the active area, and the gate runner includes a plurality of additional segments extending radially outward from the gate pad. In some embodiments, the plurality of additional segments are radially spaced 60° apart from each other.

[0043] In some embodiments, the semiconductor die is a hexagonal shaped semiconductor die.

[0044] According to another embodiment of the present invention, a semiconductor device is provided, which includes a semiconductor tube core having a semiconductor layer structure, the semiconductor layer structure including an active area and a gate channel located on the semiconductor layer structure, the gate channel including a first segment, a second segment and a third segment extending respectively along the first crystal axis, the second crystal axis and the third crystal axis of the semiconductor substrate of the semiconductor layer structure.

[0045] In some embodiments, the first segment, the second segment, and the third segment of the gate runner each extend along a periphery of the active region.

[0046] In some embodiments, the gate runner further includes a fourth segment, and wherein the first to fourth segments define first to fourth sides of a hexagon, respectively, when viewed in plan view.

[0047] In some embodiments, the semiconductor die is a hexagonal shaped semiconductor die.

[0048] According to another embodiment of the present invention, a semiconductor device is provided, which includes a semiconductor die; a semiconductor layer structure including an active region; a gate pad located on the semiconductor layer structure; and a plurality of gate runner segments extending radially from the gate pad to corners of the semiconductor die.

[0049] In some embodiments, the gate pad is located in a central portion of the active area.

[0050] In some embodiments, the semiconductor device further includes an additional plurality of gate runner segments extending along a periphery of the active region.

[0051] In some embodiments, the semiconductor die is a hexagonal shaped semiconductor die.

[0052] In some embodiments, the gate pad is located at the center of the active area.

[0053] In some embodiments, the semiconductor layer structure includes a 4H silicon carbide substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1A and Figure 1B Schematic plan (top) and perspective views, respectively, of a conventional semiconductor die mounted on a submount.

[0055] Figure 2 yes Figure 1A-1B Schematic side view of the structure shown in.

[0056] Figure 3 is a graph that illustrates a series of regular polygons with varying numbers of sides.

[0057] Figure 4is a schematic plan view of a conventional silicon carbide semiconductor wafer illustrating the vertical and lateral "saw lines" at which the wafer is sawed to singulate the wafer into individual semiconductor die.

[0058] Figure 5 is a schematic plan view of a silicon carbide semiconductor wafer configured to be diced into hexagonally shaped semiconductor dies in accordance with an embodiment of the present invention.

[0059] Figure 6 is a collage of plan views of square, hexagonal, and circular semiconductor dies illustrating the relative stress levels throughout each die as it is bonded to an underlying base and heated.

[0060] Figure 7 is a collage of plan views of square semiconductor dies with sharp corners, rounded corners, and chamfered corners illustrating relative stress levels throughout each die as it is bonded to an underlying base and heated.

[0061] Figure 8 is a collage of plan views of hexagonal semiconductor dies having sharp and rounded corners illustrating relative levels of thermally generated stress throughout each die as it is bonded to an underlying base and heated.

[0062] Figure 9 is an example of a stress concentration factor design chart that illustrates how the degree to which the corners of a semiconductor die are rounded affects the maximum stress concentration level in the semiconductor die.

[0063] Figure 10 is a plan view illustrating how a semiconductor die having a regular hexagonal shape can be replaced with a semiconductor die having two longer sides to increase the semiconductor die area.

[0064] Figure 11A and Figure 11B Schematic plan view and schematic perspective view, respectively, of a silicon carbide based power diode semiconductor die according to an embodiment of the present invention.

[0065] Figure 12A and Figure 12B Schematic plan view and schematic perspective view of silicon carbide-based power MOSFET semiconductor dies according to further embodiments of the present invention, respectively.

[0066] Figure 12C yes Figures 12A-12B Schematic side view of a portion of a semiconductor die.

[0067] Figures 13A-13Fis a schematic plan view of six three-terminal hexagonally shaped power semiconductor dies (eg, power MOSFETs) with gate pads located at different positions according to an embodiment of the present invention.

[0068] Figures 14A-14D is a schematic plan view of four three-terminal hexagonal shaped power semiconductor dies having circular gate pads or gate pads including at least semicircular segments according to an embodiment of the present invention.

[0069] Figures 15A-15D is a schematic plan view of four three-terminal hexagonal shaped power semiconductor dies with rectangular gate pads or irregular pentagonal gate pads according to an embodiment of the present invention.

[0070] Figures 16A-16D is a schematic plan view of four three-terminal hexagonal shaped power semiconductor dies with rectangular or irregular pentagonal shaped gate pads (where at least some of the corners of the gate pads are rounded) according to an embodiment of the present invention.

[0071] Figures 17A-17C is a schematic plan view of three hexagonally shaped power MOSFETs illustrating example locations of gate runners in accordance with an embodiment of the present invention.

[0072] Figures 18A-18C is a schematic plan view of three hexagonally shaped power MOSFETs illustrating additional example locations of gate runners in accordance with an embodiment of the present invention.

[0073] Figures 19A-19C is a schematic plan view of three hexagonally shaped power MOSFETs illustrating yet additional example locations of gate runners in accordance with an embodiment of the present invention.

[0074] Figures 20A-20D An example semiconductor die with additional topside contact pads is illustrated. DETAILED DESCRIPTION

[0075] Power semiconductor devices typically have parasitic resistance, capacitance, and / or inductance, which may be located within the semiconductor die itself, in the electrical leads connecting the semiconductor die to external components, and / or in the device's protective packaging. These parasitic resistances, capacitances, and inductances result in the storage and / or dissipation of electrical and thermal energy. These drawbacks manifest as energy waste during device operation. For example, the processing of electrical energy generates waste heat due to conduction and switching losses. Removal of this waste heat results in a temperature increase due to thermal resistance and thermal capacitance.

[0076] As a power semiconductor device operates throughout its service life, it will typically heat up and cool down many, many times. Moreover, many power semiconductor devices, such as those used in electric vehicles, power generation substations, etc., are subject to extreme environments, including cold weather conditions, high ambient temperatures (e.g., under the hood of a vehicle), and high humidity. As the semiconductor device heats up and cools down, the materials of the semiconductor die and protective packaging will expand and contract. The rates at which the different materials in the die and package expand and contract are determined by their respective coefficients of thermal expansion (CTE), which can be very different for different materials. When two different materials are joined together, if one material wants to expand or contract more than the other, tensile and compressive stresses are generated within each material and at the interface between them.

[0077] The stress and strain generated by the above-mentioned thermal cycles and repeated many times may fatigue the semiconductor die and / or packaging structure. In particular, the stress may damage the device, resulting in a decline in functionality, until catastrophic failure occurs, for example, cracking occurs. Stress and strain may also greatly reduce the effectiveness of the interface or attachment of the semiconductor die to the package. For example, depending on the type and application of the package used, the semiconductor die in the packaged semiconductor device is typically mounted to a heat sink, copper pads, lead frame, isolated power substrate, etc. These heat sinks, pads, etc. can be mounted on one or both sides of the semiconductor die and attached to the die via die attach material. These die attach layers may be crucial because they can serve as all three of the electrical, thermal, and mechanical interfaces between the semiconductor die and the package. When the packaged semiconductor device undergoes thermal (heating and cooling) cycles, the stress and strain generated in the (one or more) die attach layers may cause cracks, ruptures, etc., which may ultimately lead to significant degradation of the die attach layer's ability to perform its electrical, thermal, and / or mechanical functions.

[0078] Thermal strains and stresses that can develop in packaged semiconductor devices can be a result of the structural geometry of the components that form the device, the method of attaching those components, the material composition of the components, and the difference between the temperature extremes encountered during device operation and the temperature at which the device is assumed to be in a stress-free state. Therefore, one way to reduce thermal strains and stresses is to select materials with similar coefficients of thermal expansion. Unfortunately, however, this is often not practical because materials serve many different functions, and it is often impossible or impractical to trade off one performance characteristic against another. For example, softer die attach materials are generally more resilient to fatigue but exhibit significantly poorer thermal conductivity. Therefore, the selection of die attach materials involves an inherent trade-off between reliability and performance, and the reliability gains from using softer die attach materials may not be worth the performance compromises.

[0079] As discussed above, semiconductor dies are typically formed using "wafer-level" operations in which semiconductor, insulating and metal layers / structures are grown, formed and / or deposited on a semiconductor wafer. The semiconductor wafer is then cut or "diced" into individual semiconductor dies by a sawing operation in which a diamond dicing blade is used to saw the wafer into columns and rows. Therefore, most power semiconductor dies have a rectangular (usually square) shape with right-angled corners, which is caused by sawing the wafer along a straight line. The corners are where thermal expansion and its associated stresses and strains are highest. Corners are also sudden changes that may become fault initiation sites. In addition, the "sharper" the corners, the greater the stresses and strains, and the more likely the corners are to become fault initiation sites. Unfortunately, the rectangular shape has relatively sharp corners and is therefore challenging from a stress perspective because sharp corners are potential failure points. In this article, the "shape" of a semiconductor die refers to the shape of the die when viewed in a plan view. Thus, a rectangular-shaped semiconductor die is a die that appears rectangular when viewed from above.

[0080] Figure 1A and Figure 1B Schematic plan (top) and perspective views, respectively, of a conventional semiconductor die 10 mounted on a base 12, such as a metal pad. The semiconductor die 10 may be soldered, sintered, epoxy-bonded, etc., to the underlying base 12 via a die attach material 14. If sufficient thermal cycling occurs, cracks in the semiconductor die 10 or die attach material 14 will typically initiate at the corners of either the semiconductor die 10 or die attach material 14, as stresses and strains are typically highest in these corner regions. The cracks may then propagate throughout the die attach material 14 or the bulk of the semiconductor die 10 in response to further thermal cycling.

[0081] Figure 2 Is installed on Figure 1A-1B A side view of the semiconductor die 10 on the base 12 is shown in FIG. Figure 2 As indicated in , in response to thermal cycling or other physical stresses, cracks may initiate at the transition between different materials, such as at the interface between the semiconductor die 10 and the die attach material 14, or at the interface between the die attach material 14 and the base 12. The die attach material 14 is a thin layer that requires a material with good electrical, thermal, and mechanical properties that allow the die attach material 14 to act as an interface between the semiconductor die 10 and the base 12. As mentioned above, and as Figure 2 As shown in , cracks typically form at the corners of semiconductor die 10 or die attach material 14 because thermally induced stresses are highest in these corner areas.

[0082] The "mechanical robustness" of a device refers to the device's ability to adapt to stresses and strains, such as those caused by thermal cycling or other physical forces. There are many potential ways to improve the mechanical robustness of packaged semiconductor devices, including reducing the mismatch in the coefficients of thermal expansion between the materials forming the device, reducing abrupt changes in the geometry of the elements forming the semiconductor device (such as sharp corners), introducing notches or slots to relieve stress concentrations, and / or using materials that are more resilient to stress-related failure modes.

[0083] According to an embodiment of the present invention, a semiconductor device is provided that can exhibit increased mechanical robustness and / or can have reduced electric field concentration at the edge of the device. In some embodiments, the semiconductor device may include a semiconductor die having a non-rectangular shape (such as a polygonal shape with more than four sides). Such a semiconductor die may have corners that form an internal angle of more than 90° and are therefore not as "sharp" as the corners of a rectangular semiconductor die having an internal angle of 90°. Such "softer" corners will exhibit less stress accumulation in response to thermal cycling or physical forces and are therefore less prone to cracks, delamination and / or device failure. In other embodiments, the semiconductor die may have rounded corners or chamfered corners that exhibit the same advantage of less stress accumulation. In each of the above embodiments, the selected shape of the semiconductor die preferably has a good packaging density to utilize the wafer as efficiently as possible. It should be noted that the electric field crowding effect may cause high electric field concentration to occur in the corner region of the semiconductor die, where the amount of electric field accumulation generally increases when the corner of the die is sharper. Thus, by providing a semiconductor die with "softer" corners, electric field crowding effects in the termination region of the semiconductor die can be reduced. This can improve the robustness of the semiconductor device or can allow the size of the termination region to be reduced, thereby increasing the amount of active die area.

[0084] In yet other embodiments of the present invention, semiconductor dies are provided that are diced along the crystal axis of the substrate of the semiconductor layer structure. Cutting along the crystal axis of the substrate may be "cleaner" than cutting that is off-axis. Less "clean" off-axis cutting may produce damage within the lattice structure of the semiconductor material, and these damages may become the initiation sites of cracking, delamination, performance degradation and / or device failure. Therefore, dicing the semiconductor wafer into semiconductor dies that are shaped to align with the crystal structure of the substrate of the wafer produces more robust semiconductor dies that are more adaptable to stress and are therefore less likely to be damaged in response to thermal cycling.

[0085] According to some further embodiments of the present invention, there is provided a semiconductor device having a semiconductor die with a gate runner and / or a gate pad that is designed / positioned to improve device performance. For example, in some embodiments, there is provided a semiconductor die having a gate runner having segments connected to each other at an angle exceeding 90° (such as an angle of 120°). For example, there is provided a semiconductor die having a gate runner that includes at least a first segment, a second segment, a third segment, and a fourth segment that form corresponding first, second, third, and fourth sides of a hexagon. In other words, the gate runner forms at least four sides of a hexagonal shape and may include additional segments so that the gate runner has a hexagonal shape or an almost complete hexagonal shape (e.g., a hexagonal shape with one or more small gaps). Such a gate runner may extend around at least four sides of a hexagonal-shaped semiconductor die. As another example, a semiconductor die is provided having a gate runner extending radially outward from a gate pad located in the center of a hexagonal-shaped semiconductor die. The gate runner may also include additional segments extending at least partially around the periphery of the die. This gate runner design can make the path of the gate signal to each unit cell transistor relatively short.

[0086] Semiconductor dies with new shapes / characteristics according to embodiments of the present invention can be formed using less conventional scribing techniques such as plasma scribing, laser ablation, stealth scribing, or thermal laser separation. Plasma scribing, also known as deep reactive ion etching, refers to a dry etching process in which a plasma gas (such as sulfur hexafluoride) is used to etch narrow cuts into a wafer. Stealth scribing refers to an internal absorption laser scribing process in which a laser beam passes along a cutting line and is focused beneath the surface of the wafer. The dies are then separated using a tape expander. These less conventional scribing techniques allow semiconductor wafers to be cut along more than two axes, and / or allow semiconductor wafers to be cut to provide semiconductor dies with rounded corners.

[0087] Therefore, according to various embodiments of the present invention, there is provided a semiconductor device comprising a semiconductor die comprising a substrate having a hexagonal crystal structure. In some embodiments, the first side and the second side of the semiconductor die extend along the corresponding first and second crystal axes of the hexagonal crystal structure of the substrate. In other embodiments, the semiconductor die may include at least five sides when viewed in a plan view. In still other embodiments, the semiconductor die may have a polygonal shape when viewed in a plan view, the polygonal shape having corners defining interior angles exceeding 90°. In yet other additional embodiments, the semiconductor die may have a polygonal shape with chamfered corners when viewed in a plan view.

[0088] In any or all of the above embodiments, the first side and the second side may intersect to define an internal angle that is an obtuse angle. The semiconductor die may have, for example, a regular or irregular hexagonal shape when viewed in a plan view, and may or may not have chamfered corners or rounded corners. The semiconductor die may include, for example, a MOSFET comprising an active area comprising a plurality of unit cell transistors. In some embodiments, the MOSFET may include a gate runner comprising a first segment and a second segment connected at an angle greater than 90°, such as, for example, an angle of 120°. The first segment and the second segment of the gate runner may, for example, each extend along the periphery of the active area. These MOSFETs may alternatively or additionally include a gate pad positioned in the center of the active area. In these embodiments, the gate runner may also include a plurality of additional segments extending outwardly from the gate pad. The semiconductor die may include, for example, a 4H silicon carbide substrate.

[0089] In yet other embodiments of the present invention, a semiconductor device is provided, comprising a semiconductor die comprising a semiconductor layer structure having an active area therein. A gate runner is provided on the semiconductor layer structure. The gate runner may, for example, comprise a first segment and a second segment connected at an angle of 120°, and / or may comprise a first segment, a second segment, and a third segment extending along a corresponding first crystal axis, a second crystal axis, and a third crystal axis of the semiconductor substrate. In some embodiments, the semiconductor die may further comprise a gate pad located on the semiconductor layer structure. In these embodiments, a plurality of gate runner segments may extend radially from the gate pad to a corner of the semiconductor die.

[0090] Embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. It will be appreciated that the features of the different embodiments disclosed herein can be combined in any manner to provide many additional embodiments. Therefore, it will be appreciated that various features of the present invention will be described below in conjunction with specific examples, but these features can be added to other embodiments and / or used in place of the example features of other embodiments to provide many additional embodiments. Therefore, the present invention should be understood to encompass these different combinations.

[0091] In a semiconductor die, thermally induced stress and / or physically induced stress accumulate more in the corners of the die than in the middle of the die. Generally speaking, stress-induced defects in a device or material are most likely to occur in the areas of highest stress, and therefore the corners of a semiconductor die are the areas of the semiconductor die that are most susceptible to stress-induced failures. The sharper the internal angle of the corner, the more stress accumulates. Therefore, one way to reduce the magnitude of the thermally induced stress and / or physically induced stress is to increase the magnitude of the internal angle of the corner. Figure 3As shown in , the more sides added to a device with a regular polygonal shape (a regular polygon is a shape formed by straight line segments, all of the same length, which are connected together to form a closed shape), the larger the internal angle of the corner. Figure 3 As shown in , an equilateral triangle has corners defining an interior angle of 60°, a rectangle has corners defining an interior angle of 60°, a pentagon has corners defining an interior angle of 108°, a hexagon has corners defining an interior angle of 120°, and so on. As the length of each side is vanishingly shortened, the polygon is converted into a circle, as shown in Figure 3 As further shown in . Therefore, Figure 3 The semiconductor die of the shapes shown in the figure will experience increasing amounts of stress at its corners as you move from the shape on the right side of the figure to the shape on the left side of the figure.

[0092] It is recognized that failure of many materials will typically initiate at a defect or flaw (e.g., a crystal defect, a damaged region of a crystal, or a void, crack, or chip in a crystal), or at areas of highest stress concentration. Various approaches described herein focus on dicing semiconductor wafers into geometries that reduce abrupt geometric transitions and / or dicing the wafer along the crystal axis of the wafer substrate (when viewing the die / wafer in a plan view) to reduce stress concentrations in the semiconductor wafer and / or strengthen areas of the semiconductor wafer where natural weaknesses may exist.

[0093] Silicon carbide-based semiconductor devices are typically formed by growing a semiconductor epitaxial layer on a silicon carbide substrate to form a semiconductor layer structure, then processing the wafer (e.g., depositing metal and / or insulating layers on the wafer, performing ion implantation steps, performing various etching steps, etc.), and then dicing the completed wafer into a plurality of discrete semiconductor dies, each of which is a separate semiconductor device. The silicon carbide wafer on which the semiconductor epitaxial layer is grown almost always has a circular shape when viewed in a plan view, and these wafers are diced by sawing the wafer along longitudinal and lateral cutting lines to singulate the wafer into a plurality of individual semiconductor dies.

[0094] Figure 4 FIG is a plan view of a conventional silicon carbide semiconductor wafer 20 illustrating longitudinal and lateral cut lines 22, 24. Figure 4 In the example of FIG, wafer 20, once diced, provides a total of fifty-seven semiconductor die 26. As discussed above, rectangular semiconductor die 26 formed using this conventional dicing technique may be susceptible to failure for two reasons.

[0095] First, the relatively sharp 90° angles formed at the corners of semiconductor die 26 cause stress to build up in these areas, creating potential failure points. Figure 6This can be seen in the figure which is a collage of plan views of a square semiconductor die 30, a hexagonal semiconductor die 32, and a circular semiconductor die 34, the collage of plan views illustrating the stress concentrations in the corners of each die. Magnified views of the corner areas of the respective semiconductor die are shown in the callouts. In these callouts, the darker the area, the greater the stress. As can be seen, very high stress concentrations are generated in the corners of the square semiconductor die 30. The corners of the hexagonal semiconductor die 32 also show increased stress, but the stress is significantly reduced compared to the square semiconductor die 30. The circular semiconductor die 34 represents an optimized shape for reducing the maximum stress concentration. In all cases, the stress concentration in the middle or "body" of the semiconductor die (i.e., away from the outer edges and any corners) is lower than at the corners, and the stress concentrations in the body of each semiconductor die 30, 32, 34 are similar. However, because failures tend to occur in areas of highest stress concentration, increasing the internal angle defined at the corners of the semiconductor die by increasing the number of sides significantly reduces the likelihood of crack formation that could lead to delamination and / or failure of the semiconductor die.

[0096] Secondly, when using a 4H silicon carbide semiconductor wafer 20 (4H silicon carbide is a type of silicon carbide almost always used to form power semiconductor devices), since 4H silicon carbide has a hexagonal crystal structure, Figure 4 At most, only one of the longitudinal cut lines 22 or transverse cut lines 24 shown in the figure can extend along the crystal axis of the 4H silicon carbide wafer 20. When the material is diced along a direction other than along the crystal axis (such a cut is referred to herein as an "off-axis" cut), damage occurs in the material crystal lattice that weakens the lattice structure. These damages may manifest as initiation sites for semiconductor die cracking, delamination, performance degradation, and / or failure.

[0097] According to an embodiment of the present invention, a semiconductor die having a polygonal shape with more than four sides when viewed in a plan view is provided. In this article, the "side" of the semiconductor die refers to the surface connecting the top surface and the bottom (main) surface of the die. For example, a semiconductor die having a hexagonal shape when viewed in a plan view (or a substantially hexagonal shape, such as a hexagonal die with a small bevel on each corner) is provided. By forming the semiconductor die into a polygonal shape with more than four sides, the amount of stress generated in the corners of the semiconductor die can be reduced. In addition, the use of a hexagonal-shaped semiconductor die may be particularly advantageous because, as discussed above, 4H silicon carbide has a hexagonal crystal structure, and therefore a semiconductor die based on a hexagonal shape of 4H silicon carbide can be formed by dicing a semiconductor wafer formed from the material along the crystal axis of the material. In addition, various other materials suitable for use in power semiconductor devices (such as gallium nitride-based materials) also have a hexagonal crystal structure, so hexagonal power semiconductor dies formed using gallium nitride or sapphire wafers can also be diced along the crystal axis of the substrate material. As discussed above, dicing the semiconductor die along the crystal axis of the substrate can reduce or eliminate damage to the crystal lattice that may be caused when the semiconductor die is cut off-axis.

[0098] Additionally, some semiconductor dies having polygonal shapes with more than four sides (such as, for example, hexagonal shaped semiconductor dies) can be "packaged" to use a greater amount of the area of ​​a circular semiconductor wafer, thereby allowing more semiconductor dies to be produced from a single wafer. For example, by comparing Figure 4 and Figure 5 Come to see this, Figure 4 Illustrated is a semiconductor wafer 20 to be cut to form square semiconductor die 26, Figure 5 A semiconductor wafer 40 is shown having hexagonal semiconductor die 46 formed therein according to an embodiment of the present invention. For example, the semiconductor wafer 40 is cut using a laser beam cutting technique to scribe the wafer into sixty-one hexagonal semiconductor die 46. The wafers 20, 40 and the semiconductor die 26, 46 have the same respective areas, and therefore Figure 4 and Figure 5 It is shown that using hexagonally shaped semiconductor die 46 may increase the amount of circular wafer that may be used to form individual semiconductor die compared to a wafer having square semiconductor die.

[0099] Another technique that can be used to reduce the inherently higher stress concentrations that may naturally occur in the corners of a semiconductor die is to include one or more bevel cuts in the corner region, replacing the sharp angle with two or more larger angles. Each bevel effectively adds an additional edge at each corner of the semiconductor die. Thus, for example, if a semiconductor wafer is diced into square semiconductor die, where each corner of the square has a bevel, the stress concentration generated in each corner can be reduced.

[0100] Figure 7 The figure illustrates how adding one or more chamfers at the corners of a semiconductor die can reduce the maximum stress concentration. In particular, Figure 7 is a collage containing plan views of: (1) a square semiconductor die 50 having sharp corners; (2) a square semiconductor die 52 having rounded corners; and (3) a square semiconductor die having chamfered corners 54 . Figure 7 The lightness / darkness of the shading in the callout indicates the relative stress level throughout each semiconductor die when the semiconductor die is bonded to an underlying base and heated, with darker shading indicating higher stress levels.

[0101] like Figure 7 As shown in , semiconductor die 50, which has sharp corners, exhibits the highest stress concentration. The view of semiconductor die 54 shows that by adding a 45° chamfer at each corner of the square, which effectively converts the square shape into an irregular octagonal shape, the stress concentration can be significantly reduced. By rounding the corners, the maximum stress concentration can be further reduced, as can be seen with reference to semiconductor die 52. The degree of rounding determines how much additional reduction in stress concentration is achieved. It will be appreciated that the techniques of using semiconductor die with more than four major sides and beveling or rounding the corners can be combined. For example, Figure 8 The diagram illustrates the relative stress levels generated in a hexagonal-shaped semiconductor die 60 having sharp corners compared to a hexagonal-shaped semiconductor die 62 having rounded corners when the semiconductor dies 60, 62 are bonded to an underlying base and heated. For silicon carbide-based semiconductor dies (or other semiconductor dies having a hexagonal crystal structure), hexagonal-shaped semiconductor dies with rounded corners can represent a very attractive option for reducing the risk of failure because the hexagonal shape allows the cutting to form the semiconductor die to be performed along the crystal axes of the material.

[0102] The "stress concentration factor" K is a scalar value that represents the percentage by which the maximum stress level increases due to the shape differences between different semiconductor dies. For example, when K is equal to 1.5, this means that the maximum stress level is 50% higher than the default case. Figure 9is an example of a stress concentration factor design graph that illustrates the extent to which increasing the internal angle defined by each corner of a semiconductor die and rounding the corners of the semiconductor die affects the maximum stress concentration level in the semiconductor die. Figure 9 , parameter "r" is the distance from the center of the semiconductor die to the radius at the vertex of the corner, parameter "d" is the distance from the center of the semiconductor die to the corner of the non-rounded version of the semiconductor die, parameter "a" is the internal angle defined by the corner of the first (default) semiconductor die (here 90°), and parameter "b" is the internal angle defined by the corner of the second semiconductor die (here shown as 120°). Figure 9 As shown in , as d / r increases (ie, as the fillet applied at the corners of the semiconductor die increases), the stress concentration factor "K" decreases. Figure 9 As shown in FIG, as the ratio "a / b" decreases (which occurs when the internal angle defined by the corners of the second semiconductor die increases relative to the 90° internal angle defined by the corners of the first (default) semiconductor die), the stress concentration factor "K" decreases. Therefore, Figure 9 Two ways of reducing stress in the corner regions of a semiconductor die are shown: (1) rounding the corners of the semiconductor die; and (2) increasing the number of corners included in the semiconductor die (because this increases the internal angle defined by each corner).

[0103] When the corners of the semiconductor die are not rounded, Figure 9 The parameter "d / r" in is equal to 1.0. Since the internal angles of a hexagon are 120° and the internal angles of a rectangle are 90°, the parameter "a / b" is equal to 0.75 when comparing the maximum stress of a hexagonal semiconductor die to the maximum stress of a rectangular semiconductor die. Figure 9 As shown in , by changing a rectangular semiconductor die to a hexagonal semiconductor die (in each case with non-rounded corners), the stress concentration factor K can be reduced from about 2.0 to about 1.5. Figure 9 It has also been shown that rounding the corners of the semiconductor die (which increases the parameter d / r) leads to a further reduction in the stress concentration factor K. Figure 9 As shown in , the maximum reduction in the stress concentration factor K occurs with the initial rounding of the corners, while further rounding of the corners results in a slower reduction in the stress concentration factor K.

[0104] Thus, according to some embodiments of the present invention, semiconductor dies are provided that have a maximum stress level that is at least 10%, at least 15%, at least 20%, or at least 25% lower than the maximum stress level in a default semiconductor die that is identical to a semiconductor die according to an embodiment of the present invention except that the default semiconductor die has a rectangular shape. "Identical" means that the two semiconductor dies are identical in all aspects (e.g., materials, layer structure, etc.) except for the shape, and have the same parameter "d" and, in some embodiments, the same parameter "r."

[0105] As discussed above, conventionally, semiconductor wafers are divided using a diamond scribing saw. Generally speaking, this technology can only be used to perform straight cuts that extend across the entire length or width of the semiconductor die and, therefore, cannot be used to singulate semiconductor wafers into semiconductor dies with polygonal shapes having more than four sides. Therefore, according to embodiments of the present invention, alternative scribing methods can be used to form semiconductor dies, such as, for example, scribing using a focused laser beam (including a laser that produces a beam outside the visible spectrum (such as an ultraviolet laser beam)). With this type of scribing, the laser beam typically passes along the cutting line multiple times and ablates the material. As the energy beam moves across the wafer, it is not limited to straight lines or orthogonal lines. As a result, more complex semiconductor die shapes can be achieved. The laser beam can completely remove material along the cutting line (i.e., cut all the way through the wafer), or in many cases, the laser beam can partially cut through the material along the cutting line, and then the tape on which the wafer is mounted can be stretched, which can cause the remaining material to separate along the cutting line. Using a laser beam to scribing wafers can be cost-effective because it is fast and may require less material to be removed between devices, potentially allowing more devices to be formed on each wafer. Other less traditional scribing techniques, such as plasma scribing, stealth scribing, or thermal laser separation, can also be used.

[0106] The semiconductor die according to an embodiment of the present invention may have a regular polygonal shape or an irregular polygonal shape. A regular polygon is a polygon in which all sides are of the same length. On the other hand, an irregular polygon is a polygon in which some sides are of different lengths. As discussed above, when the corners of a regular polygon are beveled at appropriate angles, the regular polygon can be converted into an irregular polygon. In addition, for some devices, it may be advantageous to form the semiconductor die to have an irregular polygonal shape, which can provide increased flexibility in the placement and positioning of elements of the semiconductor die (such as bonding pads, gate runners, gate fingers, etc.). Semiconductor dies of irregular polygonal shape can also be better formed to fit a given package and provide an alternative technology for increasing device area. Figure 10The diagram shows how to replace a semiconductor die 70 having a regular hexagonal shape with a semiconductor die 72 having two longer sides (converting the regular hexagon into an irregular hexagon) to increase the die area. Note that the above advantages of cutting along the crystal axis, reducing stress concentrations in the corners, and increasing packaging density can also be used Figure 10 The irregular hexagonal shaped semiconductor die 72 shown in FIG. 7 is fully realized.

[0107] Figures 11A-19C Illustrated is an example semiconductor die that can be formed using the techniques discussed above.

[0108] Figure 11A and Figure 11B 1 and 2 are respectively a plan view and a perspective view of a power diode semiconductor die 100 based on silicon carbide according to an embodiment of the present invention. Figures 11A-11B As shown in FIG, a power diode semiconductor die 100 includes a top surface and a bottom or "back" surface, with a metal anode contact pad 102 on the top surface and a metal cathode contact pad (not visible in the figure) on the bottom or "back" surface. The center of the power diode semiconductor die 100, located below the anode contact pad 102, can form an active region 106 of the power diode semiconductor die 100. This active region 106 allows current to pass when the power diode semiconductor die 100 is in its on-state, and this active region 106 is surrounded by an edge termination region 108. This edge termination region 108 is designed to reduce the electric field levels along the outer periphery of the power diode semiconductor die 100, as these electric fields can otherwise reach very high levels during device operation due to electric field crowding effects. This electric field crowding effect occurs around the periphery of the semiconductor die, particularly during reverse blocking operation. The sharper (smaller) the internal angle defined at each corner, the greater the electric field crowding effect, and thus the higher the electric field generated in the corners of the semiconductor die. The power diode semiconductor die 100 may have a 4H silicon carbide substrate and a plurality of silicon carbide semiconductor layers formed thereon.

[0109] The power diode semiconductor die 100 has a regular hexagonal shape. Figure 11AAs shown in , the interior angles defined by the corners of the semiconductor die exceed 90° (here each angle is 120°). As discussed above, these larger interior angles (compared to square-shaped semiconductor dies) reduce stress concentrations in the corners of the semiconductor die 100. In addition, because the power diode semiconductor die 100 has a silicon carbide substrate, all cut lines can be aligned with corresponding crystal axes of the silicon carbide substrate, so the six cuts used to singulate the semiconductor die 100 (one cut along each edge of the semiconductor die 100) can each be along a corresponding crystal axis of the silicon carbide substrate. This can achieve "cleaner" cuts that cause less damage to the silicon carbide substrate and the semiconductor epitaxial layer, thereby creating fewer weak points in the crystal lattice that may later serve as initiation points that may cause damage or failure of the semiconductor die 100. Furthermore, because the interior angles (120°) defined by the corners of the hexagonal semiconductor die 100 are larger than the interior angles (90°) present in a conventional square-shaped semiconductor die, the electric field level in the semiconductor die 100 can be lower than the corresponding electric field level in a conventional square-shaped semiconductor die (all else being equal). Thus, the size of the edge termination in the semiconductor die 100 can be reduced while maintaining the same electric field level as in a conventional square-shaped semiconductor die.

[0110] Although Figures 11A-11B A power diode semiconductor die 100 having a regular hexagonal shape is illustrated as an example, but it will be appreciated that, in accordance with the techniques disclosed herein, a power diode semiconductor die can include any polygonal shape having more than four sides (or corners having angles greater than 90°), and can include regular or irregular polygonal shapes. Furthermore, in some embodiments, the corners of the hexagonal shape can be chamfered.

[0111] Reference above Figures 11A-11B The power diode semiconductor die 100 discussed is a two-terminal device. Most power semiconductor devices are three-terminal devices, such as MOSFETs, JFETs, IGBTs, gate-controlled thyristors, etc. A three-terminal semiconductor die typically has a large pad on the top surface that acts as a first current-carrying terminal (e.g., source terminal, emitter terminal, etc.), and a smaller pad on the top surface that acts as a gate terminal (i.e., a terminal that controls the current flowing through the device). For some device technologies (e.g., many MOSFETs and IGBTs), a low-impedance trace called a gate runner is used to reduce the impedance of the conductive structure that distributes the signal input at the gate pad to the gate fingers that pass through the active area of ​​the semiconductor die. These semiconductor dies also typically have a large pad on the back surface that acts as a second current-carrying terminal (e.g., drain terminal, collector terminal, etc.). A termination region is typically formed around the periphery of the top surface of the semiconductor die that is designed to reduce the electric field level along the outer periphery of the semiconductor die.

[0112] Figure 12A and Figure 12B 1 and 2 are respectively a plan view and a perspective view of a power MOSFET semiconductor die 110 based on silicon carbide according to an embodiment of the present invention. Figures 12A-12B As shown in FIG, a power MOSFET semiconductor die 110 includes a top surface having a large metal source contact pad 112 and a smaller gate contact pad 114 electrically insulated from the source contact pad 112. A gate runner 116 is electrically connected to the gate contact pad 114 (and insulated from the source contact pad 116) and extends substantially around the perimeter of the semiconductor die 110. The MOSFET 110 includes an active region (which is located below the source contact pad 112). Figures 12A-12B 110). The active region 118 is a portion of the semiconductor layer structure that is located within the region substantially bounded by the gate runner 116. An edge termination region 118 extends around the periphery of the semiconductor die 110 outside the gate channel 116. The "back" side of the semiconductor die 110 has a metal drain contact pad 120 thereon that can cover substantially all of the back side of the semiconductor die 110.

[0113] Figure 12C yes Figures 12A-12B 1 is a schematic side view of a portion of a semiconductor die 110. As shown, the semiconductor die 110 includes a semiconductor layer structure 122, which includes a semiconductor substrate 124 and a plurality of semiconductor epitaxial layers 126 formed on the upper surface of the semiconductor substrate 124. The drain contact pad 120 is formed on the lower surface of the semiconductor substrate 124, and the source contact pad 112 and the gate contact pad 114 are formed on the upper surface of the semiconductor epitaxial layer 126. The insulating pattern 113 ( Figures 12A-12B The gate contact pad 114 is isolated from the source contact pad 112 (not visible in the plan view and perspective view).

[0114] The power MOSFET semiconductor die 110 has a hexagonal shape. Figures 12A-12BAs shown in FIG, gate contact pad 114 is positioned along one side of the hexagon. Gate runner 116 extends from the upper left corner of gate contact pad 114 and is located around most of the periphery of the upper surface of semiconductor die 110. Gate runner 116 includes a plurality of interconnected linear segments, including first and fifth segments 117-1 and 117-5 extending from respective upper corners of gate contact pad 114, second, third, sixth, and seventh segments 117-2, 117-3, 117-6, and 117-7, each extending along an entire side of the hexagon, and fourth and eighth segments 117-4 and 117-8, each extending partially along the side of the hexagon opposite gate contact pad 114. The first segment 117-1 is positioned between the gate contact pad 114 and the second segment 117-2 and is connected to both. The second segment 117-2 is positioned between the first segment 117-1 and the third segment 117-3 and is connected to both. The third segment 117-3 is positioned between the second segment 117-2 and the fourth segment 117-4 and is connected to both. Similarly, the fifth segment 117-5 is positioned between the gate contact pad 114 and the sixth segment 117-6 and is connected to both. The sixth segment 117-6 is positioned between the fifth segment 117-5 and the seventh segment 117-7 and is connected to both. The seventh segment 117-7 is positioned between the sixth segment 117-6 and the eighth segment 117-8 and is connected to both. Each segment 117 is connected to its adjacent segment at an internal angle of 120 degrees.

[0115] The power MOSFET semiconductor die 110 has a regular hexagonal shape and thus will have the same Figures 11A-11B The power diode semiconductor die 100 has the same advantages over conventional square semiconductor dies as discussed above. Figures 12A-12B A power MOSFET semiconductor die 110 having a regular hexagonal shape is illustrated as an example, but it will be appreciated that, in accordance with the techniques disclosed herein, the power MOSFET semiconductor die (and other three-terminal power semiconductor die) may include any polygonal shape having more than four sides (or having corners with angles greater than 90°), may include regular or irregular polygonal shapes, and / or may include chamfered or rounded corners.

[0116] Therefore, if Figures 12A-12BAs shown in , according to some embodiments of the present invention, a semiconductor device is provided, which includes a semiconductor die 110, and the semiconductor die 110 includes a semiconductor substrate 124 having a hexagonal crystal structure. In some embodiments, the semiconductor substrate 124 may include a 4H silicon carbide substrate. In some embodiments, the first side and the second side of the semiconductor die 110 extend along the corresponding first crystal axis and second crystal axis of the hexagonal crystal structure of the semiconductor substrate 124. In other embodiments, when viewed in a plan view, the semiconductor die 110 may include at least five sides. In still other embodiments, when viewed in a plan view, the semiconductor die 110 may have a polygonal shape having corners defining an internal angle exceeding 90°. For example, the semiconductor die 110 may include a MOSFET including an active region comprising a plurality of unit cell transistors.

[0117] According to other embodiments of the present invention, there are provided power MOSFET semiconductor dies (and other three-terminal semiconductor dies) with various designs of gate pads and / or gate runners. For example, Figures 13A-13F A three-terminal hexagonal shaped power semiconductor die (e.g., a power MOSFET) is illustrated with gate pads located at various positions. Figure 13A In the semiconductor die 130 illustrated in FIG, the gate pad 132 is positioned adjacent to a first side of the semiconductor die 130 and is generally centered along the center of the side. Note that the semiconductor die 130 may be Figures 12A-12B The semiconductor die 120 in FIG. 1 is the same as that in FIG. 1 . As a comparison, Figure 13B A semiconductor die 140 is illustrated having a gate pad 142 positioned at the junction of two edges of the semiconductor die 140 . Figure 13C A semiconductor die 150 is illustrated having a gate pad 152 positioned in the center of the semiconductor die 150. Finally, Figure 13D A semiconductor die 160 is illustrated having gate pads 162-1 through 162-6 positioned at each of the joints of two sides of the semiconductor die 160. Although not separately shown, it will be appreciated that in other embodiments, a semiconductor die may be provided having a gate pad positioned at the center of each side of the semiconductor die (i.e., Figure 13A The semiconductor die has an additional five gate pads added along the remaining five sides of the die. It will also be appreciated that a device having more than one gate pad may have fewer than six gate pads. For example, Figure 13E A semiconductor die 170 is illustrated having two gate pads 172 - 1 and 172 - 2 positioned adjacent opposing sides of the semiconductor die 170 ; and Figure 13F Semiconductor die 180 is illustrated having three gate pads 182-1 through 182-3 positioned at three of the six bonds on two sides of semiconductor die 180. Having multiple gate pads may involve tradeoffs between gate resistance and packaging flexibility on the one hand and active area size on the other.

[0118] It will also be appreciated that the shape of the gate pad may be different from Figures 13A-13F For example, Figures 14A-14D The diagram shows Figures 13A-13D The semiconductor die corresponds to the semiconductor die, except Figures 14A-14D The semiconductor die in the embodiment of the present invention has a circular gate pad or a gate pad that includes at least a semicircular segment. The circular or rounded gate pad can be used to increase and / or maximize the active area size of the device. Figures 15A-15D The diagram shows Figures 13A-13D The semiconductor die corresponds to the semiconductor die, except Figures 15A-15D The semiconductor die in the embodiment has a rectangular gate pad or an irregular pentagonal gate pad. The gate pad size is generally based on the method by which the external circuit is electrically connected to the gate pad (e.g., wire bonding, soldering, sintering, etc.), the size of the structure attached to the gate pad (e.g., wire bonding), and the process window of the attachment process. Changing from a square gate pad to a rectangular gate pad can be a convenient way to increase the gate pad size (e.g., for devices with large diameter bond wires). Figures 16A-16D The diagram shows Figures 15A-15D The semiconductor die in the corresponding semiconductor die, except Figures 16A-16D The semiconductor die in the embodiment has a gate pad in the shape of a rectangle or an irregular pentagon in which at least some corners are rounded.

[0119] Figures 17A-17C An example location of a gate runner in a three-terminal power semiconductor die according to an embodiment of the present invention is illustrated. The gate runner may include a connection between a gate finger and (one or more) gate pads of a device. In many cases, the gate runner is formed of metal to have low impedance. The gate runner may include segments that conform to the shape of the semiconductor die (e.g., a hexagonal shape) and may also include additional segments.

[0120] For example, Figure 17AA semiconductor die 200 is shown that includes a gate pad 202 and a gate runner 204 having a plurality of segments 206 extending substantially around the periphery of the semiconductor die 200, and an additional segment 208 extending through the center of the semiconductor die 200. A plurality of gate fingers 210 (e.g., silicon gate fingers) are electrically connected to the gate runner 204 (and, in some embodiments, may also be physically connected). A gate signal input at the gate pad 202 is passed to the gate fingers 210 via the gate runner 204. As shown, in this configuration, the gate fingers 210 are divided into two groups, and each gate finger 210 is fed from two sides, thereby reducing the resistance of the path that the gate signal follows as it travels from the gate pad 202 to and along the individual gate fingers 210. Figure 17B The semiconductor die 220 is shown. Figure 17A The semiconductor die 220 includes a gate pad 222 and a gate runner 224 having a plurality of segments 226 extending substantially all the way around the periphery of the semiconductor die 200 and two additional segments 228 extending through a central region of the semiconductor die 220. Figure 17B In the device of , three sets of gate fingers 230 are provided, wherein each gate finger 230 is fed from two sides. Semiconductor die 220 can exhibit lower gate resistance values ​​than semiconductor die 200, but at the expense of a reduced size of the active area of ​​the device. Figure 17C Semiconductor die 240 is illustrated and includes a gate pad 242 and gate runners 244 that extend substantially all the way around the periphery of semiconductor die 240 and also include additional segments 228 that extend radially from the periphery of semiconductor die 240 into the active area. The radial gate runner segments divide gate fingers 250 into six groups that extend at different angles relative to each other.

[0121] Figures 18A-18C The diagram shows a Figure 17C A semiconductor die with a gate runner design similar to that shown in FIG, except Figures 18A-18C The gate pads of the semiconductor die are positioned at the edges of two sides, and Figures 17A-17C The gate pad of the semiconductor die is centered along an edge of the corresponding semiconductor die. Figures 19A-19C Similarly, the diagram shows Figures 17A-17C A semiconductor die with a gate runner design similar to that shown in FIG, except Figures 19A-19C The gate pad of the semiconductor die is positioned in the center of the device. To simplify the figures, Figures 18A-19C The gate fingers are not shown.

[0122] In some cases, a three-terminal semiconductor die may require additional contact (bonding) pads required for secondary functions. For example, in a device with a soldered or sintered top surface connection, a dedicated source Kelvin wire bond pad is also provided. As another example, in some cases, additional auxiliary bond pads may be required for on-chip sensors, such as temperature or current sensors. Figures 20A-20D An example semiconductor die is shown with additional top surface contact pads, namely, a source contact pad 300, a gate contact pad 302, and one or more additional contact pads 304. Many more arrangements are envisioned in which some or all of the gate contact pads and / or the additional contact pads have a circular (or partially circular) shape or a rectangular shape.

[0123] Semiconductor dies according to embodiments of the present invention may be used in a wide variety of applications, including motor drives, battery chargers, wind / solar inverters, power supplies, and the like.

[0124] Although the present invention has been described above primarily with respect to power MOSFET embodiments, it will be appreciated that the techniques described herein are equally well applicable to other power semiconductor devices.Accordingly, embodiments of the present invention are not limited to MOSFETs.

[0125] While embodiments of the present invention have been discussed above primarily with respect to semiconductor dies having at least five sides and / or having corners defining interior angles greater than 90° when viewed in plan view, it will be appreciated that embodiments of the present invention are not limited thereto. In other embodiments, the semiconductor die may have fewer than four sides (e.g., three sides to form a triangle) and / or may have corners defining interior angles less than 90° (such as 60° angles) when viewed in plan view. Thus, it will be appreciated that in other embodiments, all of the hexagonal-shaped semiconductor dies described above may be implemented as triangular-shaped dies.

[0126] The present invention has been discussed above primarily with respect to power semiconductor devices based on silicon carbide. However, it will be appreciated that silicon carbide is used as an example herein, and the devices discussed herein may be formed in any suitable wide-bandgap semiconductor material system. As an example, in any of the above embodiments, a semiconductor material having gallium nitride (e.g., gallium nitride, aluminum gallium nitride, etc.) may be used in place of silicon carbide.

[0127] Embodiments of the present invention have been described above with reference to the accompanying drawings, which illustrate embodiments of the present invention. However, it will be appreciated that the present invention may be implemented in a variety of different forms and should not be construed as being limited to the embodiments described above. Rather, these embodiments are provided so that this disclosure will be more thorough and complete and will fully convey the scope of the invention to those skilled in the art. Throughout the present disclosure, like reference numerals represent like elements.

[0128] In this context, the term "plurality" means two or more. In this context, "substantially" means within + / - 10%.

[0129] It will be understood that although the terms "first," "second," etc. are used throughout this specification to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0130] The terms used herein are used only to describe specific embodiments and are not intended to limit the present invention. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms "comprises," "comprising," "includes," and / or "including" when used herein specify the presence of the features, integers, steps, operations, elements, and / or parts, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, parts, and / or groups thereof.

[0131] It will be understood that when an element (such as a layer, region, or substrate) is referred to as being “on” or extending “onto” another element, it may be directly on or extend directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly on” or extending “directly onto” another element, there are no intervening elements. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it may be directly connected or coupled to the other element, or there may be intervening elements. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements.

[0132] Relative terms such as "below," "above," "upper," "lower," "top," or "bottom" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

[0133] Embodiments of the present invention are described herein with reference to cross-sectional illustrations, which are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Furthermore, variations from the illustrated shapes are to be expected, for example, as a result of manufacturing techniques and / or tolerances. Embodiments of the present invention are also described with reference to flow charts. It will be appreciated that the steps shown in the flow charts need not be performed in the order shown.

[0134] In the drawings and specification, typical embodiments of the invention are disclosed, and although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the appended claims.

Claims

1. A semiconductor device comprising: a semiconductor die comprising a substrate having a hexagonal crystal structure, The first side and the second side of the semiconductor die extend along the corresponding first crystal axis and the second crystal axis of the hexagonal crystal structure of the substrate. 2 . The semiconductor device of claim 1 , wherein the first side and the second side intersect to define an obtuse interior angle. 3 . The semiconductor device of claim 1 , wherein the semiconductor die comprises at least five sides when viewed in plan view. 4 . The semiconductor device of claim 3 , wherein the semiconductor die has a hexagonal shape when viewed in plan view. 5 . The semiconductor device of claim 3 , wherein the semiconductor die has an irregular polygonal shape when viewed in plan view. 6 . The semiconductor device of claim 3 , wherein the semiconductor die has a hexagonal shape with chamfered corners when viewed in plan view. 7 . The semiconductor device of claim 1 , wherein the semiconductor die comprises a MOSFET including an active region including a plurality of unit cell transistors. 8 . The semiconductor device according to claim 7 , wherein the gate runner of the MOSFET includes a first segment and a second segment connected at an obtuse angle. 9 . The semiconductor device of claim 8 , wherein the first segment and the second segment of the gate runner each extend along a periphery of the active region.

10. The semiconductor device of claim 9, wherein a gate pad of the MOSFET is located in the center of an active area, and wherein the gate runner includes a plurality of additional segments extending outwardly from the gate pad. 11 . The semiconductor device of claim 7 , wherein the gate runner of the MOSFET comprises a first segment and a second segment connected at an angle between 115° and 125°. 12 . The semiconductor device of claim 1 , wherein the semiconductor die has a polygonal shape when viewed in plan view, wherein corners of the polygonal shape define internal angles exceeding 90°.

13. The semiconductor device according to any one of claims 1 to 6, wherein the substrate comprises a silicon carbide substrate.

14. The semiconductor device according to any one of claims 1 to 6, wherein the substrate comprises a gallium nitride substrate.

15. A semiconductor device comprising: semiconductor die, Wherein the semiconductor die comprises at least five sides when viewed in plan view. 16 . The semiconductor device of claim 15 , wherein the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure. 17 . The semiconductor device of claim 16 , wherein the semiconductor die has a hexagonal shape when viewed in plan view.

18. The semiconductor device of claim 17, wherein the semiconductor die has an irregular hexagonal shape when viewed in plan view.

19. The semiconductor device of claim 17, wherein the semiconductor die has a hexagonal shape with chamfered corners when viewed in plan view.

20. The semiconductor device of any one of claims 16 to 19, wherein at least three of the sides of the semiconductor die extend along crystal axes of a hexagonal crystal structure of the semiconductor layer.

21. The semiconductor device of any one of claims 16 to 19, wherein all of the sides of the semiconductor die extend along crystal axes of a hexagonal crystal structure of the semiconductor layer.

22. The semiconductor device of any one of claims 16 to 19, wherein the semiconductor die comprises a MOSFET including an active region comprising a plurality of unit cell transistors, and The gate channel of the MOSFET includes a first segment and a second segment connected at an obtuse angle.

23. The semiconductor device according to claim 22, wherein the obtuse angle is an angle of 120°.

24. The semiconductor device of claim 22, wherein the first segment and the second segment of the gate runner each extend along a periphery of the active region.

25. The semiconductor device of claim 21, wherein a gate pad of the MOSFET is located in the center of an active area, and wherein the gate runner includes a plurality of additional segments extending radially outward from the gate pad.

26. The semiconductor device of any of claims 16-19, wherein the semiconductor die has a polygonal shape when viewed in plan view, wherein corners of the polygonal shape define internal angles exceeding 90°.

27. The semiconductor device of any one of claims 16 to 26, wherein the semiconductor layer comprises a silicon carbide substrate.

28. The semiconductor device of any one of claims 16 to 26, wherein the semiconductor layer comprises a gallium nitride substrate.

29. A semiconductor device comprising: semiconductor die, Therein, when viewed in plan view, the semiconductor die has a polygonal shape with corners defining interior angles exceeding 90°.

30. The semiconductor device of claim 29, wherein the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

31. The semiconductor device of claim 30, wherein the polygonal shape is a hexagon.

32. The semiconductor device of claim 31, wherein the polygonal shape is an irregular hexagonal shape.

33. The semiconductor device of claim 30, wherein at least two sides of the semiconductor die extend along crystal axes of a hexagonal crystal structure of the semiconductor layer.

34. The semiconductor device of claim 30, wherein all sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

35. The semiconductor device of any one of claims 30-34, wherein the semiconductor die comprises a MOSFET, an active region comprising a plurality of unit cell transistors, and The gate channel of the MOSFET includes a first segment and a second segment connected at an obtuse angle.

36. The semiconductor device of claim 35, wherein the obtuse angle is an angle of 120°.

37. The semiconductor device of claim 35, wherein the first segment and the second segment of the gate runner each extend along a periphery of the active region.

38. The semiconductor device of claim 37, wherein the gate pad of the MOSFET is located in the center of the active area, and wherein the gate runner includes a plurality of additional segments extending radially outward from the gate pad.

39. The semiconductor device according to any one of claims 30 to 38, wherein the semiconductor layer comprises a silicon carbide substrate or a gallium nitride substrate.

40. A semiconductor device comprising: semiconductor die, Wherein the semiconductor die has a polygonal shape with chamfered corners when viewed in plan view.

41. The semiconductor device of claim 40, wherein the semiconductor die comprises a semiconductor layer having a hexagonal crystal structure.

42. The semiconductor device of claim 41, wherein the polygonal shape has six main sides, and the chamfered corners include six chamfered corners.

43. The semiconductor device of claim 42, wherein at least two of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the substrate.

44. The semiconductor device of claim 42, wherein all of the sides of the semiconductor die extend along crystal axes of the hexagonal crystal structure of the semiconductor layer.

45. The semiconductor device of any one of claims 40-44, wherein the semiconductor die comprises a MOSFET including an active region comprising a plurality of unit cell transistors, and The gate channel of the MOSFET includes a first segment and a second segment connected at an obtuse angle.

46. ​​The semiconductor device of claim 45, wherein the obtuse angle is an angle of 120°.

47. A semiconductor device as claimed in claim 45 or 46, wherein the first segment and the second segment of the gate runner each extend along a periphery of the active region.

48. The semiconductor device of any one of claims 45 to 47, wherein a gate pad of the MOSFET is located in the center of an active area, and wherein the gate runner comprises a plurality of additional segments extending radially outward from the gate pad.

49. A semiconductor device comprising: A semiconductor die, the semiconductor die comprising: a semiconductor layer structure comprising an active region; and A gate runner is located on the semiconductor layer structure, and includes a first segment and a second segment connected at an obtuse angle.

50. The semiconductor device of claim 49, wherein the obtuse angle is an angle of 120°.

51. The semiconductor device of claim 50, wherein the first segment and the second segment of the gate runner each extend along a periphery of the active region.

52. The semiconductor device of claim 50, wherein the gate runner further comprises a third segment and a fourth segment, and wherein the first to fourth segments define respective first to fourth sides of a hexagon when viewed in plan view.

53. The semiconductor device of claim 50, wherein a gate pad of the MOSFET is located in the center of an active area, and wherein the gate runner includes a plurality of additional segments extending radially outward from the gate pad.

54. The semiconductor device of claim 53, wherein the plurality of additional segments are radially spaced 60° apart from each other.

55. The semiconductor device of claim 53, wherein the semiconductor die is a hexagonal shaped semiconductor die.

56. A semiconductor device comprising: A semiconductor die, the semiconductor die comprising: a semiconductor layer structure comprising an active region; and A gate runner is located on the semiconductor layer structure, and includes a first segment, a second segment, and a third segment extending along a first crystal axis, a second crystal axis, and a third crystal axis, respectively, of a semiconductor substrate of the semiconductor layer structure.

57. The semiconductor device of claim 56, wherein the first segment, the second segment, and the third segment of the gate runner each extend along a periphery of the active region.

58. The semiconductor device of claim 56, wherein the gate runner further comprises a fourth segment, and wherein the first through fourth segments define respective first through fourth sides of a hexagon when viewed in plan view.

59. The semiconductor device of any one of claims 56-58, wherein the semiconductor die is a hexagonal shaped semiconductor die.

60. A semiconductor device comprising: a semiconductor layer structure comprising an active region; a gate pad located on the semiconductor layer structure; as well as A plurality of gate runner segments extend radially from the gate pad to corners of the semiconductor die.

61. The semiconductor device of claim 60, wherein the gate pad is located at a central portion of the active region.

62. The semiconductor device of claim 60, further comprising an additional plurality of gate runner segments extending along a periphery of the active region.

63. The semiconductor device of any one of claims 60-62, wherein the semiconductor die is a hexagonal shaped semiconductor die.

64. The semiconductor device of any one of claims 60 to 62, wherein the gate pad is located at the center of the active area.

65. The semiconductor device of any one of claims 60 to 62, wherein the semiconductor layer structure comprises a 4H silicon carbide substrate.

66. A semiconductor device as described in any of the above claims, wherein the semiconductor die is a first semiconductor die and has a maximum stress level that is at least 20% lower than the maximum stress level in a second semiconductor die, and except that the second semiconductor die has a rectangular shape, the second semiconductor die is identical to the first semiconductor die.

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