Error correction device, control circuit, storage medium, and error correction method

Abstract

An error correction device (20) that performs 2-bit error correction decoding using a block error correction code is provided with: a syndrome generation unit (1) that generates a syndrome pattern from a reception sequence; an error number determination unit (2) that determines the number of bit errors in the reception sequence on the basis of the syndrome pattern; and a 2-bit error candidate correction unit (5) that, when the error number determination unit (2) determines that there is a 2-bit error and there is a possibility of correction, calculates a first parameter on the basis of the correction sub-pattern, excludes the first parameter that is determined to be non-correctable for the 2-bit error from the first parameter, and corrects the 2-bit error candidate using a second parameter obtained by performing 1-bit degradation on the first parameter, and corrects the 2-bit error candidate using the second parameter that is determined to be non-correctable for the 2-bit error candidate correction unit (5). The first parameter, which is a constant term of a normalized polynomial obtained by normalizing a quadratic error position polynomial, is a normalized parameter, and the normalized root is obtained for the 2-bit error.

Description

Technical Field

[0001] The present disclosure relates to an error correction device, a control circuit, a storage medium, and an error correction method for correcting errors generated in wireless communication. Background Art

[0002] Conventionally, in 2-bit error correction using a block error correction code such as a Bose Chaudhuri Hocquenghem code, the syndrome pattern S1=α obtained by syndrome calculation is used. i +α j , S3=α 3i +α 3j , construct the error position polynomial X of degree 2 2 +σ1X+σ2, thus finding the quadratic error position polynomial X 2 +σ1X+σ2 roots. In addition, α i , α j is an element of the finite field that corresponds one-to-one to the error position, i≠j, and "+" is the addition operation on the finite field. In addition, σ1=α i +α j ,σ2=α i α j , “·” is a multiplication operation over a finite field.

[0003] For example, Patent Document 1 discloses the following technique: when finding the root, the quadratic error position polynomial X 2 +σ1X+σ2 to normalize and find the normalized polynomial Y 2 +Y+P, use parameter P as the address to find the root y through table lookup, perform multiplication or addition on the root y, and find α indicating the error position i , α j In addition, P = σ2 / σ1 2 , “ / ” is the division operation on a finite field. Here, the parameter P is P = (α i α j ) / (α i +α j ) 2 =S3 / S1 3 +1, root y through y = α i / (α i +α j ) to find out.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 01 / 084719 Summary of the Invention

[0007] Problems to be solved by the invention

[0008] However, according to the above prior art, when the normalized polynomial Y 2 In the table search for the root y of the parameter P of +Y+P, the root y is output using the parameter P as the address. Therefore, for example, in the case of the finite field GF(2 8 ) is a BCH code with a code length of 255 bits and an information bit length of 239 bits. The parameter P is 8 bits and the root y is 8 bits, so a table of 8 bits and 256 words is required. 16 In a BCH code with a code length of 65535 bits and an information bit length of 65503 bits, the parameter P is 16 bits, the root y is 16 bits, and a 16-bit table of 65536 words is required. This increases the size of the table required for table lookup and the circuit scale of the device.

[0009] The present disclosure has been made in view of the above-mentioned circumstances, and an object of the present disclosure is to provide an error correction device capable of suppressing an increase in circuit scale.

[0010] Means for solving problems

[0011] To solve the above-mentioned problems and achieve the purpose, the present invention discloses an error correction device for performing 2-bit error correction decoding using a block error correction code. The error correction device is characterized by comprising: a syndrome generation unit that generates a syndrome pattern based on a received sequence; an error count determination unit that determines the number of bit errors in the received sequence based on the syndrome pattern; and a 2-bit error candidate correction unit that, when the error count determination unit determines that a 2-bit error exists and is possibly correctable, calculates a first parameter based on the syndrome pattern, excludes the first parameter determined to be an uncorrectable 2-bit error from the first parameter, and uses a second parameter obtained by performing a 1-bit degeneration on the first parameter to determine a normalized root for the 2-bit error. The first parameter is a constant term of a normalized polynomial obtained by normalizing a quadratic error location polynomial and is a normalized parameter.

[0012] Effects of the Invention

[0013] The error correction device of the present disclosure has the effect of being able to suppress an increase in circuit scale. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is a diagram showing a configuration example of an error correction device according to the first embodiment.

[0015] Figure 2 This is a flowchart showing the operation of the error correction device according to the first embodiment.

[0016] Figure 3 This is a diagram showing an example of a table required for table lookup when finding a root from a normalization parameter as a comparative example.

[0017] Figure 4 This is a diagram showing an example of a degenerate normalized root table used in the degenerate normalized root acquisition unit included in the error correction device according to the first embodiment.

[0018] Figure 5 This is a diagram showing a configuration example of a processing circuit in which the processing circuit realizing the error correction device according to the first embodiment is constituted by a processor and a memory.

[0019] Figure 6 This is a diagram showing an example of a processing circuit in the case where the processing circuit of the error correction device according to the first embodiment is configured by dedicated hardware. DETAILED DESCRIPTION

[0020] Hereinafter, an error correction device, a control circuit, a storage medium, and an error correction method according to embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0021] Implementation Method 1

[0022] Figure 1 This diagram shows an example configuration of an error correction device 20 according to Embodiment 1. Error correction device 20 performs 2-bit error correction decoding using a block error correction code such as a BCH code, and corrects errors of 2 bits or less in an input received sequence. Error correction device 20 includes a syndrome generation unit 1, an error count determination unit 2, a determination result processing unit 3, a 2-bit error candidate correction unit 5, a selection unit 10, an error position conversion unit 11, a delay unit 12, and a correction unit 13. The determination result processing unit 3 includes a 1-bit error correction operation unit 4. The 2-bit error candidate correction unit 5 includes a 2-bit error correction normalization operation unit 6, an uncorrectable determination unit 7, a degenerate normalization root acquisition unit 8, and a 2-bit error position calculation unit 9.

[0023] The syndrome generator 1 generates syndrome patterns S1 and S3 based on a branched received sequence among the received sequences input to the error correction device 20. The received sequence is, for example, a received sequence received by a receiving device (not shown) having the error correction device 20 via wireless communication, but is not limited thereto.

[0024] The error count determination unit 2 determines the number of bit errors in the received sequence input to the error correction device 20 based on the syndrome patterns S1 and S3 generated by the syndrome generation unit 1. Specifically, the error count determination unit 2 determines whether there is no error, a 1-bit error, an uncorrectable error, or a 2-bit error candidate based on the syndrome patterns S1 and S3. As described later, a 2-bit error candidate is the result of the 2-bit error candidate correction unit 5 determining whether a 2-bit error is correctable or uncorrectable, that is, the result of the determination that a 2-bit error exists and is possibly correctable.

[0025] The determination result processing unit 3 processes the determination results other than the 2-bit error candidates (specifically, the determination results of no error, 1-bit error, and uncorrectable) in the error number determination unit 2 .

[0026] The 1-bit error correction calculation unit 4 calculates an element indicating a 1-bit error position based on the 1-bit error determination result by the error number determination unit 2 .

[0027] When the error number determination unit 2 determines that the 2-bit error candidate is correctable, the 2-bit error candidate correcting unit 5 calculates the element indicating the 2-bit error position or determines that the error is uncorrectable.

[0028] The 2-bit error correction normalization operation unit 6 uses the finite field GF(2 8 ) over the original polynomial X of the extended field 8 +X 4 +X 3 +X 2 + 1 to calculate the normalization parameter P, which is a constant term of the normalization polynomial obtained by normalizing the quadratic error position polynomial and is a normalized parameter. In the following description, the normalization parameter P may be referred to as the first parameter.

[0029] The uncorrectable error determination unit 7 determines whether or not a 2-bit error candidate is uncorrectable based on the normalization parameter P calculated by the 2-bit error correction normalization calculation unit 6 .

[0030] If the result of the determination by the uncorrectable determination unit 7 is that the condition is correctable, the degenerate normalization root acquisition unit 8 determines the root y from the degenerate normalization root table 8a, which uses as an address a parameter P1 obtained by degenerating the normalization parameter P. In the following description, the parameter P1 may be referred to as the second parameter.

[0031] The 2-bit error position calculation unit 9 obtains the element α of the finite field representing the 2-bit error based on the root y obtained from the degenerate normalized root acquisition unit 8. i , α j .

[0032] The selection unit 10 selects an output to the error position conversion unit 11 according to the state of each error number.

[0033] When the output from the selection unit 10 is a 1-bit error or a 2-bit error, the error position conversion unit 11 converts the elements of the finite field indicating error positions into error positions using an error position conversion table 11a.

[0034] The delay unit 12 delays the branched reception sequence input to the error correction device 20 by the processing time from the syndrome generation unit 1 to the error position conversion unit 11 .

[0035] The correction unit 13 corrects the corresponding bits of the received sequence delayed by the delay unit 12 based on the error position acquired from the error position conversion unit 11 .

[0036] Next, the operation of the error correction device 20 will be described. Figure 2 This is a flowchart showing the operation of the error correction device 20 according to the first embodiment. Figure 2 As a specific example, the use of the finite field GF(2 8 ) in the extended field of the primitive polynomial X 8 +X 4 +X 3 +X 2 +1 is a diagram showing the operation of the error correction device 20 when the BCH code is 255 bits long and the information bit length is 239 bits. Figure 2 In the example, steps ST1 to ST13 are divided by five dotted quadrilaterals, and the numbers assigned to the quadrilaterals are the same as those in the example above. Figure 1 The reference numerals of the components of the error correction device 20 are the same. Figure 2 The reference numerals shown indicate the structure of the error correction device 20 that performs the operation of each step.

[0037] In the error correction device 20, the syndrome generator 1 generates syndrome patterns S1 and S3 based on a branched received sequence among the received sequences input to the error correction device 20 (step ST1). The syndrome generator 1 outputs the generated syndrome patterns S1 and S3 to the error count determination unit 2.

[0038] The error count determination unit 2 determines the number of errors based on the syndrome patterns S1 and S3 generated by the syndrome generation unit 1. Specifically, when S1 = S3 = 0 (step ST2: Yes), the error count determination unit 2 outputs the syndrome patterns S1 and S3 and the error-free determination result to the determination result processing unit 3. Since the determination result obtained from the error count determination unit 2 is error-free (step ST3), the determination result processing unit 3 outputs the syndrome patterns S1 and S3 and the error-free determination result directly to the selection unit 10.

[0039] When at least one of S1 and S3 is not 0 (step ST2: No) and S1 = 0, that is, when S1 = 0 and S3 ≠ 0 (step ST4: Yes), the error number determination unit 2 outputs the syndrome patterns S1 and S3 and the uncorrectable determination result to the determination result processing unit 3. Since the determination result obtained from the error number determination unit 2 is uncorrectable (step ST5), the determination result processing unit 3 outputs the syndrome patterns S1 and S3 and the uncorrectable determination result directly to the selection unit 10.

[0040] The error number determination unit 2 is in the state where S1≠0 (step ST4: No) and S1 3 +S3=0, that is, S1≠0 and S3≠0 and S1 3 If +S3 = 0 (step ST6: Yes), the syndrome patterns S1 and S3 and the result of the one-bit error determination are output to the determination result processing unit 3. Note that "+" represents an addition operation on a finite field. In the determination result processing unit 3, the one-bit error correction calculation unit 4 calculates the element of the finite field indicating the position of the one-bit error, based on the one-bit error determination result from the error number determination unit 2. Specifically, the one-bit error correction calculation unit 4 calculates the element X1 = S1 of the finite field indicating the position of the one-bit error (step ST7) and outputs it to the selection unit 10.

[0041] The error number determination unit 2 in S1 3 +S3≠0, that is, S1≠0 and S3≠0 and S1 3 When +S3≠0 (step ST6 : NO), the syndrome patterns S1 and S3 and the judgment result of the 2-bit error candidate are output to the 2-bit error candidate correction unit 5 .

[0042] The 2-bit error candidate correction unit 5 can also use the syndrome patterns S1 and S3 as input parameters and find the 2-bit error position by table lookup. 8 ) in the extended field of the primitive polynomial X 8 +X 4 +X 3 +X 2In a BCH code with a code length of 255 bits and an information bit length of 239 bits, the 2-bit error candidate correction unit 5 needs to output a 65,536-word table with 16 bits. Therefore, compared to the case of determining a 2-bit error position using syndrome patterns S1 and S3 as input parameters, the 2-bit error candidate correction unit 5 performs normalization to reduce the size of the table required for table lookup.

[0043] In the 2-bit error candidate correction unit 5, first, when the error number determination unit 2 determines that the candidate is a 2-bit error candidate, the 2-bit error correction normalization calculation unit 6 calculates the normalization parameter P = S3 / S1 based on the syndrome patterns S1 and S3 obtained from the error number determination unit 2. 3 +1, the normalization parameter P is a constant term of the normalization polynomial obtained by normalizing the quadratic error position polynomial and is a normalized parameter (step ST8). The 2-bit error correction normalization operation unit 6 outputs the syndrome patterns S1 and S3 and the normalization parameter P obtained by the operation to the uncorrectable determination unit 7. In addition, " / " is a division operation on a finite field. In addition, Figure 2 In FIG, “Adr[7:0]” is used to represent the normalization parameter P.

[0044] The 2-bit error candidate correction unit 5 can also use the normalization parameter P as an address to find the root y, but for example, in the primitive polynomial X 8 +X 4 +X 3 +X 2 +1, need to Figure 3 Table shown. Figure 3 : is a diagram showing an example of a table required for table lookup when finding the root y based on the normalization parameter P as a comparative example. Figure 3 In , address (P) is used to indicate that the normalization parameter P is set to the address. Figure 3 In the address (P), the vertical direction represents the high-order bits, and the horizontal direction represents the low-order four bits. Here, an address (P) that outputs an input value of 0, i.e., normalization parameter P, becomes uncorrectable. In this embodiment, focusing on the address (P) that outputs 0, i.e., normalization parameter P, uncorrectable determination unit 7 determines whether a 2-bit error candidate is uncorrectable based on normalization parameter P.

[0045] exist Figure 3In the example, when P=0, or when the normalization parameter P is set to an 8-bit address and the LSB (Least Significant Bit) is set to bit 0 and the fifth bit from the LSB is 1, the error is uncorrectable. Therefore, when P=0, or when the normalization parameter P is set to an 8-bit address and the fifth bit from the LSB is 1 (step ST9: Yes), the uncorrectable determination unit 7 determines that the error is uncorrectable (step ST10), and outputs the syndrome patterns S1 and S3 and the determination result of uncorrectable to the selection unit 10. In addition, in Figure 2 In the example, "Adr[7:0] = 0" indicates the case where P = 0, and "Adr[5] = 1" indicates the case where the fifth bit from the LSB is 1. Thus, uncorrectable determination unit 7 preemptively excludes cases where the normalization parameter P is set to an 8-bit address and the fifth bit from the LSB is 1 as uncorrectable from the 2-bit correction process. In other words, uncorrectable determination unit 7 can exclude normalization parameters P that have been determined to be uncorrectable due to a 2-bit error from the normalization parameter P. In the following description, the LSB may be referred to as the least significant bit.

[0046] If P≠0, the normalization parameter P is set to an 8-bit address, and the fifth bit from the LSB is not 1 (step ST9: No), the uncorrectable determination unit 7 determines the 2-bit error candidate as correctable. The uncorrectable determination unit 7 outputs the syndrome patterns S1 and S3 and the correctable determination result to the degenerate normalization root acquisition unit 8. If the uncorrectable determination unit 7 determines the 2-bit error candidate as correctable, the degenerate normalization root acquisition unit 8 calculates the root y from the degenerate normalization root table 8a, which uses the parameter P1 obtained by degenerating the normalization parameter P as the address.

[0047] Figure 4 This is a diagram showing an example of the degenerate normalization root table 8 a used in the degenerate normalization root acquisition unit 8 included in the error correction device 20 according to the first embodiment. Figure 4 The degenerate normalized root shown in Table 8a is about Figure 3 The table shown excludes the 7-bit parameter P1, which is the fifth bit from the LSB of the normalization parameter P. The degenerate normalization root acquisition unit 8 Figure 4 The degenerate normalized root table 8a shown in FIG. 8 outputs the root y (step ST11). Figure 2 In the example, the degenerate normalized root table 8a is represented as a table of 7-bit addresses (P1) {"set to Adr[7:6], Adr[4:0]}". The degenerate normalized root acquisition unit 8 outputs the root y and the syndrome patterns S1 and S3 to the 2-bit error position calculation unit 9. If the uncorrectable error determination unit 7 determines that the 2-bit error candidate is correctable, the root y output from the degenerate normalized root acquisition unit 8 is y = αi / (α i +α j ) In this way, the degenerate normalized root acquisition unit 8 can obtain the normalized root y for a 2-bit error using the parameter P1 obtained by degenerating the normalization parameter P by 1 bit.

[0048] The 2-bit error position calculation unit 9 calculates the element of the finite field representing the 2-bit error position using the root y obtained from the degenerate normalized root acquisition unit 8 and the syndrome patterns S1 and S3. Specifically, the 2-bit error position calculation unit 9 obtains the element X1=α of the finite field representing the 2-bit error position. i =y·S1, X2=α j =X1+S1 (step ST12), and outputs it to the selection unit 10. In addition, "·" is a multiplication operation on a finite field.

[0049] The selection unit 10 performs selection processing on the calculation results obtained from the judgment result processing unit 3 or the 2-bit error candidate correction unit 5 (step ST13). When the selection unit 10 obtains the element X1=S1 of the finite field indicating the 1-bit error position from the 1-bit error correction calculation unit 4 of the judgment result processing unit 3, the element X1=S1 of the finite field indicating the 1-bit error position is output to the error position conversion unit 11. When the selection unit 10 obtains the element X1=α of the finite field indicating the 2-bit error position from the 2-bit error position calculation unit 9 of the 2-bit error candidate correction unit 5, the element X1=α of the finite field indicating the 2-bit error position is output to the error position conversion unit 11. i =y·S1, X2=α j =X1+S1, the element X1 of the finite field representing the 2-bit error position is set to α i =y·S1, X2=α j =X1+S1 is output to the error position conversion unit 11.

[0050] The error position conversion unit 11 obtains from the selection unit 10 an element X1=S1 of the finite field indicating a 1-bit error position or an element X1=α of the finite field indicating a 2-bit error position. i =y·S1, X2=α j =X1+S1, the error position conversion table 11a is used to convert the elements of the finite field representing the error positions into error positions, and the error positions obtained by the conversion are output to the correction unit 13. Furthermore, even when it is determined that there is no error or that the error position is uncorrectable, the error position conversion unit 11 can use the error position conversion table 11a to convert positions other than the target error positions.

[0051] The correction unit 13 corrects the corresponding bit of the received sequence delayed by the delay unit 12 based on the error position obtained from the error position conversion unit 11 , that is, inverts the corresponding bit to complete the correction and outputs it.

[0052] Thus, in the error correction device 20, when the 2-bit error candidate correcting unit 5 determines that the error number determination unit 2 is a 2-bit candidate, it calculates the normalization parameter P based on the syndrome patterns S1 and S3. The normalization parameter P is a normalized parameter obtained by normalizing the quadratic error location polynomial. The 2-bit error candidate correcting unit 5 excludes the normalization parameter P determined as an uncorrectable 2-bit error from the normalization parameter P and uses the parameter P1 obtained by degenerating the normalization parameter P by 1 bit to find the normalized root y for the 2-bit error. Specifically, the 2-bit error candidate correcting unit 5 uses the original polynomial X in the extended field over the finite field. 8 +X 4 +X 3 +X 2 +1, when at least the LSB is set to the 0th bit and the 5th bit from the LSB is set to 1 in the normalized 8-bit normalization parameter P, it is determined to be an uncorrectable 2-bit error, and the normalized root y is calculated using the parameter P1 that is degraded by deleting the 5th bit from the LSB from the normalization parameter P.

[0053] Next, the hardware structure of error correction device 20 will be described. In error correction device 20, the syndrome generator 1, error count determination unit 2, determination result processing unit 3, 2-bit error candidate correction unit 5, selection unit 10, error position conversion unit 11, delay unit 12, and correction unit 13 are implemented by processing circuits. The processing circuits can be a processor and memory that executes a program stored in memory, or dedicated hardware. Processing circuits are also called control circuits.

[0054] Figure 5 1 is a diagram showing a configuration example of a processing circuit 90 in which a processor 91 and a memory 92 constitute a processing circuit for realizing the error correction device 20 according to the first embodiment. Figure 5 The processing circuit 90 shown is a control circuit having a processor 91 and a memory 92. When the processing circuit 90 is composed of the processor 91 and the memory 92, the various functions of the processing circuit 90 are implemented by software, firmware, or a combination of software and firmware. The software or firmware is described as a program and stored in the memory 92. In the processing circuit 90, the processor 91 reads and executes the program stored in the memory 92, thereby implementing the various functions. In other words, the processing circuit 90 has a memory 92 for storing a program that results in the execution of the processing of the error correction device 20. This program can also be said to be a program for causing the error correction device 20 to execute the various functions implemented by the processing circuit 90. This program can be provided by a storage medium storing the program, or it can be provided by other means such as a communication medium.

[0055] It can be said that the above program is a program for the error correction device 20 to execute the following steps: Step 1, the syndrome generation unit 1 generates syndrome patterns S1 and S3 based on the received sequence; Step 2, the error number determination unit 2 determines the number of bit errors in the received sequence based on the syndrome patterns S1 and S3; and Step 3, when the 2-bit error candidate correction unit 5 determines that the error number determination unit 2 determines that the error is a 2-bit error candidate, it calculates a normalization parameter P based on the syndrome patterns S1 and S3, excludes the normalization parameter P determined as an uncorrectable 2-bit error from the normalization parameter P, and uses the parameter P1 obtained by performing 1-bit degeneration on the normalization parameter P to determine the normalized root y for the 2-bit error, wherein the normalization parameter P is a constant term of the normalization polynomial obtained by normalizing the quadratic error location polynomial and is a normalized parameter.

[0056] Here, the processor 91 is, for example, a CPU (Central Processing Unit), a processing device, an arithmetic device, a microprocessor, a microcomputer, or a DSP (Digital Signal Processor). Furthermore, the memory 92 is, for example, a non-volatile or volatile semiconductor memory such as RAM (Random Access Memory), ROM (Read Only Memory), flash memory, EPROM (Erasable Programmable ROM), EEPROM (registered trademark) (Electrically EPROM), a magnetic disk, a floppy disk, an optical disk, a compact disk, a minidisc, or a DVD (Digital Versatile Disc).

[0057] Figure 6 This diagram shows an example of a processing circuit 93 in the case where the processing circuit of the error correction device 20 according to the first embodiment is implemented by a dedicated hardware configuration. Figure 6 The processing circuit 93 shown may be, for example, a single circuit, a complex circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or a combination thereof. The processing circuit may be partially implemented using dedicated hardware and partially implemented using software or firmware. Thus, the processing circuit can implement the aforementioned functions using dedicated hardware, software, firmware, or a combination thereof.

[0058] As described above, according to this embodiment, error correction device 20 preliminarily determines uncorrectable errors using normalization parameter P when processing 2-bit error correction candidates. Through simple processing, it generates parameter P1, which is obtained by reducing the input address by one bit from normalization parameter P, and then calculates root y based on parameter P1. Consequently, error correction device 20 can calculate root y using a table that is half the size of a table calculated using normalization parameter P, thereby reducing circuit size.

[0059] In addition, in this embodiment, a BCH code with a code length of 255 bits and an information bit length of 239 bits is shown as an example, but the same processing can also be performed on a BCH code with a 2-bit error correction and 3-bit error detection, in which the parity bit is increased by 1 bit and the information bit length is 238 bits.

[0060] The same processing can also be performed on an extended BCH code with 2-bit error correction and 3-bit error detection, which has a code length of 256 bits and an information bit length of 239 bits, with the parity bit increased by 1 bit.

[0061] Even with shortened codes that shorten the bit lengths of these information, additional processing for uncorrectable determination in the error position conversion unit 11 is required, but similar processing can be performed.

[0062] Implementation Method 2

[0063] In the first embodiment, the error correction device 20 is used for the finite field GF(2 8 ) in the extended field of the primitive polynomial X 8 +X 4 +X 3 +X 2 A 2-bit error correction candidate in a BCH code with a code length of 255 bits and an information bit length of 239 bits, consisting of a 1-bit code length, is pre-determined to be uncorrectable based on the normalization parameter P. A root y is then determined from the degenerate normalized root table 8a. In the degenerate normalized root table 8a, the parameter P1, obtained by degenerating one bit through a simple process, is used as an address, and the table size is set to 1 / 2. The error correction device 20 can also use the degenerate normalized root table with the table size set to 1 / 2 for other primitive polynomials. However, when generating the parameter P1 obtained by degenerating one bit from the normalization parameter P, whether the parameter P1 can be generated through a simple process depends on the primitive polynomial used.

[0064] For example, consider an extended field GF(2 16 ) of the original polynomial X 16 +X 12 +X3 +X+1. When normalization parameter P = 0 and P is set to a 16-bit address, the table outputting the root y is a 16-bit output and consists of 65536 words. However, when the hexadecimal representation is 2000-2FFF, 3000-3FFF, 6000-6FFF, 7000-7FFF, 8000-8FFF, 9000-9FFF, C000-CFFF, and D000-DFFF, the 16-bit root y is all 0, making it uncorrectable. Therefore, uncorrectable determination unit 7 of error correction device 20 performs an exclusive OR operation between the MSB (Most Significant Bit) and the second bit from the MSB, or the 13th bit from the LSB when the LSB is set to bit 0. If the result is 1, the result is deemed uncorrectable and excluded from the 2-bit correction process. In the following description, the MSB may be referred to as the most significant bit.

[0065] The degenerate normalized root acquisition unit 8 of the error correction device 20 uses the degenerate normalized root table 8a, which moves the data of the root y in the normalization parameter P with non-zero values ​​of A000 to BFFF to the output of the root y in the normalization parameter P, and moves the data of the root y in the normalization parameter P with non-zero values ​​of E000 to FFFF to the output of the root y in the normalization parameter P, thereby being able to calculate the root y based on the 15-bit parameter P1 from which the MSB of the normalization parameter P is removed.

[0066] Thus, using the extended field GF(2 16 ) of the original polynomial X 16 +X 12 +X 3 In the case of +X+1, when at least the LSB is set to the 0th bit in the normalized 16-bit normalization parameter P and the exclusive OR of the 13th bit from the LSB and the MSB is 1, the 2-bit error candidate correction unit 5 determines that it is an uncorrectable 2-bit error, and uses the parameter P1 degraded by deleting the MSB from the normalized parameter P to calculate the normalized root y.

[0067] As described above, according to this embodiment, it is assumed that the error correction device 20 has an extended field GF(2 16 ) of the original polynomial X 16 +X 12 +X 3 In processing the 2-bit error correction candidate of +X+1, the normalization parameter P is used to pre-determine that the error is uncorrectable. A simple process generates parameter P1, which is obtained by reducing the input address by one bit from normalization parameter P. The root y is then calculated based on parameter P1. This allows error correction device 20 to calculate the root y using a table that is half the size of a table calculated using normalization parameter P, thereby reducing circuit size.

[0068] In addition, even when using various extended fields GF(2 n ), the error correction device 20 also uses the normalization parameter P to pre-determine that it is uncorrectable, similarly to the first or second embodiment, generates a parameter P1 obtained by reducing the input address by 1 bit from the normalization parameter P through simple processing, and calculates the root y based on the parameter P1. As a result, compared with the case of using the normalization parameter P to calculate the root y, the root y can be calculated using a table of 1 / 2 size, thereby reducing the circuit scale.

[0069] The configuration described in the above embodiment is merely an example, and can be combined with other known technologies, the embodiments can be combined with each other, and part of the configuration can be omitted or modified without departing from the spirit of the invention.

[0070] Description of labels

[0071] 1: Synchronization sub-unit; 2: Error number determination unit; 3: Determination result processing unit; 4: 1-bit error correction operation unit; 5: 2-bit error candidate correction unit; 6: 2-bit error correction normalization operation unit; 7: Uncorrectable determination unit; 8: Degenerate normalization root acquisition unit; 8a: Degenerate normalization root table; 9: 2-bit error position operation unit; 10: Selection unit; 11: Error position conversion unit; 11a: Error position conversion table; 12: Delay unit; 13: Correction unit; 20: Error correction device; 90, 93: Processing circuit; 91: Processor; 92: Memory.

Claims

1. An error correction device that performs 2-bit error correction decoding using a block error correction code, characterized in that: The error correction device comprises: a syndrome generating unit, which generates a syndrome pattern according to a received sequence; an error number determination unit configured to determine the number of bit errors in the received sequence based on the syndrome pattern; as well as a 2-bit error candidate correcting unit that, when the error number determining unit determines that a 2-bit error exists and is possibly correctable, calculates a first parameter based on the syndrome pattern, excludes from the first parameter the first parameter determined to be uncorrectable for the 2-bit error, and uses a second parameter obtained by performing 1-bit degeneration on the first parameter to obtain a normalized root for the 2-bit error, wherein the first parameter is a constant term of a normalized polynomial obtained by normalizing a quadratic error location polynomial and is a normalized parameter.

2. The error correction device according to claim 1, characterized in that The 2-bit error candidate correction unit uses the primitive polynomial X of the extended field over the finite field. 8 +X 4 +X 3 +X 2 +1, when at least the least significant bit is set to bit 0 and the fifth bit from the least significant bit is set to 1 in the normalized 8-bit first parameter, it is determined that the 2-bit error is uncorrectable, and the normalized root is calculated using the second parameter that is degraded by deleting the fifth bit from the least significant bit from the first parameter.

3. The error correction device according to claim 1, wherein: The 2-bit error candidate correction unit uses the primitive polynomial X of the extended field over the finite field. 16 +X 12 +X 3 In the case of +X+1, when at least the least significant bit in the normalized 16-bit first parameter is set to bit 0 and the exclusive OR between the 13th bit from the least significant bit and the most significant bit is 1, it is determined that the 2-bit error is uncorrectable, and the normalized root is calculated using the second parameter degenerated by deleting the most significant bit from the first parameter.

4. A control circuit for controlling an error correction device that performs 2-bit error correction decoding using a block error correction code, characterized in that: The control circuit causes the error correction device to perform the following processing: generating a syndrome pattern according to a received sequence; determining a number of bit errors in the received sequence based on the syndrome pattern; as well as When it is determined that a 2-bit error exists and there is a possibility of correction, a first parameter is calculated based on the syndrome pattern, the first parameter determined to be uncorrectable for the 2-bit error is excluded from the first parameter, and a second parameter obtained by performing 1-bit degeneration on the first parameter is used to calculate a normalized root for the 2-bit error, wherein the first parameter is a constant term of a normalized polynomial obtained by normalizing a quadratic error location polynomial and is a normalized parameter.

5. A storage medium storing a program for controlling an error correction device that performs 2-bit error correction decoding using a block error correction code, characterized in that: The program causes the error correction device to perform the following processing: generating a syndrome pattern according to a received sequence; determining a number of bit errors in the received sequence based on the syndrome pattern; as well as When it is determined that a 2-bit error exists and there is a possibility of correction, a first parameter is calculated based on the syndrome pattern, the first parameter determined to be uncorrectable for the 2-bit error is excluded from the first parameter, and a second parameter obtained by performing 1-bit degeneration on the first parameter is used to calculate a normalized root for the 2-bit error, wherein the first parameter is a constant term of a normalized polynomial obtained by normalizing a quadratic error location polynomial and is a normalized parameter.

6. An error correction method for an error correction device that performs 2-bit error correction decoding using a block error correction code, characterized in that: The error correction method comprises the following steps: In step 1, a syndrome generation unit generates a syndrome pattern according to a received sequence; In a second step, an error number determination unit determines the number of bit errors in the received sequence based on the syndrome pattern; as well as In step 3, when the error number determination unit determines that a 2-bit error exists and there is a possibility of correction, the 2-bit error candidate correction unit calculates a first parameter based on the syndrome pattern, excludes the first parameter determined to be uncorrectable for the 2-bit error from the first parameter, and uses a second parameter obtained by performing 1-bit degeneration on the first parameter to obtain a normalized root for the 2-bit error, wherein the first parameter is a constant term of a normalized polynomial obtained by normalizing a quadratic error location polynomial and is a normalized parameter.

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