Chip testing method and device

Abstract

The invention provides a chip testing method and device, and belongs to the technical field of chip testing. The method comprises the steps that an intermediate clock with the frequency the same as that of an input channel-associated clock in a test excitation signal is generated through a high-frequency clock signal, and the frequency of the high-frequency clock signal is larger than that of the input channel-associated clock; adjusting the phase of the intermediate clock according to the time sequence parameter of each tested chip, and generating a phase correction associated clock; and replacing the input associated clock based on the phase correction associated clock to update the test excitation signal so as to test each tested chip by using the updated test excitation signal. Independent time sequence compensation of each chip is achieved through high-frequency signal dynamic high-precision phase adjustment, the limitation of a traditional single time sequence parameter is broken through, and flexible consideration of the test rate and the test number is achieved. From the aspect of deployment, the design process and the file format of the original test system do not need to be modified, the compatibility is good, the universality and the deployment efficiency are improved, and the deployment cost is reduced.

Description

Technical Field

[0001] The present disclosure relates to the field of chip testing technology, and in particular to a chip testing method and device. Background Art

[0002] During the chip testing and burn-in phase, pre-designed test vectors, such as scan test (Scan FT), IP core test (IPTest), and memory built-in self-test (MBist), are input as stimulus signals to the chip under test. These vectors drive the chip's internal circuitry to operate according to preset states and generate corresponding output responses. By capturing the output signals in real time and comparing them with expected values, the chip's functional status can be accurately determined, enabling qualified product screening.

[0003] The input and output of test patterns typically represent multiple parallel digital signal streams. During testing, the chip is mounted on a dedicated load board, and the test equipment transmits parallel data via the board's high-speed connectors. It's important to note that test patterns not only contain valid data but also require an accompanying clock signal, which ensures that the chip latches the data at specific edges.

[0004] Existing chip testing solutions are limited by the fact that test vectors such as Scan FT, IP Test, and MBist only support a single set of timing parameter configurations. Practical applications face two constraints: First, to achieve high-speed testing, the timing must be fine-tuned based on electrical characteristics such as the carrier board's dielectric constant and trace length to meet the chip's setup / hold time requirements. This forces each carrier board to only accommodate a single chip, which ensures speed but sacrifices parallel efficiency. Second, when a single carrier board integrates multiple chips to increase the test scale, the transmission delay of the signal to each chip varies significantly, and the test vector cannot provide multiple sets of independent timing parameters. Therefore, the rate can only be reduced by 1-2 orders of magnitude, and the risk of signal failure is avoided by relaxing the timing margin. Summary of the Invention

[0005] The present disclosure provides a chip testing method and apparatus. The technical solution of the present disclosure is implemented as follows: In a first aspect, the present disclosure provides a chip testing method, the method comprising: Generate an intermediate clock with the same frequency as the input accompanying clock in the test stimulus signal through a high-frequency clock signal, wherein the frequency of the high-frequency clock signal is greater than the input accompanying clock; Adjusting the phase of the intermediate clock according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock; The input associated clock is replaced based on the phase-corrected associated clock to update the test stimulus signal, so as to test each chip under test using the updated test stimulus signal.

[0006] In a second aspect, the present disclosure provides a chip testing device, which includes a frequency adjustment part, a phase adjustment part, and an update part, wherein: The frequency adjustment part is used to generate an intermediate clock with the same frequency as the input accompanying clock in the test stimulus signal through a high-frequency clock signal, wherein the frequency of the high-frequency clock signal is greater than the input accompanying clock; The phase adjustment part is used to adjust the phase of the intermediate clock according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock; The updating part is used to replace the input associated clock based on the phase-corrected associated clock to update the test stimulus signal, so as to test each chip under test using the updated test stimulus signal.

[0007] The present disclosure provides a chip testing method and device, which realizes independent timing compensation for each chip by reconstructing a clock based on a high-frequency clock for each chip under test, and dynamically adjusting the phase of the reconstructed clock based on the timing parameters of each chip under test with high precision, so that the stimulus signal received by each chip under test can be independently optimized according to its actual timing requirements, breaking through the limitations of the traditional single timing parameter, and performing simultaneous testing of multiple chips without reducing the test rate, thus achieving a flexible balance between test rate and test quantity. From the deployment perspective, the use of high-frequency signals to regenerate test signals does not require reliance on the complex adjustment mechanism of the test equipment, retains the original test equipment, and does not require modification of the original test system design process and file format. It has good compatibility, improves the versatility and deployment efficiency of the system, and is suitable for a variety of test scenarios. Timing optimization can be achieved without replacing hardware or rewriting test programs, thereby significantly reducing deployment costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A schematic diagram of a chip testing method provided by the present disclosure.

[0009] Figure 2 A schematic diagram of the structure of a chip testing device provided by the present disclosure.

[0010] Figure 3 A connection diagram of a chip testing device embodiment provided by the present disclosure. DETAILED DESCRIPTION

[0011] The following will be combined with the drawings in this disclosure to clearly describe the technical solutions in the embodiments of the present disclosure. Obviously, the embodiments described are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this disclosure.

[0012] In chip testing, test vectors are pre-programmed digital instruction sets within the chip testing process. Their core function is to drive the chip and verify its behavior by simulating real-world operating scenarios. Test vectors typically include the following three components: First, the data signal layer, which contains multiple parallel or serial valid test data streams transmitted to the chip pins via a carrier board; second, the synchronization control layer, which provides accompanying clock signals to precisely lock the data sampling instant and define the rising or falling edge triggering mechanism; and third, the timing specification layer, which uses timing parameters to quantitatively describe the key constraints that must be met by the clock and data signals in the digital circuit in the time dimension. This ensures that the chip's internal logic states can correctly capture, process, and transmit data, avoiding metastability or logical errors. Timing parameters typically include clock-related parameters, data transmission-related parameters, and signal integrity-related parameters. Clock-related parameters include clock jitter, clock frequency, and clock rise / fall times; data transmission-related parameters include data setup time, hold time, and data arrival time; and signal integrity-related parameters include signal pulse width. The test equipment acts as a physical execution engine, converting the digital instructions in the test vector into actual electrical signals, namely test stimulus signals, and applies them to the chip pins for testing.

[0013] The test vectors in existing chip testing technologies only support a single set of timing parameter configurations. To achieve signal rates of hundreds of MHz, the timing needs to be finely adjusted based on the dielectric constant, trace length and other electrical parameters of the carrier board to meet the chip setup / hold time requirements. When a single chip is placed on each carrier board, the rate is guaranteed but the parallel efficiency is sacrificed. When a single carrier board integrates multiple chips, due to the difference in transmission delay of the signal to each chip, the test vector cannot provide multiple sets of independent timing parameters. The rate can only be reduced by 1-2 orders of magnitude, and the risk of signal failure is avoided by relaxing the timing margin. In actual engineering applications, increasing the test rate of a single chip requires reducing the number of parallel operations, while increasing the parallel scale is forced to significantly reduce the speed, which seriously restricts test efficiency and cost optimization. Based on this, if Figure 1 As shown, the present disclosure proposes a chip testing method, which includes S101 to S103: S101: Generate an intermediate clock having the same frequency as the input associated clock in the test stimulus signal using a high-frequency clock signal, wherein the frequency of the high-frequency clock signal is greater than the input associated clock; S102: Adjust the phase of the intermediate clock according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock; S103: Replace the input associated clock based on the phase-corrected associated clock to update the test stimulus signal, so as to test each chip under test using the updated test stimulus signal.

[0014] A high-frequency clock signal refers to a clock signal with a frequency greater than the frequency of the input accompanying clock signal in the test excitation signal, which can be provided by a high-frequency signal generator as input. The test excitation signal is output by the test equipment, including the input accompanying clock and input parallel data. The present disclosure processes the test excitation signal output by the test equipment and transmits it to the chip under test for testing without affecting or changing the design process, operation process, and file format of the original test system. First, an intermediate clock signal with the same frequency as the input accompanying clock is generated by the high-frequency clock signal. Due to its high frequency characteristics, the high-frequency clock signal can be flexibly generated according to actual application requirements through technical means such as frequency division or phase-locked loop synthesis to generate an intermediate clock signal consistent with the input accompanying clock frequency. Due to the different timing parameters of the different chips under test, such as the wiring length and chip data establishment time, the present disclosure independently adjusts the phase of the intermediate clock for each chip under test, generates a phase-corrected accompanying clock for each chip under test, and uses it to replace the input accompanying clock in the original test excitation signal and transmits it to each chip under test for testing. By regenerating a clock that matches the timing requirements of each chip under test based on the frequency of the input clock output by the test equipment and the timing parameters of each chip under test, it is possible to support simultaneous testing of multiple chips under test without reducing the test data rate. In addition, since the clock can be independently reconstructed for each test chip, there is no need to force all signal paths to be strictly equal in length, which reduces the difficulty of carrier board design. The reconstruction of the clock signal based on a high-frequency clock signal can more accurately track the input data jump edge and can also flexibly generate clock signals with multiple frequency levels to meet the needs of different test scenarios.

[0015] In some examples, for generating an intermediate clock with the same frequency as the input accompanying clock in the test stimulus signal through a high-frequency clock signal, the high-frequency clock signal can be divided by programmable division to generate an intermediate clock with the same frequency as the input accompanying clock in the test stimulus signal.

[0016] Dividing high-frequency clock signals offers simple hardware implementation, fast response, and highly deterministic clock signals without introducing additional jitter. A programmable divider is a circuit module that dynamically adjusts the division ratio through digital control. The division ratio can be configured in real time via a programming interface, enabling it to adapt to various test rates.

[0017] Specifically, the high-frequency clock frequency , generates an intermediate clock through programmable frequency division , its frequency The frequency of the input channel clock output by the test equipment Consistent:

[0018] In some examples, the phase of the intermediate clock is adjusted according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock. The phase of the intermediate clock can be adjusted using a high-frequency clock signal according to the timing parameters corresponding to each chip under test to obtain a phase-corrected accompanying clock corresponding to each chip under test.

[0019] High-frequency clock signals can provide a higher time subdivision capability, making the reconstructed path clock phase adjustment more precise, accurately compensating for the path delay differences between different chips, and allowing more chips to be tested simultaneously.

[0020] Specifically, the time offset of each chip under test is calculated based on the wiring length, chip setup time, and clock jitter of each chip under test. For example, when the test equipment and the chip under test are connected through a connector on the carrier board, the corresponding time offset is calculated based on the timing parameters of the chip under test i. , used to ensure that the timing of the signal reaching the chip under test i meets the requirements. Time offset It is necessary to comprehensively consider various parameters such as PCB design, chip setup time, clock jitter, etc. The calculation formula is as follows:

[0021] in: : PCB trace length of the signal from the connector to the chip under test i; : The shortest trace length among all chips is used as a reference benchmark to unify the starting point of timing calculation; : Dielectric constant of PCB board, (speed of light); : Chip parallel data setup time, ensuring that the data is stable before the clock edge; : Standard deviation of clock jitter, Provides timing margin for jitter effects; : Calculate the propagation delay difference caused by the difference in trace length and compensate for the inconsistency of signal arrival time.

[0022] It should be noted that, in a chip test system, the above-mentioned timing margin refers to the maximum timing deviation range allowed during signal transmission or processing when the system is operating normally.

[0023] In some examples, in order to adjust the phase of the intermediate clock according to the timing parameters corresponding to each chip under test and generate a phase-corrected accompanying clock, the time offset corresponding to the timing parameters of each chip under test can be first converted into an integer multiple of the period of the high-frequency clock signal according to the timing parameters of each chip under test, and then the phase of the intermediate clock can be adjusted according to the integer multiple of the period of the high-frequency clock signal to generate a phase-corrected accompanying clock.

[0024] Specifically, the time offset Quantized into high-frequency clock cycles The integer multiple of is calculated as follows:

[0025] Each clock cycle can be considered as the smallest scale of time measurement. By counting the time offset as the number of high-frequency clock cycles, the low-speed clock phase can be adjusted in steps, with the step size being the high-frequency clock cycle. For example, a programmable delay unit can be driven by a high-frequency clock to insert a delay unit as needed. The purpose of phase adjustment is achieved by delaying a high-frequency clock cycle.

[0026] High-frequency clock signals offer greater flexibility in frequency division control when generating lower-frequency target clocks. Regarding phase adjustment, high-frequency clocks provide fine time resolution, enabling precise time offset adjustment. For example, when using a 10GHz high-frequency clock, the system achieves a time adjustment accuracy of 0.1 nanoseconds, a tenfold improvement compared to the 1 nanosecond accuracy of a 1GHz clock. This fine resolution enables highly accurate phase correction and timing compensation. Leveraging the fine time resolution of high-frequency clocks, the previously continuous time offset is converted into discrete integer multiples of the high-frequency clock cycle, simplifying the implementation complexity of timing compensation. By constraining the time offset to within integer multiples of the high-frequency clock cycle, the system can utilize standard digital circuit technology to perform phase adjustment. This digital processing significantly improves system reliability and repeatability. Integer multiple quantization ensures deterministic timing compensation. Because each compensation step corresponds to an integer number of high-frequency clock cycles, the residual error between the compensated clock phase and the ideal value is strictly limited to within a single high-frequency clock cycle. From the perspective of test accuracy, the quantization scheme can achieve the optimal balance between compensation accuracy and system complexity by reasonably selecting a high-frequency clock frequency. Selecting an appropriate high-frequency clock frequency can meet the accuracy requirements of most test scenarios while maintaining reasonable power consumption and area overhead.

[0027] When the input slave clock is stable, in some implementations, the start and stop of intermediate clock generation can be controlled based on the state of the input slave clock. For example, when a valid input slave clock signal is detected, intermediate clock generation is initiated, further controlling the real-time generation of a phase-corrected slave clock to update the slave clock in the test stimulus signal for testing the chip under test. Conversely, when the input slave clock is detected to be terminated, intermediate clock generation is also stopped, thereby stopping the update of the slave clock in the test stimulus signal and interrupting the transmission of the test stimulus signal to the chip under test. However, the test stimulus signal may experience interruptions lasting several clock cycles, and the input slave clock may also experience interruptions for several clock cycles. If the generation of the intermediate clock is synchronized with the interruption of the input slave clock, that is, if the generation of the intermediate clock is stopped when the input slave clock is interrupted, this may cause a sudden phase jump in the high-frequency clock signal, resulting in metastable perturbations on the edges of the intermediate clock. To avoid this problem, in some examples, the test stimulus signal is received by an input / output module, and a control signal is output based on the data state of the input / output module to control the start and stop of intermediate clock generation. The parallel data received by the I / O module is transmitted continuously. During the test, the I / O module data will not enter a "null" state. Therefore, the start and stop of intermediate clock generation can be determined based on whether the parallel data in the I / O module is "null." This approach effectively reduces clock jitter caused by brief interruptions in the input slave clock signal and ensures that the phase-corrected slave clock remains stable throughout the test.

[0028] In some examples, the input-output module may be an asynchronous first-in-first-out queue.

[0029] The asynchronous first-in-first-out (FIFO) queue completes the clock domain conversion. The input end receives the input clock signal and input parallel data from the test equipment, and the output end outputs the parallel data according to the rhythm of the phase-corrected path clock to ensure uninterrupted data flow. The buffer depth of the asynchronous FIFO does not need to be designed too large, as long as it meets the basic requirements of clock domain synchronization. Generally, the depth can be set to 8 or less for normal operation, and it can also be customized according to needs. There is no restriction in this embodiment. The specific depth can be flexibly adjusted according to the system clock frequency and data transmission speed, which ensures correct data transmission without wasting chip resources.

[0030] In some examples, for Figure 1 The technical solution shown can also perform waveform adjustment on the phase-corrected accompanying clock based on the input accompanying clock before replacing the input accompanying clock based on the phase-corrected accompanying clock to update the test excitation signal, so as to replace the input accompanying clock based on the waveform-adjusted phase-corrected accompanying clock to update the test excitation signal.

[0031] After completing frequency and phase adjustment of the high-frequency clock, a phase-corrected slave clock that meets the test requirements of the chip under test can be stably output. Because the generation of the phase-corrected slave clock relies on the enable control of the intermediate clock, it can maintain normal output even if the input slave clock experiences a brief interruption, ensuring continuity of the test process. However, to maintain synchronization with the input slave clock, the phase-corrected slave clock must be adjusted based on the validity of the input slave clock after the phase-corrected slave clock. This ensures that the clock signal ultimately transmitted to the chip under test matches the waveform of the input slave clock, minimizing the impact of the reconstructed clock on chip test results. The validity of the input slave clock refers to determining whether the input slave clock data is normal based on preset conditions, such as physical layer signal quality and protocol conformance. If normal, the clock is considered valid; if it does not meet the criteria, the clock is considered invalid. If the input slave clock experiences a brief interruption, the phase-corrected slave clock is controlled to synchronize with the input slave clock data, introducing the same invalid period. This ensures that the clock waveform ultimately transmitted to the chip under test matches the waveform of the input slave clock.

[0032] In a possible implementation, waveform adjustment is performed on the phase correction associated clock based on the input associated clock, including: According to the validity of the input accompanying clock, the phase correction accompanying clock is enabled and controlled to obtain the phase correction accompanying clock after waveform adjustment, so that the waveform of the phase correction accompanying clock after waveform adjustment is consistent with the waveform of the input accompanying clock.

[0033] Adjustment of the phase-corrected accompanying clock can be achieved by enabling the phase-corrected accompanying clock to the chip under test (CUT). Furthermore, this can be achieved through a gating module. When the input accompanying clock data is judged to be valid, the gating switch opens, allowing the phase-corrected accompanying clock to be transmitted to the chip under test. When the input accompanying clock data is judged to be invalid, the gating switch closes, blocking the phase-corrected accompanying clock from being transmitted to the chip under test.

[0034] In some examples, for the above technical solution, for the input parallel data in the test excitation signal, the updated test excitation signal is used to test the chip under test, and it can also include controlling the output of the input parallel data based on the phase-corrected accompanying clock, obtaining parallel data synchronized with the phase-corrected accompanying clock timing, replacing the input parallel data to update the test excitation signal, and using the updated test excitation signal to test each test chip.

[0035] If the parallel data in the test stimulus signal is not synchronized with the phase-corrected accompanying clock, data sampling errors may occur, thereby affecting the accuracy of the test results. By phase-correcting the accompanying clock to control the input parallel data output, the accompanying clock and parallel data in the updated test stimulus signal are synchronized, so that the test stimulus signal after synchronously updating the parallel data can dynamically adapt to the differences in timing parameters of different test chips. By correcting the clock phase in real time and synchronously outputting parallel data, each test chip can be ensured to receive stimulus under optimal timing conditions, thereby improving test efficiency while ensuring test reliability when testing multiple chips simultaneously in high-speed data rate scenarios.

[0036] Specifically, based on the phase-corrected accompanying clock to control the output of the input parallel data, a read pulse signal may be first generated according to the phase-corrected accompanying clock, and then the output of the input parallel data may be controlled by the read pulse signal.

[0037] In the data output control process based on a phase-corrected accompanying clock, generating a read pulse signal and using it to manage the output of parallel data is a key step in achieving precise timing synchronization. First, the input parallel data can be temporarily stored in an input / output module, which provides the function of receiving data from the test equipment and outputting data according to control. Then, the phase-corrected accompanying clock is used to generate a read pulse signal through, for example, a pulse generator. Subsequently, the read pulse signal acts as a control signal on the input / output module, triggering the stable output of the input parallel data. During the effective period of the read pulse, the input data is securely captured and transmitted to the chip under test, ensuring that it is aligned with the edge of the reconstructed clock. This mechanism effectively eliminates the timing uncertainty introduced by clock domain switching, allowing the output data to be correctly sampled at the receiving end. Through precise control of the read pulse signal, the system can maintain a low bit error rate in high-speed data transmission scenarios while adapting to the clock jitter and offset characteristics of different chips under test, thereby improving the reliability and consistency of the test system.

[0038] The present invention realizes independent timing compensation for each chip through dynamic phase adjustment and multi-channel timing synchronization algorithm, breaks through the limitations of traditional single timing parameters, and achieves flexible balance between test rate and test quantity. Without affecting the original test process, it maintains the integrity of the expected test vector, realizes seamless conversion of clock domains, can adapt to the timing characteristics of different chips, and can efficiently detect multiple chips with different timing requirements at the same time, thereby improving reliability and test efficiency and reducing test costs. High-frequency signals have shorter clock cycles, such as a 1GHz clock cycle of 1ns, and can adjust the phase and timing of signals with extremely high precision. Compared with traditional low-frequency signals, such as a 20MHz clock cycle of 50ns, the adjustment accuracy is far less than 1ns. The present invention can fine-tune the routing delay differences of each chip under test to ensure that the setup time and hold time requirements are accurately met when the signal arrives, thereby improving test efficiency and timing adjustment accuracy, thereby improving the reliability of multiple chips during parallel high-speed testing, and further reducing chip testing costs and increasing chip production capacity. From a deployment perspective, this approach eliminates the need to rely on complex test equipment adjustment mechanisms, retains the original test equipment, and eliminates the need to modify the existing test system design process and file formats, resulting in excellent compatibility. This approach improves system versatility and deployment efficiency, making it suitable for a wide range of test scenarios. Furthermore, since this proposal does not require modifications to the existing test equipment and test stimulus, it seamlessly integrates with existing test equipment and stimulus files, enabling timing optimization without replacing hardware or rewriting test programs, significantly reducing deployment costs.

[0039] Based on the same concept as the above technical solution, the present disclosure also provides a chip testing device, such as Figure 2 The schematic diagram of the structure of a chip testing device shown in FIG. 1 includes a frequency adjustment part, a phase adjustment part, and an update part, wherein: The frequency adjustment part is used to generate an intermediate clock with the same frequency as the input accompanying clock in the test stimulus signal through a high-frequency clock signal, wherein the frequency of the high-frequency clock signal is greater than the input accompanying clock; The phase adjustment part is used to adjust the phase of the intermediate clock according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock; The updating part is used to replace the input accompanying clock based on the phase-corrected accompanying clock to update the test stimulus signal, so as to test each chip under test using the updated test stimulus signal.

[0040] It should be noted that Figure 2 The test excitation signal 1 to the test excitation signal N are test excitation signals output by the test equipment for the chips under test 1 to the chips under test N respectively, and the timing parameter 1 to the timing parameter N are timing parameters for the chips under test 1 to the chips under test N respectively.

[0041] In some examples, the phase adjustment portion is further configured to: According to the timing parameters of each chip under test, converting the time offset corresponding to the timing parameters of each chip under test into an integer multiple of the period of the high-frequency clock signal; The phase of the intermediate clock is adjusted according to an integer multiple of the period of the high-frequency clock signal to generate a phase-corrected associated clock.

[0042] In some examples, the device also includes a waveform adjustment part, which is configured to perform waveform adjustment on the phase correction accompanying clock based on the input accompanying clock to replace the input accompanying clock based on the waveform-adjusted phase correction accompanying clock to update the test stimulus signal.

[0043] In some examples, the waveform adjustment portion is further configured to: According to the validity of the input accompanying clock, the phase correction accompanying clock is enabled and controlled to obtain the phase correction accompanying clock after waveform adjustment, so that the waveform of the phase correction accompanying clock after waveform adjustment is consistent with the waveform of the input accompanying clock.

[0044] In some examples, the update part also includes a data update module, which is configured to control the output of input parallel data in the test excitation signal based on the phase-corrected accompanying clock, obtain parallel data synchronized with the phase-corrected accompanying clock timing, replace the input parallel data to update the test excitation signal, and use the updated test excitation signal to test each test chip.

[0045] In some examples, the data update module is further configured to: Generate a read pulse signal according to the phase-corrected accompanying clock; The input parallel data output is controlled by the read pulse signal.

[0046] In some examples, the apparatus further includes an input-output module and a clock enable module, wherein: The input-output module is configured to receive an input path clock and input parallel data in a test stimulus signal; The clock enable module is configured to output a control signal according to the data state in the input / output module to control the operation of the frequency adjustment part.

[0047] It should be noted that, when actually deployed, each functional unit in the above device may be a centralized processing unit deployed for each chip under test, or a processing unit may be set for each chip under test, which is not limited in the present disclosure. Figure 3The figure shows a connection diagram of an embodiment of a chip testing device. In this embodiment, each chip under test is equipped with an asynchronous FIFO as its input and output component and an associated clock generator as its waveform adjustment component. The frequency adjuster, phase adjuster, and pulse generator, which serve as the data update module, form a centralized clock adjustment module. This module generates a phase-corrected clock signal for each chip under test and a control signal for parallel data output based on the high-frequency signal and timing parameters.

[0048] Specifically, for each chip under test, the asynchronous FIFO can be internally implemented to include a first asynchronous FIFO queue for receiving a test stimulus signal and a second asynchronous FIFO queue for receiving response data from the chip under test. The input end of the first asynchronous FIFO queue is connected to the test equipment to receive the input parallel data and input associated clock sent by the test equipment to the chip under test. The input end of the second asynchronous FIFO queue is connected to the chip under test to receive the response data from the chip under test. One output end of the first asynchronous FIFO queue is connected to the clock enable control module to send the input associated clock signal and the status of the first asynchronous FIFO queue to the clock adjustment module. The input end of the first asynchronous FIFO queue is connected to the pulse generator to receive a read pulse signal for reading parallel data and outputting it to the chip under test. Another output end of the first asynchronous FIFO queue is connected to the chip under test to send adjusted data to chips under test 1, 2, and N. The third output end of the first asynchronous FIFO queue is connected to the associated clock generator to send the input associated clock signal status to the associated clock generator, so that the associated clock generator adjusts and reconstructs the waveform of the associated clock based on the waveform of the input associated clock signal. An input end of the second asynchronous FIFO queue inside the asynchronous FIFO receives response data of the chip under test, and an output end is used to send the response data to the test equipment.

[0049] The frequency adjuster has its input connected to the clock enable control and high-frequency signal, and its output connected to the phase adjuster. It generates an intermediate clock signal with the same frequency as the input accompanying clock output by the test equipment based on the input high-frequency clock (such as 500MHz or 1GHz).

[0050] The phase adjuster, whose input end is connected to the frequency adjuster and the high-frequency clock signal, uses the high-frequency clock to adjust the phase of the intermediate clock output by the frequency adjuster according to the pre-configured timing parameters to meet the timing requirements of the signal to each chip under test and generate a phase-corrected accompanying clock.

[0051] Clock enable control, with the input connected to the asynchronous FIFO and the output connected to the frequency adjuster. Monitors the asynchronous FIFO status and dynamically controls the generation of the intermediate clock.

[0052] The pulse generator has an input end connected to the phase adjuster and an output end connected to the asynchronous FIFO, and controls the reading and writing of parallel data of the asynchronous FIFO according to the phase adjustment clock.

[0053] The accompanying clock generator has its input connected to the phase adjuster and asynchronous FIFO, and its output connected to the chip under test. It is used to control the transmission of the phase-corrected accompanying clock output by the phase adjuster to the chip under test according to the state of the input accompanying clock, ensuring that the accompanying clock waveform output to the chip under test is consistent with the original input accompanying clock signal.

[0054] During operation, the asynchronous FIFO receives the input parallel data and input accompanying clock output by the test equipment. The input of the asynchronous FIFO is the test equipment clock domain provided by the test equipment, for example, 20MHz. The output of the asynchronous FIFO is the reconstructed clock domain, generated by the clock adjustment module, and has a frequency consistent with the input accompanying clock, for example, also 20MHz. During actual testing, input test data is transmitted continuously. The main function of the asynchronous FIFO is to smooth the transition between clock domains, rather than processing bursts of data. Therefore, when data is written to the asynchronous FIFO, the output immediately transmits the waveform to the chip under test, ensuring no data accumulation or delay.

[0055] Frequency adjuster based on high frequency clock , such as frequency , generate synchronous clock through programmable frequency division , whose frequency is consistent with the input clock of the test equipment, for example, the frequency division coefficient , generating an intermediate clock signal of the same 20MHz.

[0056] The phase adjuster adjusts the phase of the intermediate clock signal according to preset timing parameters to compensate for time deviations caused by differences in line lengths or different chip timing requirements, ensuring that the signal meets the requirements when it reaches each chip.

[0057] Assumptions ,but: Time offset

[0058] like ,but , .

[0059] The associated clock generator ensures that the output test associated clock waveform is consistent with the input associated clock based on the state of the associated clock. The clock enable controller monitors the asynchronous FIFO status and dynamically controls the operation of the clock adjustment module. Because data is continuously transmitted, the asynchronous FIFO never becomes empty, and the clock enable signal remains active. The pulse generator generates read pulses based on the phase-corrected associated clock, controlling the asynchronous FIFO to output parallel data to the chip under test in real time according to timing requirements. The response signal from the chip under test is sent to the test equipment via the asynchronous FIFO.

[0060] It should be noted that the device embodiments described above are merely exemplary, in which the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment of the present disclosure. It can be deployed as a functional unit part for processing multiple chips under test, or it can be deployed as an independent functional unit part for each chip under test for processing. In addition, in the drawings of the device embodiments provided by the present disclosure, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines. It should be noted that the technical solutions recorded in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0061] In addition, it should be appreciated by those skilled in the art that in one or more of the above examples, the functions described in this disclosure can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

[0062] It should be noted that the technical solutions described in this disclosure can be combined arbitrarily without conflict.

[0063] The above are only specific embodiments of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A chip testing method, characterized in that: The method comprises: Generate an intermediate clock with the same frequency as the input accompanying clock in the test stimulus signal through a high-frequency clock signal, wherein the frequency of the high-frequency clock signal is greater than the input accompanying clock; Adjusting the phase of the intermediate clock according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock; The input associated clock is replaced based on the phase-corrected associated clock to update the test stimulus signal, so as to test each chip under test using the updated test stimulus signal.

2. The method according to claim 1, characterized in that The step of adjusting the phase of the intermediate clock according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock includes: According to the timing parameters of each chip under test, converting the time offset corresponding to the timing parameters of each chip under test into an integer multiple of the period of the high-frequency clock signal; The phase of the intermediate clock is adjusted according to an integer multiple of the period of the high-frequency clock signal to generate a phase-corrected accompanying clock.

3. The method according to claim 1, characterized in that Before replacing the input associated clock based on the phase-corrected associated clock to update the test stimulus signal, the method further includes: The waveform of the phase-corrected associated clock is adjusted based on the input associated clock, so as to replace the input associated clock with the waveform-adjusted phase-corrected associated clock to update the test stimulus signal.

4. The method according to claim 3, characterized in that The waveform adjustment of the phase correction associated clock based on the input associated clock includes: According to the validity of the input accompanying clock, the phase correction accompanying clock is enabled and controlled to obtain a waveform-adjusted phase correction accompanying clock, so that the waveform of the waveform-adjusted phase correction accompanying clock is consistent with the waveform of the input accompanying clock.

5. The method according to any one of claims 1 to 3, characterized in that The test stimulus signal includes input parallel data; The testing of the chip under test using the updated test stimulus signal includes: Based on the phase-corrected accompanying clock, the output of the input parallel data is controlled to obtain parallel data synchronized with the phase-corrected accompanying clock, and the input parallel data is replaced to update the test stimulus signal, so as to test each test chip using the updated test stimulus signal.

6. The method according to claim 5, characterized in that The controlling the output of the input parallel data based on the phase-corrected accompanying clock comprises: Generate a read pulse signal according to the phase-corrected accompanying clock; The input parallel data output is controlled by the read pulse signal.

7. A chip testing device, characterized in that: The device includes a frequency adjustment part, a phase adjustment part, and an update part, wherein: The frequency adjustment part is used to generate an intermediate clock with the same frequency as the input accompanying clock in the test stimulus signal through a high-frequency clock signal, wherein the frequency of the high-frequency clock signal is greater than the input accompanying clock; The phase adjustment part is used to adjust the phase of the intermediate clock according to the timing parameters of each chip under test to generate a phase-corrected accompanying clock; The updating part is used to replace the input associated clock based on the phase-corrected associated clock to update the test stimulus signal, so as to test each chip under test using the updated test stimulus signal.

8. The device according to claim 7, characterized in that The phase adjustment part is further configured to: According to the timing parameters of each chip under test, converting the time offset corresponding to the timing parameters of each chip under test into an integer multiple of the period of the high-frequency clock signal; The phase of the intermediate clock is adjusted according to an integer multiple of the period of the high-frequency clock signal to generate a phase-corrected accompanying clock.

9. The device according to claim 7, characterized in that Before the updating part, the device also includes a waveform adjustment part, which is configured to perform waveform adjustment on the phase correction accompanying clock based on the input accompanying clock, so as to replace the input accompanying clock based on the waveform-adjusted phase correction accompanying clock to update the test stimulus signal.

10. The device according to claim 7, characterized in that The update part also includes a data update module, which is configured to control the output of the input parallel data in the test excitation signal based on the phase correction clock, obtain parallel data synchronized with the phase correction clock timing, replace the input parallel data to update the test excitation signal, and use the updated test excitation signal to test each test chip.

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