Automatic PCB splicing identification method

Abstract

The invention relates to the technical field of PCB jointed board matching, in particular to an automatic PCB jointed board identification method, which comprises the following steps: acquiring a layer file containing PCB frame information, the frame information comprising coordinates and lengths of line segments forming a frame; taking the origin of coordinates as a starting point, searching a shortest closed path based on the frame information, and forming a first daughter board frame by an area enclosed by the closed path; according to the shape of the frame of the first daughter board, identifying the frames of all the daughter boards in the substrate through a graph matching algorithm; generating position information and rotation angle information of each daughter board relative to the first daughter board based on a matching result; according to the invention, frame layer data is directly processed, manual intervention is eliminated, and matching failure caused by wrong pad selection is avoided; the rotation angle is automatically calculated, any-angle board splicing is supported, and parameters do not need to be predefined; based on frame template matching of geometric features, the calculation amount is reduced, and the trial and error process is avoided; the physical frame structure is preferentially identified, and the problem of matching fault tolerance when the bonding pad is missing or deformed is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of PCB panel matching, and in particular to a PCB automatic panel recognition method. Background Art

[0002] The existing technology calculates the panelization by pre-selecting the pads as markers, and determines whether it is a panelization by including the pads as markers in all the pad information, and finally obtains all matching panels, such as CN110245412A and CN113239657A. However, for the method that requires manual specification of the pads as markers, if the selected pads are not sufficiently iconic, then the panelization may not be calculated, or the correct panelization may not be matched if the pad information is insufficient.

[0003] In view of this, we propose a PCB automatic panel recognition method to solve the existing problem. Summary of the Invention

[0004] The purpose of the present invention is to provide a PCB automatic panel recognition method to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solution: a PCB automatic panel recognition method, comprising: Get the layer file containing the PCB border information, including the coordinates and lengths of the line segments that make up the border; Starting from the coordinate origin, the shortest closed path is searched based on the border information, and the area enclosed by the closed path forms the border of the first sub-board; According to the shape of the first sub-board frame, identifying the frames of all sub-boards in the substrate by a graphic matching algorithm; The position information and rotation angle information of each sub-board relative to the first sub-board are generated based on the matching result.

[0006] Furthermore, searching for the shortest closed path includes traversing paths starting from the coordinate origin and screening a closed path with the shortest length and a coincident start point and end point.

[0007] Furthermore, the graphic matching algorithm includes: extracting geometric features of the first sub-board border; matching areas with the same geometric features in the substrate border data; performing affine transformation on the matching area and calculating its translation and rotation angle relative to the first sub-board.

[0008] Furthermore, the layer file containing the PCB border information is a GKO layer.

[0009] Furthermore, after generating the position information of each sub-board, the method further includes: extracting the pad set corresponding to the sub-board from the steel mesh pad data file according to the coordinates of the sub-board frame.

[0010] Furthermore, the screening of closed paths includes: modeling line segment endpoints as graph vertices, modeling line segments as weighted edges, and constructing an adjacency matrix; performing a hierarchical path search starting from the coordinate origin vertex; and identifying all sub-board layouts through template matching based on the bounding box.

[0011] Furthermore, the hierarchical path search includes a first-level search and a second-level search. The first-level search uses the Dijkstra algorithm to generate a set of candidate closed loops. The second-level search applies the A* heuristic algorithm to screen the closed loop with the smallest total length from the candidate set, and uses the smallest closed loop as the first sub-board border.

[0012] Furthermore, the specific operations of the graphics matching algorithm include: obtaining the vertex sequence of the first sub-plate border, performing Delaunay triangulation to generate a feature triangle set, and calculating a geometric fingerprint for each feature triangle; in the substrate border data, retrieving a candidate triangle set that matches the geometric fingerprint through a local sensitive hash bucket, calculating a direction chain code for the candidate area, and performing a differential operation with the reference chain code. When the chain code differential value is less than a threshold, it is determined to be a matching sub-plate; selecting the three non-collinear feature points with the highest matching degree, solving the affine transformation matrix, and extracting the translation and rotation angle from the matrix parameters.

[0013] Furthermore, the specific operations of extracting the pad set include: obtaining the sub-board border coordinate set, generating a dynamic buffer boundary and traversing the steel mesh pad data file.

[0014] Furthermore, the dynamic buffer boundary includes an inward-shrinking buffer layer and an outward-expanding buffer layer.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention directly processes border layer data, eliminating manual intervention and avoiding matching failures caused by incorrect pad selection; automatically calculates the rotation angle, supports paneling at any angle without the need for predefined parameters; matches border templates based on geometric features, reduces the amount of calculation and avoids the trial-and-error process; and prioritizes identifying the physical border structure to solve matching fault tolerance issues when pads are missing or deformed. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 The figure is a schematic diagram of the workflow of a PCB automatic panel recognition method of the present invention. DETAILED DESCRIPTION

[0017] The technical solution of the present invention is further described below with reference to the accompanying drawings and specific embodiments. Example 1

[0018] like Figure 1 As shown, a PCB automatic panel recognition method is characterized by comprising: Get the layer file containing the PCB border information, which includes the coordinates and lengths of the line segments that make up the border. The layer file containing the PCB border information is a GKO layer. Starting from the coordinate origin, searching for the shortest closed path based on the border information, the area enclosed by the closed path forming the first sub-board border; wherein searching for the shortest closed path includes: traversing the paths starting from the coordinate origin and selecting the closed path with the shortest length and the same starting point and end point; Based on the shape of the first sub-board border, the borders of all sub-boards in the substrate are identified using a pattern matching algorithm; wherein the pattern matching algorithm includes: extracting geometric features of the first sub-board border; matching regions with the same geometric features in the substrate border data; performing an affine transformation on the matching regions to calculate their translation and rotation angle relative to the first sub-board; Based on the matching results, the position information and rotation angle information of each sub-board relative to the first sub-board are generated; after the position information of each sub-board is generated, it also includes: according to the coordinates of the sub-board border, extracting the pad set of the corresponding sub-board from the steel mesh pad data file.

[0019] The working principle of a PCB automatic panel recognition method based on the first embodiment is as follows: The screening of closed paths includes: modeling line segment endpoints as graph vertices, modeling line segments as weighted edges, and constructing an adjacency matrix; performing a hierarchical path search starting from the coordinate origin vertex; and identifying all sub-board layouts through template matching based on the bounding box.

[0020] The hierarchical path search includes the first-level search and the second-level search. The first-level search uses the Dijkstra algorithm to generate a set of candidate closed loops. The second-level search applies the A* heuristic algorithm to screen the closed loop with the smallest total length from the candidate set, and uses the smallest closed loop as the first sub-board border.

[0021] The cost function of the A* heuristic algorithm is: f(n)=g(n)+h(n), where g(n) is the actual path length from the starting point to the current vertex, and h(n) is the Euclidean distance from the current vertex to the origin multiplied by the weight coefficient α, 0.5≤α≤0.8.

[0022] Constructing the adjacency matrix includes: for any two vertices v i With v j , if there is a directly connected line segment, then the adjacency matrix element A ij = line segment length; otherwise A ij =∞; For obtuse vertex pairs with an angle greater than 170°, A is mandatory. ij =∞.

[0023] The first level of search includes dynamic pruning: when the current path length L current >2×L mincandidate Terminate the branch when Lmincandidate is the current shortest candidate closed loop length.

[0024] The screening of closed paths also includes closed loop verification: a vector cross product operation is performed on the screened minimum closed loop to verify whether it is a convex polygon; if there is a concave point, the loop is removed from the candidate set and the search is repeated.

[0025] The specific operations of the graphics matching algorithm include: obtaining the vertex sequence of the first sub-plate border, performing Delaunay triangulation to generate a set of feature triangles, and calculating the geometric fingerprint for each feature triangle; in the substrate border data, retrieving the candidate triangle set that matches the geometric fingerprint through the local sensitive hash bucket, calculating the direction chain code for the candidate area, and performing a differential operation with the reference chain code. When the chain code difference value is less than the threshold, it is determined to be a matching sub-plate; selecting the three non-collinear feature points with the highest matching degree, solving the affine transformation matrix, and extracting the translation and rotation angle from the matrix parameters.

[0026] The geometric fingerprint formula for calculating the i-th characteristic triangle is FP i =(r a ,r b ,cosθ c ), where r a With r b is the normalized side length ratio, r a =I min / I mid , r b =I mid / I max , I min is the length of the shortest side of the triangle, I max is the length of the longest side of the triangle, I mid is the length of the middle side of the triangle, cosθ c is the cosine of the maximum interior angle.

[0027] The solution formula for the affine transformation matrix is , where x and y are the horizontal and vertical coordinates before affine transformation, x' and y' are the horizontal and vertical coordinates after affine transformation, the translation amount is (c, f), and the rotation angle θ = arctan(d / a).

[0028] The generation of the direction chain code includes: converting the border vertex sequence into a vector edge set, calculating the direction angle for each edge, and quantizing the direction angle to 8 intervals to generate the chain code.

[0029] The calculation formula of chain code difference is: ,in, is the i-th value in the reference chain code, is the i-th value in the direction chain code. Both the reference chain code and the direction chain code have n values, and the threshold is 0.25.

[0030] Solving the affine transformation matrix involves selecting three sets of matching point pairs and constructing a set of equations: and , add the orthogonal constraint: a·d + b·e = 0; use the least squares method to solve the overdetermined system of equations.

[0031] The specific operations of the graphic matching algorithm also include deformation compensation: when 0.3<ΔCC<0.6, the thin plate spline interpolation algorithm is started: interpolation points are dynamically inserted on the candidate border, the matching degree is optimized through the bending energy function, and the transformation matrix parameters are updated.

[0032] The specific operations of extracting the pad set include: obtaining the sub-board border coordinate set, generating a dynamic buffer boundary and traversing the steel mesh pad data file.

[0033] The dynamic buffer boundary includes an inward-shrinking buffer layer and an outward-expanding buffer layer. Let the sub-board border coordinate set be B, and the inward-shrinking buffer layer B in =Offset(B,-k1·δ), where δ=0.1mm, k1∈[0.8,1.2] is the tension coefficient of the steel mesh; the external expansion buffer layer B out =Offset(B,+k2·δ), k2=2.5k1.

[0034] In the traversal of the steel mesh pad data file, if the pad center is located in B, it is directly added to the current daughter board pad set; if the pad center is located in B in Between and B, calculate the pad projection area ratio R=S proj / S pad , S proj is the pad projection area, S pad The area of ​​the pad itself. When R>0.7, it belongs to the sub-board. If the center of the pad is between B and B out If the number of sub-boards is greater than 0.85, cross-board arbitration is initiated: the sub-board with higher network connectivity is given priority, and the sub-board with the shape similarity of the pad at the corresponding position of the reference sub-board is secondly selected.

[0035] The network connectivity calculation includes: extracting the electrical network Net to which the pad belongs i , count the Net i The number of confirmed pads N connected Calculate the proportion of the network in the total number of pads on the entire board C i =N connected / |Net i |.

[0036] The calculation formula for shape similarity is Sim=ω1·IoU+ω2·e -|A-B| , where IoU is the intersection over union ratio of pad contours, A and B are Zernike moment eigenvectors, ω1=0.6, ω2=0.4.

[0037] The specific operation of extracting the pad set also includes process compensation: detecting whether the pad is located in the electroplating compensation area; if so, correcting the coordinates according to the compensation formula: x'=x+α·Δx, y'=y+β·Δy, where α and β are the substrate warpage coefficients, and Δx and Δy are the compensation vectors.

[0038] The compensation vector calculation includes: obtaining the historical offset data of the position and predicting the current compensation amount through Gaussian process regression.

[0039] The above specific embodiments are only several preferred embodiments of the present invention. Based on the technical solutions of the present invention and the relevant inspirations of the above embodiments, those skilled in the art can make various alternative improvements and combinations to the above specific embodiments.

Claims

1. A PCB automatic panel recognition method, characterized in that: include: Get the layer file containing the PCB border information, including the coordinates and lengths of the line segments that make up the border; Starting from the coordinate origin, the shortest closed path is searched based on the border information, and the area enclosed by the closed path forms the border of the first sub-board; According to the shape of the first sub-board frame, identifying the frames of all sub-boards in the substrate by a graphic matching algorithm; The position information and rotation angle information of each sub-board relative to the first sub-board are generated based on the matching result.

2. A PCB automatic panel recognition method according to claim 1, characterized in that: Searching for the shortest closed path includes: traversing the path starting from the coordinate origin, and screening the closed path with the shortest length and the coincidence of the starting point and the end point.

3. A PCB automatic panel recognition method according to claim 1, characterized in that: The graphic matching algorithm includes: extracting geometric features of the first sub-board frame; matching areas with the same geometric features in the substrate frame data; performing affine transformation on the matching area and calculating its translation and rotation angle relative to the first sub-board.

4. The method for automatically identifying PCB panels according to claim 1, wherein: The layer file containing PCB border information is the GKO layer.

5. A PCB automatic panel recognition method according to claim 1, characterized in that: After generating the position information of each sub-board, the method further includes: extracting the pad set corresponding to the sub-board from the steel mesh pad data file according to the coordinates of the sub-board frame.

6. A PCB automatic panel recognition method according to claim 2, characterized in that: The screening of closed paths includes: modeling line segment endpoints as graph vertices, modeling line segments as weighted edges, and constructing an adjacency matrix; performing a hierarchical path search starting from the coordinate origin vertex; and identifying all sub-board layouts through template matching based on the bounding box.

7. The method for automatically identifying PCB panels according to claim 6, wherein: The hierarchical path search includes the first-level search and the second-level search. The first-level search uses the Dijkstra algorithm to generate a set of candidate closed loops. The second-level search applies the A* heuristic algorithm to screen the closed loop with the smallest total length from the candidate set, and uses the smallest closed loop as the first sub-board border.

8. A PCB automatic panel recognition method according to claim 3, characterized in that: The specific operations of the graphics matching algorithm include: obtaining the vertex sequence of the first sub-plate border, performing Delaunay triangulation to generate a set of feature triangles, and calculating the geometric fingerprint for each feature triangle; in the substrate border data, retrieving the candidate triangle set that matches the geometric fingerprint through the local sensitive hash bucket, calculating the direction chain code for the candidate area, and performing a differential operation with the reference chain code. When the chain code difference value is less than the threshold, it is determined to be a matching sub-plate; selecting the three non-collinear feature points with the highest matching degree, solving the affine transformation matrix, and extracting the translation and rotation angle from the matrix parameters.

9. A PCB automatic panel recognition method according to claim 5, characterized in that: The specific operations of extracting the pad set include: obtaining the sub-board border coordinate set, generating a dynamic buffer boundary and traversing the steel mesh pad data file.

10. The PCB automatic panel recognition method according to claim 9, characterized in that: The dynamic buffer boundary includes an inward-shrinking buffer layer and an outward-expanding buffer layer.

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