Novel high-frequency three-phase H-bridge inversion parallel retopology and modulation method thereof

Abstract

The invention discloses a novel high-frequency three-phase H-bridge inversion parallel re-topology and a modulation method thereof, each phase in a three-phase inverter adopts one or more parallel single-phase full-bridge topologies, and each single-phase full-bridge topology comprises a direct-current bus part, an MOS module part, a differential-mode inductor part and a common-mode rejection part; the direct current bus part is a bus capacitor plate, the MOS module part is a full-bridge circuit, the differential mode inductor part comprises two differential mode inductors, and the common mode rejection part comprises a common mode inductor. A unipolar frequency doubling and carrier phase shift PWM (Pulse Width Modulation) mode is adopted, each full-bridge topology adopts unipolar frequency doubling modulation, modulation wave phase shift modulation is adopted between the full-bridge topologies, the phase difference is 360 / N, and N is the number of full-bridge circuits connected in parallel. According to the scheme, the purpose of increasing the output power, the switching frequency and the level number can be achieved.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronic converter control, and in particular to a novel high-frequency three-phase H-bridge parallel inverter topology and a modulation method thereof. Background Art

[0002] As practical applications place increasingly stringent demands on key performance parameters of inverter equipment, such as output voltage level, current ripple, harmonic content, volume, and weight, inverter equipment is required not only to increase output power, but also to increase its output switching frequency and number of levels, in order to achieve the goals of increasing voltage level, reducing output ripple and harmonic content, and reducing the volume of output filter inductors. Existing inverters generally use a three-phase half-bridge topology. There are two main ways to increase output power: one is to add parallel power switches per phase. The PWM modulation method ensures that the parallel power switches in each half-bridge are driven identically. This method requires high consistency in the power switch components and drivers, otherwise there is a risk of tube explosion. Furthermore, this control method can only increase power, not frequency or the number of power levels. Another method is to add parallel power switches per phase. The PWM modulation method uses bipolar carrier phase-shift modulation. Although the output equivalent switching frequency is N times the switching frequency after each phase is connected in parallel, where N is the number of parallel half-bridges per phase, and the number of power levels is N+1, this topology's output phase amplitude is half the bus voltage, resulting in low bus utilization. Furthermore, the N-fold switching frequency and N+1-fold power levels still fall short of expectations. Furthermore, despite bipolar modulation, the imbalance between the three phases still presents the problem of common-mode interference in the output. Summary of the Invention

[0003] The purpose of the present invention is to provide a novel high-frequency three-phase H-bridge parallel inverter topology and its modulation method, which can not only increase the output power of the inverter equipment, but also simultaneously improve the output switching frequency and the number of levels.

[0004] In order to achieve the above-mentioned purpose, the present invention is implemented through the following technical solutions.

[0005] A new high-frequency three-phase H-bridge parallel inverter topology, each phase of the three-phase inverter adopts one or more parallel single-phase full-bridge topologies, and the single-phase full-bridge topology includes a DC bus part, a MOS module part, a differential mode inductor part, and a common mode suppression part; The DC bus portion is a bus capacitor plate, the MOS module portion is a full-bridge circuit, the differential mode inductor portion includes two differential mode inductors, and the common mode suppression portion includes a common mode inductor; The upper and lower ends of the busbar capacitor plate are respectively connected to the upper and lower ends of the full-bridge circuit. The midpoint outputs of the two bridge arms of the full-bridge circuit are respectively connected to two differential-mode inductors, and the other ends of the two differential-mode inductors are connected to the common-mode inductor of the common-mode suppression part.

[0006] Furthermore, the busbar capacitor plate includes a film capacitor C1, an electrolytic capacitor C3, an electrolytic capacitor C4, and a common-mode inductor L1. The two windings of the common-mode inductor L1 are respectively connected in series with the positive and negative circuits of the DC bus. The film capacitor C1 is connected in parallel between the positive and negative poles of the DC bus on the output side of the common-mode inductor L1 winding. The electrolytic capacitor C3 and the electrolytic capacitor C4 are connected in parallel at both ends of C1 as the DC side bus of the full bridge. One end of the electrolytic capacitor C3 is connected to the upper tube side of the full bridge, and the other end is connected to the electrolytic capacitor C4. The other end of the electrolytic capacitor C4 is connected to the lower tube side of the full bridge.

[0007] Furthermore, the differential mode inductor part includes a differential mode inductor L3 and a differential mode inductor L4. One end of the differential mode inductor L3 is connected to the midpoint of the first bridge arm in the full-bridge circuit, and the other end is connected to the common mode inductor of the common mode suppression part; one end of the differential mode inductor L4 is connected to the midpoint of the second bridge arm in the full-bridge circuit, and the other end is connected to the common mode inductor of the common mode suppression part.

[0008] Furthermore, the common-mode suppression part includes a common-mode inductor L7, a film capacitor C7, and a film capacitor C8. The two windings of the common-mode inductor L7 are respectively connected to the phase line loop and the neutral line loop on the output side of the inverter. The film capacitor C7 and the film capacitor C8 are respectively connected in series between the output sides of the two windings of the common-mode inductor L7 and the N1 point. The N1 point is the connection point between the electrolytic capacitor C3 and the electrolytic capacitor C4.

[0009] Furthermore, the common-mode suppression part further includes a current-limiting resistor R1 and a current-limiting resistor R2. The current-limiting resistor R1 is connected in series between the film capacitor C7 and the point N1, and the current-limiting resistor R2 is connected in series between the film capacitor C8 and the point N1.

[0010] Furthermore, the MOS module part is a silicon carbide MOS module.

[0011] Furthermore, it also includes a total output filter inductor connected to the phase line output end of the common-mode suppression part. If there are enough parallel H-bridge modules connected in parallel, the filter inductor can be cancelled.

[0012] A novel high-frequency three-phase H-bridge parallel inverter re-connected topology modulation method is used to control the above-mentioned novel high-frequency three-phase H-bridge parallel inverter re-connected topology, adopting unipolar frequency doubling and carrier phase-shift PWM modulation methods. Each full-bridge topology adopts unipolar frequency doubling modulation, and each full-bridge topology adopts modulation wave phase-shift modulation. The phase difference is 360 / N, where N is the number of parallel full-bridge circuits.

[0013] Further, the method comprises the steps of: The DC source provides energy to the inverter through the bus capacitor plate; the bus capacitor plate includes a film capacitor C1, an electrolytic capacitor C3, an electrolytic capacitor C4, and a common-mode inductor L1. The DC source suppresses common-mode current through the common-mode inductor L1, and the film capacitor C1 provides a loop for high-frequency ripple.

[0014] The output equivalent switching frequency of each full-bridge topology is twice the switching frequency of the power MOS tube, and the number of levels is 3. The total output equivalent switching frequency of N parallel full-bridge topologies is 2N times the switching frequency of the power MOS tube, and the number of levels is 2N+1. The phase voltage amplitude is the bus voltage. Differential mode inductors are used as choke inductors to suppress circulating currents caused by carrier phase differences when multiple MOS modules are turned on at the same time. The common-mode current calculation formula of the common-mode rejection part is: Wherein, Udc is the bus voltage, L7 is the inductance of the common-mode inductor L7, L7 is the inductance of the common-mode inductor L7. One end of the common-mode inductor L7 is connected to the two differential-mode inductors, and the two windings at the other end are respectively connected to the phase line loop and the neutral line loop on the inverter output side. f is the frequency. The lower the bus voltage, the larger the common-mode inductance, and the higher the frequency, the smaller the common-mode current. The common-mode voltage calculation formula is: Among them, C8 is the capacitance value of the film capacitor C8 connected in series between the output side of the common-mode inductor winding and point N1. Point N1 is the connection point of electrolytic capacitor C3 and electrolytic capacitor C4. C8 provides a low-impedance loop for the common-mode current and clamps the external common-mode voltage. The smaller the common-mode current, the larger the capacitance, the smaller the external output common-mode voltage, and the smaller the common-mode interference to external equipment.

[0015] Furthermore, since the series circuit of the inductor and the capacitor is prone to resonance, a resistor is connected in series with the common-mode suppression circuit to suppress current resonance.

[0016] The advantages of the present invention are that after N full-bridges are connected in parallel and re-connected, the output switching frequency is 2N times the switching frequency, the number of levels is 2N+1, the phase voltage amplitude is the bus voltage, and the output frequency and phase voltage amplitude are both twice those of a three-phase half-bridge topology. If enough re-connected H-bridges are connected in parallel, the equivalent output switching frequency can reach the MHz level. This achieves the goal of increasing output power, switching frequency, and the number of levels.

[0017] This solution uses silicon carbide MOS modules, which have lower switching losses than IGBTs and can operate at frequencies of tens of kHz. The differential mode inductor can suppress the short-circuit condition between the two bridge arms caused by the phase difference of the modulation wave. In order to suppress common-mode interference, a common-mode suppression topology is added to each full-bridge output to reduce common-mode interference. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is the overall circuit diagram of the novel high-frequency three-phase H-bridge parallel inverter topology of the present invention; Figure 2This is a circuit diagram of the DC bus portion of Example 1 of the present invention; Figure 3 This is a topological diagram of the H-bridge parallel connection in Example 1 of the present invention; Figure 4 The V after the H-bridge parallel connection of embodiment 1 of the present invention is UN waveform; Figure 5 This is a common-mode suppression circuit diagram of Example 1 of the present invention; Figure 6 This is a total output common-mode inductor circuit diagram of Example 3 of the present invention. DETAILED DESCRIPTION

[0019] The technical solutions in the embodiments of the present invention will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present invention.

[0020] Example 1 Please refer to Figure 1 This embodiment provides a new high-frequency three-phase H-bridge inverter parallel heavy topology. Each phase of the three-phase inverter adopts one or more parallel single-phase full-bridge topologies. The single-phase full-bridge topology includes a DC bus part, a MOS module part, a differential mode inductor part, and a common mode suppression part.

[0021] The DC bus portion is a bus capacitor plate, the MOS module portion is a full-bridge circuit, the differential mode inductor portion includes two differential mode inductors, and the common mode suppression portion includes a common mode inductor.

[0022] This embodiment is described in detail by taking the U-phase two H-bridge parallel topology as an example. Figure 2 、 Figure 3 In the first H-bridge, the upper and lower ends of the busbar capacitor plate are respectively connected to the upper and lower ends of the full-bridge circuit. The busbar capacitor plate includes a film capacitor C1, an electrolytic capacitor C3, an electrolytic capacitor C4, and a common-mode inductor L1. The two windings of the common-mode inductor L1 are respectively connected in series with the positive and negative circuits of the DC busbar. The film capacitor C1 is connected in parallel between the positive and negative poles of the DC busbar on the output side of the common-mode inductor L1 winding. The electrolytic capacitors C3 and C4 are connected in parallel at both ends of C1 as the DC side busbar of the full bridge. One end of the electrolytic capacitor C3 is connected to the upper tube side of the full bridge, and the other end is connected to the electrolytic capacitor C4. The other end of the electrolytic capacitor C4 is connected to the lower tube side of the full bridge.

[0023] The full-bridge circuit is an H-bridge circuit composed of four silicon carbide MOS modules. Switches T1 and T2 form the first (left) arm of the bridge, and switches T3 and T4 form the second (right) arm. The midpoint output of the left arm is connected to differential-mode inductor L3, while the center output of the right arm is connected to differential-mode inductor L4. The other ends of differential-mode inductors L3 and L4 are connected to one end of each winding of common-mode inductor L7, which serves as the common-mode suppression component.

[0024] The common-mode suppression part includes common-mode inductor L7, film capacitor C7, film capacitor C8, current limiting resistor R1, and current limiting resistor R2. The two windings of common-mode inductor L7 are respectively connected to the phase line loop and neutral line loop on the output side of the inverter. Film capacitor C7 and film capacitor C8 are respectively connected in series between the output sides of the two windings of common-mode inductor L7 and point N1. Current limiting resistor R1 is connected in series between film capacitor C7 and point N1. Current limiting resistor R2 is connected in series between film capacitor C8 and point N1. Point N1 is the connection point of electrolytic capacitor C3 and electrolytic capacitor C4.

[0025] The structure of the second H-bridge is the same as that of the first H-bridge, so I will not go into details here. Figure 2 、 Figure 3 .

[0026] Example 2 This embodiment proposes a novel high-frequency three-phase H-bridge parallel inverter re-connected topology modulation method for controlling the above-mentioned novel high-frequency three-phase H-bridge parallel inverter re-connected topology, adopting unipolar frequency doubling and carrier phase-shift PWM modulation methods. Each full-bridge topology adopts unipolar frequency doubling modulation, and each full-bridge topology adopts modulation wave phase-shift modulation, with a phase difference of 360 / N, where N is the number of parallel full-bridge circuits.

[0027] Taking the parallel connection of two H-bridges in phase U as an example, the DC source provides energy to the inverter through the bus capacitor plate; L1 is a common-mode inductor that mainly suppresses common-mode current and reduces the common-mode interference problem caused by the DC source; C1 is a film capacitor that mainly provides a loop for high-frequency ripple; C3, C4, C5, and C6 are electrolytic capacitors that mainly provide energy for the main circuit.

[0028] Each full-bridge topology outputs an equivalent switching frequency of twice the switching frequency of the power MOS transistor, with three levels. The total output equivalent switching frequency of N parallel full-bridge topologies is 2N times the switching frequency of the power MOS transistor, with 2N+1 levels. The phase voltage amplitude is the bus voltage. In this embodiment, the inverter portion comprises two H-bridges connected in parallel, each employing a unipolar, multiplied-frequency PWM modulation scheme. H-bridge 1 outputs an equivalent switching frequency of twice the switching frequency of the power MOS transistor, with three levels, including ±1 and 0. H-bridge 2 outputs an equivalent switching frequency of twice the switching frequency of the power MOS transistor, with three levels, including ±1 and 0. Because the carrier phases of full-bridges 1 and 2 differ by 180°, the total output equivalent switching frequency of the U phase after H-bridges 1 and 2 are connected in parallel is four times that of the power MOS transistor, with five levels, including ±1, ±1 / 2, and 0. The phase voltage amplitude is the bus voltage.

[0029] Because the present invention uses unipolar frequency-doubled modulation, the first H-bridge upper transistor and the second H-bridge lower transistor modules are simultaneously conductive. Therefore, differential-mode inductors L3, L4, L5, and L6 are used as choke inductors to suppress circulating currents caused by carrier phase differences. Due to the use of unipolar frequency-doubled modulation, the current ripple on the inductor is twice the switching frequency of the power MOS tube, and the inductor voltage drop is ±Udc / 4 and 0V. Compared to bipolar modulation, under the same high-frequency circulating current, unipolar frequency-doubled modulation requires less inductance and a smaller inductance.

[0030] L7 is the common-mode inductor, C8 is the film capacitor, and R2 is the current-limiting resistor. Formula 1.1 gives the common-mode current calculation formula: (1.1) The formula shows that the lower the bus voltage, the greater the common-mode inductance, and the higher the frequency, the smaller the common-mode current. C2 primarily provides a low-impedance path for the common-mode current and clamps the external common-mode voltage.

[0031] Formula 1.2 gives the common-mode voltage calculation formula: (1.2) The formula shows that the smaller the common-mode current, the larger the capacitance, the smaller the external common-mode voltage output, and the smaller the common-mode interference to external devices. In summary, in order to reduce common-mode interference, it is necessary to reduce the bus voltage, increase the switching frequency, increase the common-mode inductance, and increase the capacitance. However, since the series circuit of inductance and capacitance is prone to resonance, it is necessary to add a series resistor in the common-mode suppression circuit to suppress current resonance.

[0032] Among them, C8 is the capacitance value of the film capacitor C8 connected in series between the output side of the common mode inductor winding and point N1, U dc is the bus voltage, L7 is the inductance of the common mode inductor, and f is the frequency.

[0033] The voltage V between the U phase line output and the neutral line N line UN Waveform Figure 4 shown.

[0034] Example 3 On the basis of the above circuit topology, you can also add the total output filter inductance connected to the phase line output end of the common mode suppression part. Please refer to Figure 6 Since the inductor current is large, the cost and weight of the whole machine account for a large proportion. In the above steps, V UN The ripple frequency is four times the switching frequency and is 5-level, so a smaller inductance for L9 can achieve better filtering. If enough H-bridge modules are connected in parallel and the frequency is fast enough, the filter inductor can even be eliminated, reducing cost and weight.

[0035] Finally, it should be noted that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A new high-frequency three-phase H-bridge parallel inverter topology, characterized by: Each phase of the three-phase inverter adopts one or more parallel single-phase full-bridge topologies, and the single-phase full-bridge topology includes a DC bus part, a MOS module part, a differential mode inductor part, and a common mode suppression part; The DC bus portion is a bus capacitor plate, the MOS module portion is a full-bridge circuit, the differential mode inductor portion includes two differential mode inductors, and the common mode suppression portion includes a common mode inductor; The upper and lower ends of the busbar capacitor plate are respectively connected to the upper and lower ends of the full-bridge circuit. The midpoint outputs of the two bridge arms of the full-bridge circuit are respectively connected to two differential-mode inductors, and the other ends of the two differential-mode inductors are connected to the common-mode inductor of the common-mode suppression part.

2. The novel high-frequency three-phase H-bridge parallel inverter topology according to claim 1 is characterized in that: The busbar capacitor plate includes a film capacitor C1, an electrolytic capacitor C3, an electrolytic capacitor C4, and a common-mode inductor L1. The two windings of the common-mode inductor L1 are respectively connected in series with the positive and negative circuits of the DC bus. The film capacitor C1 is connected in parallel between the positive and negative poles of the DC bus on the output side of the common-mode inductor L1 winding. The electrolytic capacitor C3 and the electrolytic capacitor C4 are connected in parallel at both ends of C1 as the DC side bus of the full bridge. One end of the electrolytic capacitor C3 is connected to the upper tube side of the full bridge, and the other end is connected to the electrolytic capacitor C4. The other end of the electrolytic capacitor C4 is connected to the lower tube side of the full bridge.

3. The novel high-frequency three-phase H-bridge parallel inverter topology according to claim 2 is characterized in that: The differential mode inductor part includes a differential mode inductor L3 and a differential mode inductor L4. One end of the differential mode inductor L3 is connected to the midpoint of the first bridge arm in the full-bridge circuit, and the other end is connected to the common mode inductor of the common mode suppression part; one end of the differential mode inductor L4 is connected to the midpoint of the second bridge arm in the full-bridge circuit, and the other end is connected to the common mode inductor of the common mode suppression part.

4. The novel high-frequency three-phase H-bridge parallel inverter topology according to claim 2 is characterized in that: The common-mode suppression part includes a common-mode inductor L7, a film capacitor C7, and a film capacitor C8. The two windings of the common-mode inductor L7 are respectively connected to the phase line loop and the neutral line loop on the output side of the inverter. The film capacitors C7 and C8 are respectively connected in series between the output sides of the two windings of the common-mode inductor L7 and point N1. Point N1 is the connection point between the electrolytic capacitor C3 and the electrolytic capacitor C4.

5. The novel high-frequency three-phase H-bridge parallel inverter topology according to claim 4 is characterized in that: The common-mode suppression part further includes a current-limiting resistor R1 and a current-limiting resistor R2. The current-limiting resistor R1 is connected in series between the thin-film capacitor C7 and the point N1. The current-limiting resistor R2 is connected in series between the thin-film capacitor C8 and the point N1.

6. The novel high-frequency three-phase H-bridge parallel inverter topology according to claim 1 is characterized in that: The MOS module part is a silicon carbide MOS module.

7. The novel high-frequency three-phase H-bridge parallel inverter topology according to claim 1 is characterized in that: It also includes the total output filter inductor connected to the phase line output end of the common mode suppression part.

8. A novel high-frequency three-phase H-bridge parallel inverter recharge topology modulation method for controlling the novel high-frequency three-phase H-bridge parallel inverter recharge topology according to any one of claims 1 to 7, characterized in that: Unipolar frequency doubling and carrier phase shift PWM modulation is adopted. Each full-bridge topology adopts unipolar frequency doubling modulation, and modulation wave phase shift modulation is adopted between each full-bridge topology. The phase difference is 360 / N, where N is the number of full-bridge circuits in parallel.

9. The novel high-frequency three-phase H-bridge parallel inverter topology modulation method according to claim 8 is characterized in that: Including steps: The DC source provides energy to the inverter through the bus capacitor plate; The output equivalent switching frequency of each full-bridge topology is twice the switching frequency of the power MOS tube, and the number of levels is 3. The total output equivalent switching frequency of N parallel full-bridge topologies is 2N times the switching frequency of the power MOS tube, and the number of levels is 2N+1. The phase voltage amplitude is the bus voltage. Differential mode inductors are used as choke inductors to suppress circulating currents caused by carrier phase differences when multiple MOS modules are turned on at the same time. The common-mode current calculation formula of the common-mode rejection part is: Where Udc is the bus voltage, L7 is the inductance of the common-mode inductor L7, one end of the common-mode inductor L7 is connected to the two differential-mode inductors, and the two windings at the other end are connected to the phase line loop and neutral line loop on the inverter output side respectively, and f is the frequency; The common-mode voltage calculation formula is: Among them, C8 is a film capacitor connected in series between the output side of the common-mode inductor winding and point N1, and point N1 is the connection point between the electrolytic capacitor C3 and the electrolytic capacitor C4.

10. The novel high-frequency three-phase H-bridge parallel inverter topology modulation method according to claim 9, characterized in that: The series resistor in the common mode rejection loop suppresses current resonance.

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