High-signal-to-noise-ratio and high-bandwidth Sigma-Delta analog-to-digital converter and implementation method thereof
By improving the structure and algorithm of the Sigma-Delta analog-to-digital converter and adopting a multi-bit quantizer and adaptive FIR filter, the quantization noise is reduced and the signal-to-noise ratio and bandwidth are improved. This solves the limitations of traditional analog-to-digital converters in high signal-to-noise ratio and high bandwidth, and achieves the effect of improving the signal-to-noise ratio and bandwidth without increasing hardware cost and power consumption.
Patent Information
- Application Number
- CN202510716103.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-05-30
- Publication Date
- 2025-09-19
AI Technical Summary
Traditional Sigma-Delta analog-to-digital converters (ADCs) struggle to achieve high bandwidth while simultaneously achieving a high signal-to-noise ratio (SNR). Furthermore, there are challenges in increasing both SNR and bandwidth without increasing hardware cost and power consumption.
The system adopts a multi-bit quantizer, loop filter, quantization error processing module, auxiliary analog-to-digital converter and adaptive FIR filter, and reduces quantization noise and improves signal-to-noise ratio by optimizing structure and algorithm design. It also controls hardware cost and power consumption by adaptively adjusting weight factors and reference voltage.
The low-order loop filter achieves improvements in signal-to-noise ratio and bandwidth, meeting the requirements of high-speed and high-precision signal processing while controlling hardware costs and power consumption, with good economic benefits and practicality.
Smart Images
Figure CN120675567A_ABST
Abstract
Description
Technical Field
[0001] The present invention provides a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and an implementation method thereof, belonging to the technical field of integrated circuit design. Background Art
[0002] In modern electronic systems, analog-to-digital converters (ADCs) are key components for converting analog signals to digital signals. Sigma-Delta analog-to-digital converters (SDMs) have been widely used in numerous fields due to their advantages, such as high resolution, low power consumption, and strong noise immunity. However, traditional Sigma-Delta ADCs have limitations in achieving both a high signal-to-noise ratio and a high bandwidth. With the increasing demands for signal processing accuracy and speed, how to further improve the SNR and bandwidth of Sigma-Delta ADCs to meet the growing application needs has become an urgent issue in this field.
[0003] Currently, methods for improving the signal-to-noise ratio (SNR) of Sigma-Delta analog-to-digital converters primarily include optimizing loop filter design to increase its order, increasing the oversampling rate, and improving the quantizer structure. However, these methods are primarily focused on the analog domain and, in practical applications, often struggle to achieve significant improvements in SNR and bandwidth without significantly increasing hardware cost and power consumption.
[0004] Therefore, in view of this, the existing structure is studied and improved, and a high signal-to-noise ratio and high bandwidth Sigma-Delta analog-to-digital converter and its implementation method are proposed to solve the above problems. Summary of the Invention
[0005] The object of the present invention is to provide a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and an implementation method thereof. By improving the existing Sigma-Delta analog-to-digital converter structure and algorithm, the quantization noise is effectively reduced so that a low-order loop filter can also achieve a high signal-to-noise ratio and bandwidth. At the same time, the hardware cost and power consumption are controlled to a certain extent to meet the requirements of high-speed and high-precision signal processing.
[0006] In order to solve the above problems, the present invention proposes a technical solution: a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and an implementation method thereof, characterized in that it includes a multi-bit quantizer, a loop filter, a quantization error processing module, an auxiliary analog-to-digital converter (ADC), an adaptive FIR filter, and a signal synthesis module. The multi-bit quantizer has a quantization accuracy of 4 bits or higher and is configured in a Sigma-Delta modulator (SDM) to quantize the output signal of the loop filter. The auxiliary analog-to-digital converter (ADC) has a quantization accuracy of 9 bits or higher, and its reference voltage Vrefp2, Vrefn2 is 1 / 2 of the reference voltage Vrefp1, Vrefn1 of the multi-bit quantizer. k The proportional relationship is (k is a positive integer), and the number of bits of the auxiliary ADC is reduced by k bits synchronously with the reduction of the reference voltage while keeping the quantization accuracy unchanged.
[0007] Furthermore, all poles of the quantization noise transfer function (NTF) derived by the loop filter are located at the origin of the z-domain, so that the NTF has the form of an N-order finite impulse response (FIR) filter, such as: Where N ≥ 1 and the coefficient {b} satisfies the stability condition of the Sigma-Delta analog-to-digital converter.
[0008] Furthermore, the quantization error processing module includes a subtractor for extracting a quantization error signal of the multi-bit quantizer and inputting the quantization error signal into an auxiliary analog-to-digital converter (ADC).
[0009] Furthermore, the input of the adaptive FIR filter is the output signal of the auxiliary ADC, the form of its transfer function is completely matched with the NTF derived by the loop filter, and the filter weight factor can be adaptively adjusted by the least mean square (LMS) algorithm to minimize the in-band noise power. The adaptive FIR filter iteratively updates the weight factor of the FIR filter by calculating the correlation of the input signal until the in-band noise power reaches a minimum value.
[0010] Furthermore, the signal synthesis module is used to add the output signal Y(z) of the Sigma-Delta modulator and the output signal of the adaptive FIR filter to generate a final analog-to-digital conversion output signal ADC_OUT(z).
[0011] Furthermore, the reference voltage Vrefp2, Vrefn2 of the auxiliary analog-to-digital converter (ADC) is 1 / 2, 1 / 4 or 1 / 8 of the multi-bit quantizer reference voltage Vrefp1, Vrefn1, and the number of bits of the corresponding auxiliary group analog-to-digital converter is reduced by 1 bit, 2 bits or 3 bits respectively, while the quantization accuracy remains unchanged.
[0012] Furthermore, the NTF of the loop filter is an N-order FIR filter, and its transfer function satisfies Make sure that all poles of the NTF are located at the z-domain origin.
[0013] Furthermore, during the convergence of the weight factors of the adaptive FIR filter, the input signals are the quantization noise of the Sigma-Delta modulator and the output signal of the auxiliary ADC, and the weight factors are iteratively adjusted through the LMS algorithm to minimize the in-band noise power.
[0014] Furthermore, the output signal of the signal synthesis module satisfies ADC_OUT(z)=Y(z)+NTF(z)·EQaux(z), where EQaux(z) is the quantization noise of the auxiliary ADC. Theoretically, when the FIR weight factor and the NTF coefficient are equal, ADC_OUT(z) has the lowest in-band quantization noise.
[0015] Furthermore, the quantization accuracy of the multi-bit quantizer is 4-5 bits, the quantization accuracy of the auxiliary ADC is 9-12 bits, and the input signal amplitude of the auxiliary ADC is very small, not exceeding 1 / 8 of its reference voltage range.
[0016] Furthermore, the quantization accuracy of the multi-bit quantizer is 4-5 bits, the quantization accuracy of the auxiliary ADC is 9-12 bits, and the input signal amplitude of the auxiliary ADC does not exceed 1 / 2 of its reference voltage range.
[0017] Due to the adoption of the above technical solution, the high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method of the present invention have the following beneficial effects:
[0018] 1. The present invention effectively reduces quantization noise and improves the signal-to-noise ratio of analog-to-digital conversion through the collaborative work of a multi-bit quantizer, a specially designed loop filter, a quantization error processing module, and an adaptive FIR filter, thereby meeting the needs of high-speed and high-precision signal processing.
[0019] 2. The reference voltage and quantization accuracy of the auxiliary ADC of the present invention can be adjusted according to actual needs. The adaptive FIR filter can dynamically adjust the weight factor according to the input out-of-band signal, so that the analog-to-digital converter of the present invention can adapt to the slight error of the loop filter transfer function caused by the chip manufacturing process.
[0020] 3. While achieving a high signal-to-noise ratio, the present invention controls hardware costs and power consumption to a certain extent through reasonable structural design and algorithm optimization, and has good economic benefits and practicality. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:
[0022] Figure 1 This is an NTF display diagram of a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method of the present invention.
[0023] Figure 2 This is an architecture diagram of an SDM analog-to-digital converter of the present invention, which includes a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and an implementation method thereof.
[0024] Figure 3 This is a linear model diagram of a high-precision SDM analog-to-digital converter with a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to the present invention.
[0025] Figure 4 This is a diagram of a second-order high-precision SDM analog-to-digital converter with a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method of the present invention.
[0026] Figure 5 This is a diagram of the signal-to-noise ratio simulation results of a second-order high-precision SDM analog-to-digital converter of the present invention, a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method.
[0027] Figure 6 This is a diagram of an adaptive FIR filter for a high signal-to-noise ratio, high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to the present invention.
[0028] Figure 7 The present invention provides a high signal-to-noise ratio, high-bandwidth Sigma-Delta analog-to-digital converter and an implementation method thereof) with a weighting factor LMS loop diagram. DETAILED DESCRIPTION
[0029] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. It is obvious that the embodiments described are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts are within the scope of protection of the present invention.
[0030] The present invention provides a high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and an implementation method thereof:
[0031] Example 1
[0032] In this embodiment, the quantization accuracy of the multi-bit quantizer is set to 5 bits, the quantization accuracy of the auxiliary ADC is set to 10 bits, and the reference voltages Vrefp2 and Vrefn2 of the auxiliary ADC are 1 / 2 of the reference voltages Vrefp1 and Vrefn1 of the multi-bit quantizer, that is, the quantization accuracy is reduced by 1 bit.
[0033] The noise transfer function (NTF) derived from the loop filter has the form of a second-order finite impulse response (FIR) filter:
[0034]
[0035] The subtractor in the quantization error processing module extracts the quantization error signal from the multi-bit quantizer and feeds it into the auxiliary ADC. The auxiliary ADC performs analog-to-digital conversion on the quantization error signal, and the output is fed into an adaptive FIR filter. The adaptive FIR filter's transfer function perfectly matches the loop filter's NTF. When an out-of-band signal is input, a least mean square (LMS) algorithm adaptively adjusts the weighting factors to minimize the in-band noise power.
[0036] Finally, the signal synthesis module adds the sigma-delta modulator's output signal, Y(z), to the adaptive FIR filter's output signal to generate the final analog-to-digital conversion output signal, ADC_OUT(z), satisfying the equation ADC_OUT(z) = Y(z) + NTF(z) · EQaux(z), where EQaux(z) is the auxiliary ADC's quantization noise. Theoretically, when the FIR weight factor and the NTF coefficient are equal, the in-band quantization noise of ADC_OUT(z) is minimized.
[0037] Example 2
[0038] In this embodiment, the quantization accuracy of the multi-bit quantizer is 5 bits, the quantization accuracy of the auxiliary ADC is 12 bits, and the reference voltages Vrefp2 and Vrefn2 of the auxiliary ADC are 1 / 4 of the reference voltages Vrefp1 and Vrefn1 of the multi-bit quantizer, and the quantization accuracy is reduced by 2 bits.
[0039] The loop filter is a third-order FIR filter in the form of:
[0040] Similarly, the quantization error processing module extracts the quantization error signal, converts it through the auxiliary ADC, and then feeds it into the adaptive FIR filter. The adaptive FIR filter uses the LMS algorithm to adjust the weighting factors to minimize the in-band noise power. The signal synthesis module completes signal addition to obtain the final analog-to-digital conversion output signal.
[0041] When a multi-bit quantizer is used, all the poles of the SDM quantization noise transfer function (NTF) can be placed at the origin, and the stability of the SDM can still be maintained. When a multi-bit quantizer is used, all the poles of the NTF can be placed at the origin, such as Figure 1 shown.
[0042] The general expression of NTF is shown in equation (1):
[0043]
[0044] Its transfer function conforms to an Nth-order finite impulse response (FIR) filter.
[0045] The transfer function of the loop filter (LOOPFILTER) is obtained by equation (2).
[0046]
[0047] The NTF satisfies Equation 1. The quantizer (QUANTISER) requires at least 4 bits. The quantization error is generated by a subtractor and input to another high-bit analog-to-digital converter (ADC), typically 9 to 12 bits. Because the error signal amplitude is small, the ADC's high linearity is easily achieved. The ADC's output signal is input to an Nth-order FIR filter. Its transfer function is shown in Equation (3).
[0048]
[0049] The output of the FIR is summed with the output of the SDM, SDM_OUT, to produce the final ADC output signal, ADC_OUT. When the FIR transfer function matches the NTF, the quantization noise of the SDMQUANTISER (4-5 bits) can be replaced by the quantization noise of the high-bit ADC (9-12 bits), achieving an extremely high signal-to-noise ratio.
[0050] The error signal of SDM is the quantization error Eq1 of the quantizer. The output signal G of the system can be expressed by equation (4):
[0051] G=(-E q1 +E q2 )·F+Y (4)
[0052] Where F is the FIR transfer function; Y is the output signal of SDM, which can be expressed as formula (5):
[0053] Y=STF·X+NTF·E q1 (5)
[0054] Where STF is the signal transfer function of SDM, and NTF is the quantization noise transfer function of SDM.
[0055] G=-E q1 ·F+E q2 ·F+STF·X+NTF·E q1 (6)
[0056] When F = NTF, that is, bN = kN, then equation (6) can be simplified to:
[0057] G=STF·X+NTF·E q2 (7)
[0058] The output of this system is equivalent to the quantization noise of the SDM being replaced by the quantization noise of the high-bit ADC, and then filtered through the NTF to achieve an extremely high signal-to-noise ratio. Since both F and NTF use FIR architectures, they can theoretically achieve perfect matching without the need for approximation.
[0059] The quantization noise transfer function NTF of this second-order SDM is:
[0060]
[0061] The quantizer is 5-bit, the quantization frequency is 32MHz, the data bandwidth is 1MHz, and the quantization error ADC is 10-bit. The simulation results show that the signal-to-noise ratio of the SDM itself is 73dB. When the FIR transfer function and NTF match, the final signal-to-noise ratio of the ADC output signal reaches 114dB, as shown in Figure 2. Figure 5 shown.
[0062] Generally speaking, the reference voltages Vrefp1 and Vrefn1 of the SDM quantizer should be the same as the reference voltages Vrefp2 and Vrefn2 of the ADC. However, since the amplitude of the SDM quantization error signal error is very small, the reference voltages Vrefp2 and Vrefn2 of the ADC can be reduced by half, that is,
[0063]
[0064] By reducing the bit count by 1 (from 10-bit to 9-bit), the overall signal-to-noise ratio remains unchanged, but the ADC design can be simplified. Similarly, when the ADC reference voltage is reduced to 1 / 4, the number of bits can be reduced by 2 while maintaining the same quantization accuracy.
[0065] The weight factor wn of the FIR filter can also be converged by minimizing the in-band noise power through an adaptive loop. Figure 6As shown, since the inputs In1 and In2 of the adaptive filter, i.e., the SDM quantization noise, and the output signal of the ADC are correlated, their weight factors can be obtained through iterative convergence of an LMS (least mean square) loop.
[0066] The present invention and its implementation methods are described above. This description is not restrictive. In short, if ordinary technicians in this field are inspired by it and do not depart from the purpose of the invention, they can creatively design structures and embodiments similar to the technical solution, which should fall within the scope of protection of the present invention.
Claims
1. A high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method, characterized in that: The system includes a multi-bit quantizer, a loop filter, a quantization error processing module, an auxiliary analog-to-digital converter (ADC), an adaptive FIR filter, and a signal synthesis module. The multi-bit quantizer has a quantization accuracy of 4 bits or higher and is configured in a Sigma-Delta modulator (SDM) for quantizing the output signal of the loop filter. The auxiliary analog-to-digital converter (ADC) has a quantization accuracy of 9 bits or higher and its reference voltage Vrefp2, Vrefn2 is 1 / 2 of the reference voltage Vrefp1, Vrefn1 of the multi-bit quantizer. k The proportional relationship is (k is a positive integer), and the number of bits of the auxiliary ADC is reduced by k bits synchronously with the reduction of the reference voltage while keeping the quantization accuracy unchanged.
2. A high signal-to-noise ratio, high bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: All poles of the quantization noise transfer function (NTF) derived by the loop filter are located at the origin of the z-domain, so that the NTF has the form of an Nth-order finite impulse response (FIR) filter, such as: Where N ≥ 1 and the coefficient {b} satisfies the stability condition of the Sigma-Delta analog-to-digital converter.
3. A high signal-to-noise ratio, high bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: The quantization error processing module includes a subtractor for extracting a quantization error signal from the multi-bit quantizer and inputting the quantization error signal into an auxiliary analog-to-digital converter (ADC).
4. A high signal-to-noise ratio, high bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: The input of the adaptive FIR filter is the output signal of the auxiliary ADC, the form of its transfer function is completely matched with the NTF derived by the loop filter, and the filter weight factor can be adaptively adjusted by the least mean square (LMS) algorithm to minimize the in-band noise power. The adaptive FIR filter iteratively updates the weight factor of the FIR filter by calculating the correlation of the input signal until the in-band noise power reaches a minimum value.
5. A high signal-to-noise ratio, high bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: The signal synthesis module is used to add the output signal Y(z) of the Sigma-Delta modulator and the output signal of the adaptive FIR filter to generate a final analog-to-digital conversion output signal ADC_OUT(z).
6. A high signal-to-noise ratio, high bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: The reference voltage Vrefp2, Vrefn2 of the auxiliary analog-to-digital converter (ADC) is 1 / 2, 1 / 4 or 1 / 8 of the multi-bit quantizer reference voltage Vrefp1, Vrefn1, and the number of bits of the corresponding auxiliary group analog-to-digital converter is reduced by 1 bit, 2 bits or 3 bits respectively while the quantization accuracy remains unchanged.
7. A high signal-to-noise ratio, high bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: The NTF of the loop filter is an N-order FIR filter, and its transfer function satisfies Make sure that all poles of the NTF are located at the z-domain origin.
8. A high signal-to-noise ratio, high bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: During the convergence of the weight factors of the adaptive FIR filter, the input signals are the quantization noise of the Sigma-Delta modulator and the output signal of the auxiliary ADC, and the weight factors are iteratively adjusted by the LMS algorithm to minimize the in-band noise power.
9. A high signal-to-noise ratio, high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: The output signal of the signal synthesis module satisfies ADC_OUT(z)=Y(z)+NTF(z)·EQaux(z), where EQaux(z) is the quantization noise of the auxiliary ADC. Theoretically, when the FIR weight factor and the NTF coefficient are equal, ADC_OUT(z) has the lowest in-band quantization noise.
10. The high signal-to-noise ratio and high-bandwidth Sigma-Delta analog-to-digital converter and its implementation method according to claim 1, characterized in that: The quantization accuracy of the multi-bit quantizer is 4-5 bits, the quantization accuracy of the auxiliary ADC is 9-12 bits, and the input signal amplitude of the auxiliary ADC is very small and does not exceed 1 / 8 of its reference voltage range.