Vertical channel thin film transistor for 2T0C DRAM and manufacturing method thereof

Abstract

The invention discloses a vertical channel thin film transistor for a 2T0C DRAM (Dynamic Random Access Memory) and a manufacturing method of the vertical channel thin film transistor. Comprising a substrate, a source electrode deposited on the substrate, an interlayer dielectric layer covering the source electrode, a gate dielectric layer deposited on the surface of the interlayer dielectric layer and a drain electrode arranged in the gate dielectric layer, and the drain electrode forms a conical ring shape; a vertical cylindrical channel is formed in the interlayer dielectric layer, and the bottom of the channel is located in the source electrode; and the vertical cylindrical channel is filled with an active layer. According to the invention, the regulation and control capability of the grid electrode is obviously enhanced through distributed grid electrode control, the short-channel effect is effectively inhibited, the saturation current density is greatly improved, the performance of the transistor is obviously improved, and the transistor is suitable for the fields of artificial intelligence accelerators, storage and calculation integrated chips, high-bandwidth memories and the like and has wide application prospects. And the requirements of high-performance calculation and storage application can be met.

Description

Technical Field

[0001] The present invention belongs to the field of microelectronics technology and relates to a vertical channel thin film transistor for 2TOC DRAM and a manufacturing method thereof. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that uses the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. Since Robert Dennard invented the single-transistor, single-capacitor (1T1C) DRAM architecture in 1966, this technology has been the core storage medium for digital systems. However, as the process node has exceeded 10nm, traditional DRAM architecture has gradually developed some limitations. For example, at a 50nm cell size, the equivalent oxide thickness (EOT) of the storage capacitor needs to be compressed to below 0.4nm, close to the critical thickness of SiO2 quantum tunneling (0.35nm), causing the leakage current density to surge to >1×10 -7 A / cm 2 While 3D deep trench capacitor technology can increase density, the 100:1 aspect ratio at the 5nm node results in etch uniformity deviation exceeding 15%, significantly increasing process control difficulties. Furthermore, refresh power consumption caused by DRAM's destructive read mechanism accounts for 35% of 128Gb chips. The DDR5 standard shortens the refresh cycle to 16ms at 85°C, further degrading energy efficiency by 28%. Furthermore, the 120mV capacitor crosstalk voltage caused by stacking more than eight layers in 3D stacking technologies (such as HBM) pushes bit error rates close to the error correction limit, posing severe challenges to the sustainability of traditional technology approaches.

[0003] To overcome the physical limitations of the 1T1C architecture, the academic community has been exploring the capacitor-less DRAM (2T0C) architecture since the 1990s, replacing dedicated storage capacitors with read transistor gate capacitance. Early polysilicon-based solutions suffered from subthreshold leakage current (Ioff>1×10 -12 A / μm) results in a data retention time of only 10ms; in 2008, Sony introduced oxide semiconductors (such as ZnO-TFT), which reduced the off-state current (Ioff) to 3×10 -15A / μm and extended the retention time to 1 second, but its low mobility resulted in write speeds >100ns, failing to meet DDR3 standards. More seriously, the threshold voltage (Vth) of oxide TFTs drifted by as much as ΔVth of 0.3V at high temperatures. Even with an Al2O3 passivation layer that suppressed ΔVth to 0.08V at 120°C, stress-induced cracks in the IGZO (Indium Gallium Zinc Oxide) channel still resulted in yields below 70%, stagnate- ing the technology's industrialization.

[0004] In 2020, the breakthrough of the joint team of imec and Intel in the field of IGZO TFT injected new momentum into 2T0C technology. By controlling the oxygen vacancy concentration to 1×10 16 cm -3 Below, the achieved Ioff=3×10 -19 A / μm and HfO2 / Al2O3 stack gate capacitance (Cox = 40aF / μm 2 ) enables a 45nm cell retention time exceeding 400 seconds, marking the first time that capacitor-free DRAM has practical potential. However, the field-effect mobility of planar IGZO-TFTs (μFE ≈ 10cm² / V·s) results in an on-current density of only 28μA / μm², two orders of magnitude lower than Si-FinFETs. This makes it difficult for the write speed and bandwidth to match the AI ​​accelerator's requirement for <2ns access latency. Furthermore, the 200mV storage voltage fluctuation caused by a negative Vth drift ΔVth > 0.1V at 120°C requires additional compensation circuitry, significantly increasing design complexity. Although academic researchers have attempted to improve gate control through a channel-all-around (CAA) structure, the five lithography steps and >5nm gate alignment error have resulted in a 50nm node yield of less than 60%. The three-dimensional stacking capability is far from meeting the 1TB / s single-layer bandwidth and 512Gb / mm² storage density required by HBM4.

[0005] In summary, existing planar amorphous oxide semiconductor thin-film transistors, including but not limited to IGZO TFTs, are limited by lithographic precision, low mobility, and thermally induced threshold shift, resulting in systemic deficiencies in current density, process tolerance, and vertical scalability. Therefore, developing a TFT architecture that combines high drive capability, excellent thermal stability, and scalable three-dimensional integration has become a core challenge for the industrialization of 2T0C DRAM. Summary of the Invention

[0006] This invention addresses the technical bottlenecks of traditional dynamic random access memory (DRAM) in high-density integration, thermal stability, and process feasibility by proposing a multi-hole oxide semiconductor field-effect transistor (MOT) for 2T0C DRAM (two-transistor zero-capacitance DRAM) and its fabrication method. Through innovative device design and process optimization, this invention achieves breakthroughs in gate controllability, on-current, on-off ratio, thermal stability, and three-dimensional stacking capability, providing a solution for the industrialization of next-generation high-density, low-power memory.

[0007] In a first aspect, the present invention provides a vertical channel thin film transistor for a 2TOC DRAM, comprising: substrate; a source electrode deposited on the substrate; an interlayer dielectric (ILD) layer covering the source; a gate dielectric layer deposited on a surface of the interlayer dielectric (ILD) layer; a drain electrode disposed inside the gate dielectric layer; A vertical cylindrical channel is formed in the ILD layer, and the bottom of the channel is located inside the source electrode; the interior of the vertical cylindrical channel is filled with an active layer; the bottom of the drain electrode contacts the bottom of the active layer; A plurality of cylindrical holes are provided inside the active layer, and gates are provided inside the cylindrical holes.

[0008] Furthermore, a gate dielectric layer is provided outside the gate, and the gate dielectric layer adopts High-k (high dielectric constant) dielectric or other dielectrics, including but not limited to Al2O3 / HfO2 stack (aluminum oxide / hafnium oxide stack).

[0009] Furthermore, the plurality of cylindrical holes are symmetrically distributed along the horizontal and vertical diameter directions; furthermore, the number of the cylindrical holes is five.

[0010] Furthermore, the material of the active layer is an amorphous oxide semiconductor, and its composition changes in a gradient along the channel height direction.

[0011] Furthermore, the material of the metal gate is not limited, and commonly used TaN, TiN, TiAl or other gate materials can be used.

[0012] Furthermore, the material and shape of the drain are not limited. For example, the material can be selected from TiN / Pt stack, NiPtSi / TiN or other common drain materials. Its shape can be a conical ring with the outer wall forming a certain inclination angle, such as 45°.

[0013] In a second aspect, the present invention provides a method for preparing the vertical channel thin film transistor for 2TOC DRAM, comprising the following steps: depositing a source metal layer on the substrate; Depositing an interlayer dielectric (ILD) layer and planarizing the surface by chemical mechanical polishing (CMP); A circular pattern is defined on the ILD layer by photolithography, and vertical cylindrical trenches are etched; The active layer is gradiently deposited in the cylindrical trench using a thin film deposition process, and the surface is flattened by chemical mechanical polishing (CMP); Etching a plurality of cylindrical holes in the active layer and filling the gate dielectric layer and the gate in sequence; A conical ring-shaped drain trench with an inclined outer wall is formed by anisotropic etching, and then a drain electrode is deposited; Deposit gate metal again and etch away the gate metal except for the gate area; Thermal annealing is performed in a nitrogen atmosphere to complete the preparation.

[0014] Furthermore, a low-temperature process with a full-process temperature of ≤400°C is adopted to avoid thermal damage to the underlying logic circuit.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention adopts a vertical cylindrical IGZO channel, and forms uniformly distributed tiny holes inside by etching, which expands the effective gate control area to the center of the channel, thereby reducing the subthreshold swing and realizing distributed gate control, aiming to further improve the gate control capability and current uniformity. This design greatly enhances the control capability of channel carriers through the three-dimensional electric field superposition effect, and has low-temperature preparation conditions and is compatible with back-end processes. Among them, the amorphous IGZO has a gradient composition, and the oxygen vacancy distribution is regulated by atomic layer deposition (ALD). The built-in electric field is formed by the composition gradient, which accelerates the transport of carriers from the source to the drain, further improves the saturation current density, and suppresses gate leakage. In addition, the five-hole distributed gate design greatly reduces the process complexity and reduces the dependence on multi-layer masks.

[0016] 2. This invention designs a three-dimensional conical ring-shaped trench with a sloping sidewall on one side and fills it with a drain electrode. This increases the electrode contact area and disperses the electric field lines, suppressing the hot carrier effect, reducing contact resistance, and improving current drive capability. It also avoids the interface damage caused by the multi-step dielectric etching in traditional processes. The bottom source electrode is formed into a ring electrode (such as TiN) at the bottom of the IGZO cylinder through atomic layer deposition (ALD), significantly increasing the contact area and reducing contact resistance. In a vertical stacking architecture, the single-layer unit area can be significantly compressed, and multi-layer stacking is supported.

[0017] In summary, compared with CAA IGZO TFT, the present invention has a larger active area in the cross section and achieves a larger on-current (I on), while the increased gate control capability further suppresses leakage current, thereby achieving a higher on-off ratio. Therefore, the porous vertical-channel IGZO TFT and 2T0C 3D DRAM utilizing it provided by this invention can be widely used in artificial intelligence accelerators, integrated storage and computing chips, and high-bandwidth memory (HBM), meeting the requirements of low power consumption and high-density storage. Its compatibility with existing semiconductor manufacturing processes provides a solid foundation for industrialization. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a cross-sectional view of the device structure of the present invention.

[0019] Figure 2 It is a schematic diagram of the device structure of the present invention cut along the symmetry axis.

[0020] Figure 3 This is a top view of the active layer of the device structure of the present invention.

[0021] Figure 4 The figure is a flow chart for preparing the device structure of the present invention, wherein (a) to (i) are schematic diagrams of each step.

[0022] Markings in the figure: 1, substrate; 2, source; 3, interlayer dielectric layer; 4, active layer; 5, gate dielectric layer; 6, gate; 7, drain. DETAILED DESCRIPTION

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] like Figure 1 As shown, the present invention provides a vertical channel thin film transistor for 2T0C DRAM, comprising: A substrate 1, a source electrode 2 deposited on the substrate 1, an interlayer dielectric (ILD) layer covering the source electrode 2, a gate dielectric layer 5 deposited on a surface of the interlayer dielectric (ILD) layer, and a drain electrode 7 disposed within the gate dielectric layer 5, wherein the drain electrode 7 is formed in a conical ring shape; In a preferred embodiment of the present invention, the drain electrode 7 is a TiN / Pt stack, and the outer wall of the conical ring has an inclination angle of 45°; A vertical cylindrical channel is formed in the ILD layer, and the bottom of the channel is located inside the source electrode 2; the vertical cylindrical channel is filled with an active layer 4, and the active layer 4 is made of an amorphous oxide semiconductor; the bottom of the drain electrode 7 is in contact with the bottom of the active layer 4; In a preferred embodiment of the present invention, the active layer 4 is made of indium gallium zinc oxide (IGZO), and its composition changes gradually along the channel height direction. Specifically, In:Ga:Zn changes gradually from 5:3:2 at the bottom to 3:4:3 at the top. A plurality of cylindrical holes symmetrically distributed along the horizontal and vertical diameter directions are provided inside the active layer 4 , a gate 6 is provided inside the cylindrical holes, and a gate dielectric layer 5 is provided outside the gate 6 .

[0025] In a preferred embodiment of the present invention, the gate 6 is made of TiN, and the gate dielectric layer 5 is made of Al2O3 / HfO2 stacked layers.

[0026] In a preferred embodiment of the present invention, Figure 2 、 Figure 3 As shown, the number of cylindrical holes is five. The distributed five-hole gate 6 achieves three-dimensional control of the IGZO channel through the local electric field superposition effect. Compared with the planar gate 6 or the single-hole CAA structure, the multi-hole layout can expand the effective control area of ​​the gate 6 to the center of the channel without increasing the process difficulty, thereby reducing the subthreshold swing and suppressing the short channel effect. At the same time, the Al2O3 / HfO2 dielectric stack is optimized through band engineering (HfO2 has a high k value, which improves the gate control capability, and Al2O3 inhibits the diffusion of oxygen vacancies), further reducing the leakage current and threshold voltage drift.

[0027] like Figure 4 As shown, the present invention provides a method for preparing the vertical channel thin film transistor for 2TOC DRAM, comprising the following steps: like Figure 4 As shown in (a), an 8-inch p++-type heavily doped silicon wafer is used as the substrate. A 100 nm silicon dioxide insulating layer is grown by low-pressure chemical vapor deposition (LPCVD), and then annealed to eliminate internal stress in the film. The surface of the silicon dioxide insulating layer undergoes a standard RCA cleaning process to remove organic contaminants, particles, and metal ions, followed by plasma activation treatment.

[0028] like Figure 4 As shown in (a), a 200 nm titanium nitride (TiN) layer is deposited on the surface of the activated substrate 11 by reactive magnetron sputtering as the source 2 metal layer; an electron beam lithography technique is used to form a 200×200 nm 2 The source 2 pattern is transferred to the TiN layer by ICP etching technology to form a source 2 structure.

[0029] After etching, the residual photoresist is removed by O2 plasma ashing, the surface oxide layer is removed by HF solution, and finally it is rinsed with deionized water and blown dry with nitrogen to complete the patterning of the source 2 metal layer.

[0030] like Figure 4As shown in (b)-(c), a 300 nm thick SiO2 layer was grown by plasma-enhanced chemical vapor deposition (PECVD) as the ILD layer. Annealing was performed to eliminate voids and reduce hydrogen content. Electron beam lithography (EBL) was then used to define circular patterns with a diameter of 120 nm on the ILD layer. Inductively coupled plasma etching (ICP) etching was performed using a CF4 / CHF3 / Ar gas mixture.

[0031] like Figure 4 As shown in (d), an amorphous IGZO layer with a total thickness of 60 nm was grown in the cylindrical hole by plasma enhanced atomic layer deposition (PEALD), followed by chemical mechanical polishing (CMP) using Cabot SS25 polishing liquid.

[0032] like Figure 4 As shown in (e)-(f) in the figure, a five-hole array with a pore diameter of 20 nm, a pore spacing of 20 nm, and an outermost hole edge 10 nm away from the IGZO cylindrical wall is etched by focused ion beam (FIB). Subsequently, 2 nm Al2O3 and 3 nm HfO2 are deposited on the surface in sequence as gate dielectric layers by PEALD.

[0033] like Figure 4 As shown in (g), a 15 nm TiN metal gate was deposited by PEALD, followed by CMP using Cabot iCue 5001 polishing slurry.

[0034] like Figure 4 As shown in (h), a two-step etching process is used to form a conical annular groove with an inner wall verticality of >88° and an outer wall angle of 45°±2°. A 2 nm TiN adhesion layer is grown by atomic layer deposition (ALD) at 250°C, and then 3 nm platinum (Pt) is deposited by magnetron sputtering at a 45° angle to form a conical drain 7.

[0035] like Figure 4 As shown in (i), metal TiN is deposited again, and the TiN in the non-gate 6 region is removed by etching with a Cl2 / Ar mixed gas. The device is subjected to rapid thermal annealing (RTA) in an N2 / H2 atmosphere at a temperature of 300°C for 60 seconds to complete the preparation.

[0036] Compared to traditional CAA structures, the five-hole distributed gate design of this invention significantly reduces process complexity. Existing CAA technology requires multiple photolithography and mask alignment steps to achieve a fully surrounding gate. This solution, however, uses FIB to precisely etch a limited number of small holes (only five), combined with the excellent step coverage capability of PEALD, reducing reliance on multi-layer masks. Furthermore, the conical annular trench etching design achieves electrical isolation between the gate and the channel in a single step, avoiding the interface damage caused by the multi-step dielectric etching in traditional processes and significantly improving yield.

[0037] Furthermore, the entire process temperature of this invention is ≤400°C, making it fully compatible with back-end-of-line (BEOL) processes. The low-temperature PEALD deposition and RTA annealing process of IGZO avoids thermal damage to the underlying logic circuitry. A gradient composition design regulates oxygen vacancy concentration, balancing carrier mobility and stability. The TiN / Pt stack electrode combines a low-resistance metal with an adhesion layer (TiN). The Pt provides excellent oxidation resistance, while the TiN acts as an adhesion layer between the Pt and IGZO, ensuring low resistivity while also achieving excellent oxidation resistance and contact properties.

[0038] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A vertical channel thin film transistor for 2TOC DRAM, comprising: substrate (1); a source electrode (2) deposited on the substrate (1); an interlayer dielectric layer (3) covering the source electrode (2); a gate dielectric layer (5) deposited on the surface of the interlayer dielectric layer (3); a drain electrode (7) disposed inside the gate dielectric layer (5); The invention is characterized in that a vertical cylindrical channel is formed in the interlayer dielectric layer (3), and the bottom of the channel is located inside the source electrode (2); the interior of the vertical cylindrical channel is filled with an active layer (4); the bottom of the drain electrode (7) is in contact with the bottom of the active layer (4); A plurality of cylindrical holes are provided inside the active layer (4), and gate electrodes (6) are provided inside the cylindrical holes.

2. The vertical channel thin film transistor for 2TOC DRAM according to claim 1, wherein: A gate dielectric layer (5) is provided outside the gate (6), and the gate dielectric layer (5) is made of a high dielectric constant medium.

3. The vertical channel thin film transistor for 2TOC DRAM according to claim 2, wherein: The gate dielectric layer (5) is an Al2O3 / HfO2 stacked layer.

4. The vertical channel thin film transistor for 2TOC DRAM according to claim 1, wherein: The plurality of cylindrical holes are symmetrically distributed along horizontal and vertical diameter directions.

5. The vertical channel thin film transistor for 2TOC DRAM according to claim 4, wherein: The number of the cylindrical holes is five.

6. The vertical channel thin film transistor for 2TOC DRAM according to claim 1, wherein: The material of the active layer (4) is an amorphous oxide semiconductor, and the components in the amorphous oxide semiconductor change in a gradient along the channel height direction.

7. The vertical channel thin film transistor for 2TOC DRAM according to claim 1, wherein: The gate (6) is a metal gate.

8. The vertical channel thin film transistor for 2TOC DRAM according to claim 1, wherein: The drain electrode (7) is a metal drain electrode; the drain electrode (7) is formed in a conical ring shape.

9. A method for preparing a vertical channel thin film transistor for a 2TOC DRAM according to any one of claims 1 to 8, characterized in that: The following steps are involved: Depositing a source electrode (2) metal layer on a substrate (1); depositing an interlayer dielectric layer (3) and planarizing the surface by chemical mechanical polishing; A circular pattern is defined on the interlayer dielectric layer (3) by electron beam lithography, and then a vertical cylindrical trench is etched; Gradient depositing of an active layer (4) in the cylindrical trench and planarizing the surface by chemical mechanical polishing; Etching a plurality of cylindrical holes in the active layer (4) by using a focused ion beam, and sequentially filling the gate dielectric layer (5) and the gate (6); A 45° inclined conical ring drain (7) groove is formed by anisotropic etching, and then the drain (7) is deposited; Depositing another layer of metal and etching away the metal except for the gate (6) area; Thermal annealing is performed in a nitrogen atmosphere to complete the preparation.

10. The preparation method according to claim 9, characterized in that The preparation temperature during the entire preparation process is lower than 400°C.

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