Semiconductor device and manufacturing method thereof, power module, power conversion circuit, and vehicle

Abstract

The embodiment of the invention discloses a semiconductor device, a manufacturing method, a power module, a power conversion circuit and a vehicle. The semiconductor device includes a semiconductor body including a first surface, a second surface, a first device region, and a second device region; the first device region comprises a well region, a first region and a channel layer, and the first region is in contact with the channel layer; a gate trench; a first insulating layer; a first trench located in the second device region; the second device region further comprises a second insulating layer and a filling layer; a trench gate; an interlayer insulating layer; a Schottky metal layer; a drain electrode; and a source electrode. According to the technical scheme of the embodiment of the invention, the depletion type semiconductor device is formed and is in a conducting state and a cut-off state in a normal state, negative voltage needs to be applied between the grid electrode and the source electrode to cut off the channel, the response can be faster, the current circulation can be controlled, and the conducting loss is smaller. And a Schottky structure is integrated, so that the forward conduction voltage drop of the device is reduced, and the energy loss of the device in a reverse follow current state is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle. Background Art

[0002] Wide bandgap semiconductor materials such as silicon carbide (SiC), as representatives of the third generation of semiconductor materials, have the advantages of high breakdown electric field, high thermal conductivity, high electron saturation rate and strong radiation resistance. Therefore, semiconductor devices made of SiC materials can not only operate stably at higher temperatures, but are also suitable for high voltage and high frequency scenarios.

[0003] The SiC metal-oxide-semiconductor field-effect transistor (MOSFET) in the prior art is an enhancement-mode device, which is normally non-conductive. To conduct, a positive voltage needs to be applied between the gate and the source to form a channel conduction in the device.

[0004] However, enhancement-mode devices have higher conduction losses and slower response speeds. SiC products also suffer from a large body diode conduction voltage drop across their PN junctions, which can affect device performance. Summary of the Invention

[0005] The present invention provides a semiconductor device and a manufacturing method thereof, a power module, a power conversion circuit and a vehicle to solve the problems of high conduction loss, slow response speed and large conduction voltage drop of semiconductor devices.

[0006] According to one aspect of the present invention, there is provided a semiconductor device, comprising:

[0007] A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a first device region and a second device region; the first device region and the second device region are connected; the first device region comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, and the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, and the channel layer is located between the well region and the sidewalls of the gate trench; the first device region further comprises a first insulating layer, and the first insulating layer is located on the bottom surface and sidewalls of the gate trench; a first trench is further provided on the first surface, and the first trench extends from the first surface into the semiconductor body, and the first trench is located in the second device region; the second device region further comprises a second insulating layer and a filling layer; the second insulating layer is located on the bottom surface and sidewalls of the first trench; the filling layer is located on a side of the second insulating layer away from the semiconductor body;

[0008] A trench gate is located in the gate trench on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body from the trench gate;

[0009] An interlayer insulating layer is located on the first surface; the interlayer insulating layer is provided with a first through hole, a second through hole and a third through hole; the first through hole exposes a portion of the trench gate; the second through hole exposes a portion of the first region; the third through hole exposes a portion of the filling layer and the second insulating layer;

[0010] a Schottky metal layer, located on a side of the interlayer insulating layer away from the first surface;

[0011] a source electrode, located on a side of the Schottky metal layer away from the first surface;

[0012] The drain is located on the second surface.

[0013] Optionally, the ion concentration of the channel layer is lower than the ion concentration of the first region.

[0014] Optionally, the semiconductor body further includes a second region; the second region is set to the second conductivity type and is located on the first surface; the second region is connected to the first region.

[0015] Optionally, the semiconductor body further includes a third region; the third region is set to the second conductivity type and is located at the bottom and sidewalls of the first trench.

[0016] Optionally, in the direction from the first surface to the second surface, the depth of the third region is greater than the depth of the gate trench.

[0017] Optionally, the semiconductor device further comprises a gate electrode;

[0018] The gate electrode passes through the first through hole and reaches the trench gate;

[0019] The source electrode passes through the second through hole to reach the first region; the source electrode also passes through the third through hole to reach the filling layer.

[0020] Optionally, the semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0021] According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising:

[0022] A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a first device region and a second device region; the first device region and the second device region are connected; the first device region comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, and the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, the channel layer is located between the well region and the sidewalls of the gate trench; the first device region further comprises a first insulating layer, the first insulating layer is located on the bottom surface and sidewalls of the gate trench; a first trench is further provided on the first surface, the first trench extends from the first surface into the semiconductor body, and the first trench is located in the second device region; the second device region further comprises a second insulating layer and a filling layer; the second insulating layer is located on the bottom surface and sidewalls of the first trench; the filling layer is located on a side of the second insulating layer away from the semiconductor body;

[0023] A trench gate is formed on a side of the first insulating layer away from the semiconductor body in the gate trench; the first insulating layer is used to insulate the semiconductor body and the trench gate;

[0024] An interlayer insulating layer is formed on the first surface, wherein the interlayer insulating layer is provided with a first through hole, a second through hole and a third through hole; the first through hole exposes a portion of the trench gate; the second through hole exposes a portion of the first region; and the third through hole exposes a portion of the filling layer and the second insulating layer;

[0025] forming a Schottky metal layer on a side of the interlayer insulating layer away from the first surface;

[0026] forming a source electrode on a side of the Schottky metal layer away from the first surface;

[0027] A drain electrode is formed on the second surface.

[0028] Optionally, providing a semiconductor body includes:

[0029] Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a first device region and a second device region; the first device region and the second device region being in communication;

[0030] forming a first mask layer on the first surface, wherein the first mask layer is provided with a fourth through hole;

[0031] forming a transition well region on the first surface exposed by the fourth through hole, wherein the transition well region is set to the second conductivity type;

[0032] removing the first mask layer;

[0033] forming a second mask layer on the first surface, wherein the second mask layer is provided with a fifth through hole;

[0034] forming a first transition region on the first surface exposed by the fifth through hole, wherein the first transition region is set to a first conductivity type;

[0035] removing the second mask layer;

[0036] forming a third mask layer on the first surface, wherein the third mask layer is provided with a sixth through hole;

[0037] forming a fourth mask layer on the bottom and sidewall of the sixth through hole, wherein the fourth mask layer and the third mask layer are made of different materials;

[0038] forming a gate trench and a first trench on the first surface, wherein the gate trench and the first trench penetrate the fourth mask layer and extend from the first surface into the semiconductor body;

[0039] forming a fifth mask layer in the gate trench and the first trench;

[0040] removing the fourth mask layer;

[0041] forming a channel layer on the sidewalls of the transition well region and the gate trench and the sidewalls of the first trench; the channel layer is set to be of the first conductivity type; after forming the channel layer, the transition well region retained is used as the well region, and the transition first region retained is used as the first region;

[0042] removing the third mask layer and the fifth mask layer;

[0043] forming a first insulating layer in the gate trench; and forming a second insulating layer in the first trench;

[0044] A filling layer is formed in the first trench on a side of the second insulating layer away from the semiconductor body.

[0045] Optionally, forming a fourth mask layer on the bottom and sidewall of the sixth through hole includes:

[0046] A fourth mask layer including silicon nitride is formed on the bottom and sidewalls of the sixth through hole.

[0047] Optionally, providing a semiconductor body includes:

[0048] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0049] According to another aspect of the present invention, a power module is provided. The power module includes a substrate and at least one semiconductor device as described above. The substrate is used to support the semiconductor device.

[0050] According to another aspect of the present invention, there is provided a power conversion circuit, the power conversion circuit being used for one or more of current conversion, voltage conversion, and power factor correction;

[0051] The power conversion circuit includes a circuit board and at least one of the above-mentioned semiconductor devices, and the semiconductor device is electrically connected to the circuit board.

[0052] According to another aspect of the present invention, a vehicle is provided, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0053] The technical solution of the embodiment of the present invention is to set a channel layer of opposite conductivity type to the well region between the sidewalls of the well region and the gate trench. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-mode semiconductor device. Under normal conditions, it is in the on state. In the off state, a negative gate-source voltage is applied to the gate to cut off the channel. Compared with enhancement-mode semiconductor devices, the technical solution provided by the embodiment of the present invention reduces the conduction loss of the semiconductor device, improves the response speed and the speed of controlling the flow of current, and is more suitable for high-frequency circuits and switching circuits. At the same time, the integration of a Schottky structure in the semiconductor device can reduce the forward conduction voltage drop of the semiconductor device, thereby reducing the energy loss of the semiconductor device in the reverse freewheeling state. Among them, the trench gate is located in the gate trench and extends from the first surface into the semiconductor body. Compared with semiconductor devices including a planar gate structure, there is no need to set a junction field-effect transistor (JFET) region on one side of the well region, thereby reducing the on-resistance of the semiconductor device.

[0054] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0055] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0056] Figure 1 is a schematic structural diagram of a semiconductor device provided according to an embodiment of the present invention;

[0057] Figure 2 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0058] Figure 3-Figure 6is a cross-sectional view corresponding to each step of a method for manufacturing a semiconductor device provided in accordance with an embodiment of the present invention;

[0059] Figure 7 According to an embodiment of the present invention, Figure 2 A schematic diagram of the process included in S110;

[0060] Figure 8-Figure 20 According to an embodiment of the present invention, Figure 2 The cross-sectional views corresponding to the steps included in S110 are shown in FIG. DETAILED DESCRIPTION

[0061] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0062] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0063] In order to solve the problems of high conduction loss, slow response speed and large conduction voltage drop of semiconductor devices, the embodiments of the present invention provide the following technical solutions:

[0064] Figure 1 FIG. 1 is a schematic diagram of the structure of a semiconductor device provided according to an embodiment of the present invention. Figure 1As shown, the semiconductor device includes: a semiconductor body 100, including a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a first device region 30 and a second device region 40; the first device region 30 and the second device region 40 are connected; the first device region 30 includes a well region 103, a first region 104 and a channel layer 105, the first region 104 and the channel layer 105 are in contact with each other, the first region 104 is set to a first conductivity type and is located on the first surface 101, and the well region 103 is set to a second conductivity type and is located on the first surface 101. A region 104 is located on a side away from the first surface 101; a gate trench 106 is provided on the first surface 101, and the gate trench 106 extends from the first surface 101 into the semiconductor body 100; a channel layer 105 is set to a first conductivity type, and the channel layer 105 is located between the well region 103 and the sidewall of the gate trench 106; the first device region 30 further includes a first insulating layer 107, and the first insulating layer 107 is located on the bottom surface and sidewall of the gate trench 106; the first surface 101 is also provided with a first trench 108, and the first trench 108 extends from the first surface 101 In the semiconductor body 100, the first trench 108 is located in the second device region 40; the second device region 40 further includes a second insulating layer 109 and a filling layer 110; the second insulating layer 109 is located on the bottom surface and sidewalls of the first trench 108; the filling layer 110 is located on the side of the second insulating layer 109 away from the semiconductor body 100; the trench gate 200 is located in the gate trench 106 on the side of the first insulating layer 107 away from the semiconductor body 100; the first insulating layer 107 is used to insulate the semiconductor body 100 and the trench gate 200; the interlayer insulating layer 300, Located on the first surface 101; the interlayer insulating layer 300 is provided with a first through hole CT1, a second through hole CT2 and a third through hole CT3; the first through hole CT1 exposes a portion of the trench gate 200; the second through hole CT2 exposes a portion of the first region 104; the third through hole CT3 exposes a portion of the filling layer 110 and the second insulating layer 109; the Schottky metal layer 400 is located on the side of the interlayer insulating layer 300 away from the first surface 101; the source 500 is located on the side of the Schottky metal layer 400 away from the first surface 101; the drain 600 is located on the second surface 102.

[0065] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.

[0066] like Figure 1 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through one or more epitaxial processes, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0067] The semiconductor body 100 also includes a first device region 30 and a second device region 40. For example, the first device region 30 may be a MOSFET structure region, and the second device region 40 may be a Schottky structure region. A gate trench 106 and a first trench 108 are provided on the first surface 101 of the semiconductor body 100. Both the gate trench 106 and the first trench 108 can be formed by photolithography and etching processes. If the trench depths of the gate trench 106 and the first trench 108 are the same, they can be formed by a one-step photolithography and etching process; if the trench depths of the gate trench 106 and the first trench 108 are different, two photolithography and etching steps are required.

[0068] The semiconductor body 100 also includes a first insulating layer 107. The first insulating layer 107 can be formed by a thermal oxidation process. The first insulating layer 107 can be a gate oxide layer. The first insulating layer 107 is located on the bottom surface and sidewalls of the gate trench 106. Polysilicon is deposited on the side of the first insulating layer 107 facing away from the semiconductor body 100 within the gate trench 106 to form a trench gate 200. The first insulating layer 107 is used to insulate the semiconductor body 100 from the trench gate 200.

[0069] The interlayer insulating layer 300 can be made of silicon dioxide. The interlayer insulating layer 300 can provide electrical isolation, prevent electron migration between different metal layers, and avoid diffusion or penetration between substances. The interlayer dielectric layer 300 can be formed by plasma-enhanced chemical vapor deposition. The Schottky metal layer 400 can be formed by depositing two metal layers. The deposited two metal layers can include titanium (Ti) and titanium nitride (TiN).

[0070] The source electrode 500 can be formed by depositing metal on the first surface 101. Metal is deposited on the second surface 102 to form the drain electrode 600. The deposited metal can be titanium, nickel (Ni), or silver (Ag).

[0071] The technical solution of the embodiment of the present invention is to set a channel layer 105 of opposite conductivity type to the well region 103 between the sidewalls of the well region 103 and the gate trench 106. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, there are carriers of the first conductivity type, making the semiconductor device a depletion-mode semiconductor device. Under normal conditions, it is in the on state. In the off state, a negative gate-source voltage is applied to the gate to cut off the channel. Compared with enhancement-mode semiconductor devices, the technical solution provided by the embodiment of the present invention reduces the conduction loss of the semiconductor device, improves the response speed and the speed of controlling the flow of current, and is more suitable for high-frequency circuits and switching circuits. At the same time, the integration of a Schottky structure in the semiconductor device can reduce the forward conduction voltage drop of the semiconductor device, thereby reducing the energy loss of the semiconductor device in the reverse freewheeling state. Among them, the trench gate 200 is located in the gate trench 106 and extends from the first surface 101 to the semiconductor body 100. Compared with semiconductor devices with a planar gate structure, there is no need to set a JFET region on the side of the well region 103, which reduces the on-resistance of the semiconductor device.

[0072] In an optional embodiment of the present invention, reference Figure 1 , the ion concentration of the channel layer 105 is lower than the ion concentration of the first region 104 .

[0073] Specifically, the ion concentration of the channel layer 105 is 10 16 cm -3 -10 17 cm -3 The ion concentration of the channel layer 105 is lower than the ion concentration of the first region 104 , which can reduce the manufacturing cost of the semiconductor device.

[0074] In an optional embodiment of the present invention, reference Figure 1 The semiconductor body further includes a second region 111 ; the second region 111 is configured as a second conductivity type and is located on the first surface 101 ; the second region 111 is connected to the first region 104 .

[0075] Specifically, for an N-type MOSFET, the second region 111 is a P+ doped region, and the well region 103 is a P-well region. The doping concentration of the second region 111 is greater than that of the well region 103 , and a good ohmic contact can be formed with the source 500 .

[0076] In an optional embodiment of the present invention, reference Figure 1 The semiconductor body further includes a third region 112 ; the third region 112 is configured to be of the second conductivity type and is located at the bottom and sidewalls of the first trench 108 .

[0077] Specifically, the third region 112 may be formed by an ion implantation process. For example, for an N-type MOSFET, the third region 112 is a P+ doped region.

[0078] In an optional embodiment of the present invention, reference Figure 1 In the direction X from the first surface 101 to the second surface 102 , the depth of the third region 112 is greater than the depth of the gate trench 106 .

[0079] Specifically, in the direction X from the first surface 101 to the second surface 102 , setting the depth of the third region 112 greater than the depth of the gate trench 106 can reduce the forward conduction voltage drop of the semiconductor device, thereby reducing the energy loss of the semiconductor device in the reverse freewheeling state.

[0080] In an optional embodiment of the present invention, reference Figure 1 The semiconductor device further includes a gate electrode 700 ; the gate electrode 700 passes through the first through hole CT1 to reach the trench gate 200 ; the source 500 passes through the second through hole CT2 to reach the first region 104 ; the source 500 also passes through the third through hole CT3 to reach the filling layer 110 .

[0081] Specifically, the gate electrode 700 may pass through the first through hole CT1 and connect to the trench gate 200 to provide an electrical signal to the trench gate 200. The source 500 contacts both the first region 104 and the filling layer 110 in the Schottky structure.

[0082] In an optional embodiment of the present invention, reference Figure 1 , the semiconductor body 100 includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0083] The semiconductor body 100 includes a silicon carbide semiconductor body, the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device, the semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0084] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0085] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention. Figure 2 As shown, the method for manufacturing the semiconductor device includes:

[0086] S110. Provide a semiconductor body, which includes a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a first device region and a second device region; the first device region and the second device region are connected; the first device region includes a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductive type and is located on the first surface, and the well region is set to a second conductive type and is located on a side of the first region away from the first surface; a gate trench is set on the first surface, and the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductive type, and the channel layer is located between the well region and the sidewall of the gate trench; the first device region also includes a first insulating layer, and the first insulating layer is located on the bottom and sidewall of the gate trench; a first trench is also provided on the first surface, and the first trench extends from the first surface into the semiconductor body, and the first trench is located in the second device region; the second device region also includes a second insulating layer and a filling layer; the second insulating layer is located on the bottom and sidewall of the first trench; the filling layer is located on the side of the second insulating layer away from the semiconductor body.

[0087] refer to Figure 3, providing a semiconductor body 100, the semiconductor body 100 further comprising a first device region 30 and a second device region 40; the first device region 30 and the second device region 40 are connected; the first device region 30 comprises a well region 103, a first region 104 and a channel layer 105, the first region 104 and the channel layer 105 are in contact with each other, the first region 104 is set to a first conductivity type and is located on a first surface 101, the well region 103 is set to a second conductivity type and is located on a side of the first region 104 away from the first surface 101; the first surface 101 is provided with a gate trench 106, the gate trench 106 extends from the first surface 101 into the semiconductor body 100; the channel layer 105 It is set to the first conductivity type, and the channel layer 105 is located between the well region 103 and the side wall of the gate trench 106; the first device region 30 also includes a first insulating layer 107, and the first insulating layer 107 is located on the bottom surface and side wall of the gate trench 106; the first surface 101 is also provided with a first trench 108, and the first trench 108 extends from the first surface 101 to the semiconductor body 100, and the first trench 108 is located in the second device region 40; the second device region 40 also includes a second insulating layer 109 and a filling layer 110; the second insulating layer 109 is located on the bottom surface and side wall of the first trench 108; the filling layer 110 is located on the side of the second insulating layer 109 away from the semiconductor body 100.

[0088] In an embodiment of the present invention, the semiconductor device includes but is not limited to an N-type MOSFET or a P-type MOSFET. The semiconductor body 100 may include a third-generation wide bandgap semiconductor material such as a silicon carbide semiconductor body or a gallium nitride semiconductor body. For an N-type MOSFET, the first conductivity type is N-type and the second conductivity type is P-type. For a P-type MOSFET, the first conductivity type is P-type and the second conductivity type is N-type. Exemplarily, for an N-type MOSFET, the first region 104 is an N+ doped region, and the N-type doping ions in the N+ doped region may be phosphorus (P) ions or nitrogen (N) ions; the well region 103 is a P-well region, and the P-type doping ions in the P-well region may be aluminum (Al) ions or boron (B) ions. The first region 104 may be formed on the first surface 101 of the semiconductor body 100 by processes such as ion implantation, ion diffusion, or vapor deposition.

[0089] like Figure 3 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and a semiconductor layer formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through one or more epitaxial processes, including chemical vapor epitaxy (CVE), molecular beam epitaxy (MBD), and atomic layer epitaxy (ALE).

[0090] The first surface 101 of the semiconductor body 100 is provided with a gate trench 106 and a first trench 108. Both the gate trench 106 and the first trench 108 can be formed by photolithography and etching processes. The semiconductor body 100 also includes a first insulating layer 107 and a second insulating layer 109. The first insulating layer 107 and the second insulating layer 109 can be formed by a thermal oxidation process. The first insulating layer 107 can be a gate oxide layer. The first insulating layer 107 is located on the bottom surface and sidewalls of the gate trench 106. The second insulating layer 109 is located on the bottom surface and sidewalls of the first trench 108.

[0091] Optional, reference Figure 3 The semiconductor body 100 further includes a second region 111 ; the second region 111 is configured as a second conductivity type and is located on the first surface 101 ; the second region 111 is connected to the first region 104 .

[0092] Optional, reference Figure 3 The semiconductor body 100 further includes a third region 112 ; the third region 112 is configured to be of the second conductivity type and is located at the bottom and sidewalls of the first trench 108 .

[0093] S120, forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; the first insulating layer is used to insulate the semiconductor body and the trench gate.

[0094] refer to Figure 4 Polysilicon is deposited on the side of the first insulating layer 107 in the gate trench 106 away from the semiconductor body 100 to form a trench gate 200. The first insulating layer 107 is used to insulate the semiconductor body 100 from the trench gate 200.

[0095] S130, forming an interlayer insulating layer on the first surface, wherein the interlayer insulating layer is provided with a first through hole, a second through hole and a third through hole; the first through hole exposes a portion of the trench gate; the second through hole exposes a portion of the first region; the third through hole exposes a portion of the filling layer and the second insulating layer.

[0096] refer to Figure 5 An interlayer insulating layer 300 is formed on the first surface 101, and the interlayer insulating layer 300 is provided with a first through hole CT1, a second through hole CT2 and a third through hole CT3; the first through hole CT1 exposes a portion of the trench gate 200; the second through hole CT2 exposes a portion of the first region 104; and the third through hole CT3 exposes a portion of the filling layer 110 and the second insulating layer 109.

[0097] Specifically, the interlayer insulating layer 300 can be made of silicon dioxide. The interlayer insulating layer 300 provides electrical isolation, preventing electron migration between different metal layers and preventing diffusion or penetration between substances. The interlayer dielectric layer 300 can be formed by plasma-enhanced chemical vapor deposition. The first through hole CT1, the second through hole CT2, and the third through hole CT3 can be formed by an etching process.

[0098] S140 , forming a Schottky metal layer on a side of the interlayer insulating layer away from the first surface.

[0099] refer to Figure 6 Titanium and titanium nitride are sequentially deposited on a side of the interlayer insulating layer 300 away from the first surface 100 to form a Schottky metal layer 400 .

[0100] S150 , forming a source electrode on a side of the Schottky metal layer away from the first surface.

[0101] refer to Figure 1 , metal is deposited on a side of the Schottky metal layer 400 away from the first surface 101 to form a source 500 .

[0102] S160 , forming a drain on the second surface.

[0103] refer to Figure 1 , metal is deposited on the second surface 102 to form a drain 600. The deposited metal includes but is not limited to aluminum or silver.

[0104] The technical solution of the embodiment of the present invention forms a channel layer 105 of opposite conductivity type to the well region 103 between the sidewalls of the well region 103 and the gate trench 106. There is no need to apply a gate-source voltage to the semiconductor device. Under normal conditions, carriers of the first conductivity type exist, making the semiconductor device a depletion-mode semiconductor device. Under normal conditions, it is in the on state. In the off state, a negative gate-source voltage is applied to the gate to cut off the channel. Compared with enhancement-mode semiconductor devices, the technical solution provided by the embodiment of the present invention reduces the conduction loss of the semiconductor device, improves the response speed and the speed of controlling the flow of current, and is more suitable for high-frequency circuits and switching circuits. At the same time, the integration of a Schottky structure in the semiconductor device can reduce the forward conduction voltage drop of the semiconductor device, thereby reducing the energy loss of the semiconductor device in the reverse freewheeling state. Among them, the trench gate 200 is located in the gate trench 106 and extends from the first surface 101 to the semiconductor body 100. Compared with semiconductor devices with a planar gate structure, there is no need to set a JFET region on the side of the well region 103, which reduces the on-resistance of the semiconductor device.

[0105] Figure 7 According to an embodiment of the present invention, Figure 2 The flow chart of S110 is shown in FIG. Figure 7As shown, in an optional embodiment of the present invention, S110, providing a semiconductor body includes:

[0106] S1101. Provide a semiconductor body, wherein the semiconductor body includes a first surface and a second surface arranged opposite to each other; the semiconductor body also includes a first device region and a second device region; and the first device region and the second device region are connected.

[0107] refer to Figure 8 , providing a semiconductor body 100, the semiconductor body 100 includes a first surface 101 and a second surface 102 arranged opposite to each other; the semiconductor body 100 also includes a first device region 30 and a second device region 40; the first device region 30 and the second device region 40 are connected.

[0108] like Figure 8 As shown, the semiconductor body 100 includes a substrate 10 and an epitaxial layer 20. In some embodiments of the present invention, the semiconductor body 100 may also include only the epitaxial layer 20. In other embodiments of the present invention, the semiconductor body 100 may also include the substrate 10 and semiconductor layers formed by other processes. The epitaxial layer 20 is a semiconductor layer formed on the substrate 10 through one or more epitaxial processes.

[0109] S1102 , forming a first mask layer on the first surface, wherein the first mask layer is provided with a fourth through hole.

[0110] refer to Figure 9 A first mask layer 201 is formed on the first surface 101, and the first mask layer 201 is provided with a fourth through hole CT4. A hard mask (HM) process is applied to form the first mask layer 201 on the first surface 101 of the semiconductor body 100. The first mask layer 201 can also be formed by depositing SiO2 using plasma enhanced chemical vapor deposition (PECVD). The first mask layer 201 is patterned using a photolithography process to form the fourth through hole CT4.

[0111] S1103 , forming a transition well region on the first surface exposed by the fourth through hole, wherein the transition well region is set to be of the second conductivity type.

[0112] refer to Figure 9 A transition well region 1031 is formed on the first surface 101 exposed by the fourth through hole CT4. The transition well region 1031 is configured to have the second conductivity type. The transition well region 1031 can be formed on the first surface 101 exposed by the fourth through hole CT4 by implanting ions of the second conductivity type. Methods for forming the transition well region 1031 also include ion diffusion or vapor deposition processes.

[0113] S1104 , removing the first mask layer.

[0114] refer to Figure 10 , a hydrofluoric acid solution may be used to etch away the first mask layer 201 of the SiO2 material.

[0115] S1105 , forming a second mask layer on the first surface, wherein the second mask layer is provided with a fifth through hole.

[0116] refer to Figure 11 A HM process is applied to form a second mask layer 202 on the first surface 101. The second mask layer 202 is provided with a fifth through hole CT5. The second mask layer 202 is patterned by a photolithography process to form the fifth through hole CT5.

[0117] S1106 , forming a transitional first region on the first surface exposed by the fifth through hole, wherein the transitional first region is set to be of the first conductivity type.

[0118] refer to Figure 11 A transitional first region 1041 is formed on the first surface 101 exposed by the fifth through hole CT5 through an ion implantation process. The transitional first region 1041 is set to be of the first conductivity type.

[0119] S1107 , removing the second mask layer.

[0120] refer to Figure 12 , a hydrofluoric acid solution may be used to etch away the second mask layer 202 of the SiO 2 material.

[0121] S1108 , forming a third mask layer on the first surface, wherein the third mask layer is provided with a sixth through hole.

[0122] refer to Figure 13 A third mask layer 203 is formed on the first surface 101 , and the third mask layer 203 is provided with a sixth through hole CT6 .

[0123] S1109 , forming a fourth mask layer on the bottom and sidewall of the sixth through hole, wherein the fourth mask layer and the third mask layer are made of different materials.

[0124] refer to Figure 13 A fourth mask layer 204 is formed on the bottom and sidewall of the sixth through hole CT6 , and the fourth mask layer 204 and the third mask layer 203 are made of different materials.

[0125] Optional, reference Figure 13 Forming the fourth mask layer 204 on the bottom and sidewall of the sixth through hole CT6 includes: forming the fourth mask layer 204 including silicon nitride on the bottom and sidewall of the sixth through hole CT6.

[0126] Specifically, the material of the third mask layer 203 can be silicon dioxide, and the material of the fourth mask layer 204 can be silicon nitride. The thickness of the deposited silicon nitride can be between 200 Å and 500 Å. The fourth mask layer 204 and the third mask layer 203 are made of different materials. The materials of the fourth mask layer 204 and the third mask layer 203 are distinguished to prevent the third mask layer 203 from being affected when the fourth mask layer 204 is subsequently removed.

[0127] S1110 , forming a gate trench and a first trench on the first surface, wherein the gate trench and the first trench penetrate the fourth mask layer and extend from the first surface into the semiconductor body.

[0128] refer to Figure 14 Through an etching process, a gate trench 106 and a first trench 108 are formed on the first surface 101 . The gate trench 106 and the first trench 108 penetrate the fourth mask layer 204 and extend from the first surface 101 into the semiconductor body 100 .

[0129] S1111 , forming a fifth mask layer in the gate trench and the first trench.

[0130] refer to Figure 15 , a fifth mask layer 205 is formed in the gate trench 106 and the first trench 108. The fifth mask layer 205 may be doped polysilicon.

[0131] S1112 , removing the fourth mask layer.

[0132] refer to Figure 15 Phosphoric acid is used to remove the fourth mask layer 204 made of silicon nitride.

[0133] S1113, forming a channel layer on the sidewalls of the transition well region and the gate trench and the sidewalls of the first trench; the channel layer is set to the first conductivity type; after forming the channel layer, the transition well region retained is used as the well region, and the transition first region retained is used as the first region.

[0134] refer to Figure 16 A channel layer 105 is formed on the sidewalls of the transition well region 1031 and the gate trench 106 as well as the sidewalls of the first trench 108 by an ion implantation process; the channel layer 105 is set to the first conductivity type; after the channel layer 105 is formed, the transition well region 1031 retained is used as the well region 103, and the transition first region 1041 retained is used as the first region 104.

[0135] S1114 , removing the third mask layer and the fifth mask layer.

[0136] refer to Figure 17 The third mask layer 203 of the SiO2 material can be etched away by using a hydrofluoric acid solution. The fifth mask layer 205 can be removed by using an etching process.

[0137] S1115, forming a first insulating layer in the gate trench; forming a second insulating layer in the first trench.

[0138] refer to Figure 18 , a first insulating layer 107 may be formed in the gate trench 106 by a thermal oxidation process; and a second insulating layer 109 may be formed in the first trench 108 .

[0139] In an optional embodiment of the present invention, at S1115 , a first insulating layer is formed in the gate trench; after a second insulating layer is formed in the first trench, the method further includes: forming a sixth mask layer in the gate trench, the first trench and the first surface.

[0140] refer to Figure 18 Doped polysilicon is deposited in the gate trench 106 , the first trench 108 and the first surface 101 to form a sixth mask layer 206 .

[0141] refer to Figure 19 A seventh through hole CT7 and an eighth through hole CT8 are formed in the sixth mask layer 206. An ion implantation process is performed to form a second region 111 at the seventh through hole CT7, and an ion implantation process is performed to form a third region 112 at the eighth through hole CT8. During the ion implantation process to form the third region 112, aluminum ions are implanted at a dose greater than the ion implantation dose of the channel layer 105 in the Schottky structure region, thereby covering the channel layer 105 in the Schottky structure region.

[0142] After forming the second region 111 and the third region 112 , a wet process may be applied to remove the sixth mask layer 206 .

[0143] S1106 , forming a filling layer in the first trench on a side of the second insulating layer away from the semiconductor body.

[0144] refer to Figure 20 、 Figure 3 and Figure 4 Polysilicon is deposited in the gate trench 106, the first trench 108, and the first surface 101 to form a seventh mask layer 207. A filler layer 110 is formed in the first trench 108 on the side of the second insulating layer 109 facing away from the semiconductor body 100 through an etching process. Simultaneously, a trench gate 200 is formed in the gate trench 106 on the side of the first insulating layer 107 facing away from the semiconductor body.

[0145] Optionally, S110, providing a semiconductor body further includes:

[0146] A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

[0147] Specifically, refer to Figure 1The semiconductor body 100 includes a silicon carbide semiconductor body, and the MOSFET semiconductor device is a silicon carbide MOSFET semiconductor device. The semiconductor body 100 includes a gallium nitride semiconductor body, and the MOSFET semiconductor device is a gallium nitride MOSFET semiconductor device.

[0148] Silicon carbide MOSFET semiconductor devices or gallium nitride MOSFET semiconductor devices have the advantages of high voltage resistance, low on-resistance and high frequency, which can further improve the performance of semiconductor devices.

[0149] An embodiment of the present invention provides a power module comprising a substrate and at least one semiconductor device according to any embodiment of the present invention, wherein the substrate is configured to support the semiconductor device. Therefore, the beneficial effects of the power module including any semiconductor device according to any embodiment of the present invention are not further elaborated herein.

[0150] An embodiment of the present invention provides a power conversion circuit, which is used for one or more of current conversion, voltage conversion, and power factor correction; the power conversion circuit includes a circuit board and at least one semiconductor device described in any embodiment of the present invention, and the semiconductor device is electrically connected to the circuit board.

[0151] Therefore, the power conversion circuit includes the beneficial effects of the semiconductor device described in any embodiment of the present invention, which will not be repeated here.

[0152] An embodiment of the present invention also provides a vehicle, which includes a load and the above-mentioned power conversion circuit, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

[0153] Therefore, the beneficial effects of the vehicle including any power conversion circuit package described in any embodiment of the present invention will not be repeated here.

[0154] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0155] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A semiconductor device, characterized in that: include: A semiconductor body, comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a first device region and a second device region; the first device region and the second device region are connected; the first device region comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, the channel layer is located between the well region and the sidewalls of the gate trench; the first device region further comprises a first insulating layer, the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the first surface further comprises a first trench, the first trench extends from the first surface into the semiconductor body, the first trench is located in the second device region; the second device region further comprises a second insulating layer and a filling layer; The second insulating layer is located on the bottom surface and sidewalls of the first trench; the filling layer is located on a side of the second insulating layer away from the semiconductor body; a trench gate located in the gate trench on a side of the first insulating layer away from the semiconductor body; the first insulating layer is used to insulate the semiconductor body from the trench gate; an interlayer insulating layer located on the first surface; the interlayer insulating layer is provided with a first through hole, a second through hole and a third through hole; the first through hole exposes a portion of the trench gate; The second through hole exposes a portion of the first region; the third through hole exposes a portion of the filling layer and the second insulating layer; a Schottky metal layer, located on a side of the interlayer insulating layer away from the first surface; a source electrode, located on a side of the Schottky metal layer away from the first surface; The drain is located on the second surface.

2. The semiconductor device according to claim 1, wherein The ion concentration of the channel layer is lower than the ion concentration of the first region.

3. The semiconductor device according to claim 1, wherein The semiconductor body further includes a second region; the second region is configured to be of a second conductivity type and is located on the first surface; and the second region is connected to the first region.

4. The semiconductor device according to claim 1, wherein The semiconductor body further includes a third region; the third region is configured to be of the second conductivity type and is located at the bottom and sidewalls of the first trench.

5. The semiconductor device according to claim 4, wherein In a direction from the first surface to the second surface, a depth of the third region is greater than a depth of the gate trench. The semiconductor device according to claim 1 , wherein: The semiconductor device further includes a gate electrode; The gate electrode passes through the first through hole to reach the trench gate; The source electrode passes through the second through hole to reach the first region; the source electrode also passes through the third through hole to reach the filling layer.

7. The semiconductor device according to claim 1, wherein The semiconductor body includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

8. A method for manufacturing a semiconductor device, characterized in that: include: A semiconductor body is provided, the semiconductor body comprising a first surface and a second surface arranged opposite to each other; the semiconductor body further comprising a first device region and a second device region; the first device region and the second device region are connected; the first device region comprises a well region, a first region and a channel layer, the first region and the channel layer are in contact with each other, the first region is set to a first conductivity type and is located on the first surface, the well region is set to a second conductivity type and is located on a side of the first region away from the first surface; a gate trench is provided on the first surface, the gate trench extends from the first surface into the semiconductor body; the channel layer is set to the first conductivity type, the channel layer is located between the well region and the sidewalls of the gate trench; the first device region further comprises a first insulating layer, the first insulating layer is located on the bottom surface and sidewalls of the gate trench; the first surface further comprises a first trench, the first trench extends from the first surface into the semiconductor body, the first trench is located in the second device region; the second device region further comprises a second insulating layer and a filling layer; The second insulating layer is located on the bottom surface and sidewalls of the first trench; the filling layer is located on a side of the second insulating layer away from the semiconductor body; forming a trench gate on a side of the first insulating layer away from the semiconductor body in the gate trench; The first insulating layer is used to insulate the semiconductor body and the trench gate; forming an interlayer insulating layer on the first surface, wherein the interlayer insulating layer is provided with a first through hole, a second through hole and a third through hole; the first through hole exposes a portion of the trench gate; The second through hole exposes a portion of the first region; the third through hole exposes a portion of the filling layer and the second insulating layer; forming a Schottky metal layer on a side of the interlayer insulating layer away from the first surface; forming a source electrode on a side of the Schottky metal layer away from the first surface; A drain electrode is formed on the second surface.

9. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor body provided includes: Providing a semiconductor body, the semiconductor body comprising a first surface and a second surface disposed opposite to each other; the semiconductor body further comprising a first device region and a second device region; the first device region and the second device region being in communication; forming a first mask layer on the first surface, wherein the first mask layer is provided with a fourth through hole; forming a transition well region on the first surface exposed by the fourth through hole, wherein the transition well region is set to a second conductivity type; removing the first mask layer; forming a second mask layer on the first surface, wherein the second mask layer is provided with a fifth through hole; forming a first transition region on the first surface exposed by the fifth through hole, wherein the first transition region is set to a first conductivity type; removing the second mask layer; forming a third mask layer on the first surface, wherein the third mask layer is provided with a sixth through hole; forming a fourth mask layer on the bottom and sidewall of the sixth through hole, wherein the fourth mask layer and the third mask layer are made of different materials; forming the gate trench and the first trench on the first surface, wherein the gate trench and the first trench penetrate the fourth mask layer and extend from the first surface into the semiconductor body; forming a fifth mask layer in the gate trench and the first trench; removing the fourth mask layer; forming a channel layer on the sidewalls of the transition well region, the gate trench, and the first trench; the channel layer is set to be of the first conductivity type; after forming the channel layer, the transition well region retained is used as a well region, and the transition first region retained is used as a first region; removing the third mask layer and the fifth mask layer; forming a first insulating layer in the gate trench; and forming a second insulating layer in the first trench; A filling layer is formed in the first trench on a side of the second insulating layer away from the semiconductor body.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: Forming a fourth mask layer on the bottom and sidewall of the sixth through hole includes: A fourth mask layer including silicon nitride is formed on the bottom and sidewalls of the sixth through hole.

11. The method for manufacturing a semiconductor device according to claim 8, wherein: The semiconductor body provided includes: A semiconductor body is provided which includes a silicon carbide semiconductor body or a gallium nitride semiconductor body.

12. A power module, characterized in that: The invention comprises a substrate and the semiconductor device according to any one of claims 1 to 7, wherein the substrate is used to support the semiconductor device.

13. A power conversion circuit, characterized in that: The power conversion circuit is used for one or more of current conversion, voltage conversion, and power factor correction; The power conversion circuit includes a circuit board and at least one semiconductor device according to any one of claims 1 to 7, wherein the semiconductor device is electrically connected to the circuit board.

14. A vehicle, characterized in that: It includes a load and the power conversion circuit as claimed in claim 13, wherein the power conversion circuit is used to convert AC power into DC power, convert AC power into AC power, convert DC power into DC power, or convert DC power into AC power and then input it into the load.

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