Semiconductor device and method of manufacturing the same

Abstract

The SiC substrate (10) is doped with vanadium. The high electron mobility transistor (20) is formed on the SiC substrate (10). The SiC substrate (10) has a first substrate (1) and a second substrate (2) formed on the first substrate (1). The vanadium concentration of the first substrate (1) is 1 * 1018 cm-3 or more. The vanadium concentration of the second substrate (2) at the interface between the second substrate (2) and the high electron mobility transistor (20) is 1 * 1017 cm-3 or less.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] In a high electron mobility transistor (HEMT), a SiC substrate into which a dopant such as vanadium is introduced to provide defects that impart semi-insulating characteristics is used (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application No. 2022-519825

[0004] In the HEMT manufacturing process, after semiconductor layers are deposited on a substrate, substrate warpage is minimal when the substrate is thick. However, as the substrate becomes thinner, the warpage increases to inappropriate levels. Doping SiC substrates with vanadium increases the elastic modulus, thereby reducing substrate warpage. However, increasing the vanadium concentration poses the problem of becoming a source of current collapse. Summary of the Invention

[0005] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same that can reduce the amount of substrate warpage while suppressing current collapse.

[0006] The semiconductor device of the present disclosure comprises: a SiC substrate doped with vanadium; and a high electron mobility transistor formed on the SiC substrate, wherein the SiC substrate comprises a first substrate and a second substrate formed on the first substrate, wherein the vanadium concentration of the first substrate is 1×10 18 cm －3 The vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is 1×10 17 cm －3 the following.

[0007] In the present disclosure, the vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is set to 1×10 17 cm －3 Below. Thus, the current collapse can be suppressed. In addition, although the vanadium concentration of the second substrate on the high electron mobility transistor side is reduced, by setting the vanadium concentration of the first substrate to 1×10 18 cm －3 As described above, the warping amount of the substrate can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a graph showing the vanadium concentration of the SiC substrate according to the first embodiment.

[0010] Figure 3 This is a graph showing the vanadium concentration of the SiC substrate according to the second embodiment.

[0011] Figure 4 This is a diagram comparing substrate warpage and current collapse in Embodiment 1 and Embodiment 2. DETAILED DESCRIPTION

[0012] A semiconductor device and a method for manufacturing the same according to the embodiments will be described with reference to the accompanying drawings. Identical or corresponding components are denoted by the same reference numerals, and redundant description may be omitted.

[0013] Implementation Method 1

[0014] Figure 1 1 is a cross-sectional view showing a semiconductor device according to Embodiment 1. A SiC substrate 10 is doped with vanadium. A GaN-HEMT 20 serving as a high electron mobility transistor is formed on the SiC substrate 10. The SiC substrate 10 includes a first substrate 1 and a second substrate 2 formed on the first substrate 1.

[0015] The GaN-HEMT 20 includes a nucleation layer 3, a high resistance layer 4, a channel layer 5, and an electron supply layer 6, which are sequentially stacked on a second substrate 2. The nucleation layer 3 is made of Al x1 Ga y1 In 1－x1－y1 N (0≤x1, y1≤1), with a thickness of 5 to 100 nm. The high resistance layer 4 is made of Al x2 Ga y2 In 1－x2－y2 N (0≤x2, y2≤1), with a thickness of 100 to 1000 nm. Fe, C, Mn, etc. are added to the high resistance layer 4. The impurity concentration of the high resistance layer 4 is 1E+17 to 1E+19 cm －3 The channel layer 5 is made of Al x3 Ga y3 In 1－x3－ y3 N (0≤x3, y3≤1), with a thickness of 100 to 1000 nm. The electron supply layer 6 is made of Al x4 Ga y4 In 1－x4－y4 The electron supply layer 6 has a structure of N (0≤x4, y4≤1) and a thickness of 1 to 50 nm. A gate electrode 7 , a source electrode 8 , and a drain electrode 9 are formed on the electron supply layer 6 .

[0016] Next, the method for manufacturing the semiconductor device according to Embodiment 1 is described. A first substrate 1 is manufactured by a sublimation method. Next, a second substrate 2 is manufactured on the first substrate 1 by a CVD method. In the CVD method, silicon sources such as SiCl4, SiH4, SiH3Cl, SiH2Cl2, SiHCl3, Si2H6, Si3H8, SiH3(CH3), and SiCl3(CH3) are used; carbon sources such as CH4 and C3H8 are used; vanadium sources such as VCl3 and V[N(CH3)2]4 are used; and carrier gases such as N2, H2, Ar, and He are used. The pressure is 5 to 100 kPa, and the temperature is 1000 to 1800°C.

[0017] Next, a nucleation layer 3, a channel layer 5, and an electron supply layer 6 are sequentially stacked on the second substrate 2. A gate electrode 7, a source electrode 8, and a drain electrode 9 are formed on the electron supply layer 6, thereby forming a GaN-HEMT 20. After the GaN-HEMT 20 is formed, the first substrate 1 in wafer form is ground and polished from the backside to thin it. The wafer is then divided into individual chips.

[0018] The thickness of the first substrate 1 is 300-500 μm before thinning and 10-50 μm after thinning. The thickness of the second substrate 2 is 10-50 μm. Therefore, the total film thickness of the SiC substrate 10 before thinning is 310-550 μm. Thinner than this total film thickness is prone to warping during the process, and thicker than this total film thickness increases costs. The total film thickness of the SiC substrate 10 after thinning is 20-100 μm.

[0019] Figure 2 This is a graph showing the vanadium concentration of the SiC substrate according to the first embodiment. The vanadium concentration of the first substrate 1 is constant at 1×10 18 cm -3 to 1×10 19 cm -3 On the other hand, the vanadium concentration of the second substrate 2 is constant at 0 to 1×10 17 cm -3 Thus, the vanadium concentration of the SiC substrate 10 varies in the thickness direction, but the average vanadium concentration of the SiC substrate 10 is 1×10 17 ~1×10 19 cm -3 .

[0020] The warpage amount h of a wafer formed by epitaxially growing a semiconductor layer on a substrate is expressed by the following equation.

[0021]

[0022] Here, tsub is the substrate thickness, tepi is the semiconductor layer thickness, Esub is the substrate elastic modulus, Eepi is the semiconductor layer elastic modulus, R is the wafer diameter, and εepi is the in-plane strain. This equation shows that increasing the substrate elastic modulus Esub can reduce the warpage h.

[0023] Since the bonding strength between vanadium and carbon is stronger than that between silicon and carbon, the elastic modulus of the SiC substrate 10 is increased by doping with vanadium. Table 1 shows the results of theoretical calculations of the vanadium concentration and warpage of the substrate of the semiconductor device according to the first embodiment after thinning. It can be seen that by setting the vanadium concentration of the first substrate 1 to 1×10 18 cm -3 As a result, the warping amount of the substrate is reduced.

[0024] [Table 1]

[0025] Vanadium concentration of the first substrate Vanadium concentration of the second substrate 2 t1 / t2 Warpage (normalized) 0 0 1 1 1E+18 5E+16 1 0.87 3E+1.8 5E+1.6 1 0.69

[0026] As described above, in this embodiment, the vanadium concentration at the interface between the second substrate 2 and the GaN-HEMT 20 is set to 1×10 17 cm -3 As a result, the current collapse can be suppressed. If the vanadium concentration of the second substrate 2 at the interface is set to 1×10 16 cm -3 Below, the current collapse can be further suppressed.

[0027] Furthermore, although the vanadium concentration of the second substrate 2 on the GaN-HEMT 20 side is reduced, the vanadium concentration of the first substrate 1 is set to 1×10 18 cm －3 As a result, the average vanadium concentration of the entire SiC substrate 10 can be set to 1×10 17 ~1×10 19 cm －3 This can reduce the warping of the substrate.

[0028] Furthermore, by manufacturing the second substrate 2 on the GaN-HEMT 20 side by CVD, defects such as threading dislocations in the second substrate 2 and the epitaxial layer of the GaN-HEMT 20 formed on the second substrate 2 can be suppressed.

[0029] Implementation Method 2

[0030] The semiconductor device according to the second embodiment differs from the first embodiment in how the vanadium concentration of the SiC substrate 10 changes in the thickness direction. Figure 3This is a graph showing the vanadium concentration of the SiC substrate according to the second embodiment. The vanadium concentration of the first substrate 1 is constant at 1×10 18 cm －3 to 1×10 19 cm －3 On the other hand, the vanadium concentration of the second substrate 2 is equal to that of the first substrate 1 at the interface between the first substrate 1 and the second substrate 2, and continuously decreases toward the GaN-HEMT 20. The change in the vanadium concentration of the second substrate 2 is not limited to a linear change like in Mode A; it can also change in a curved pattern like in Modes B and C. Mode B improves substrate warpage compared to Mode A, and Mode C improves current collapse compared to Mode A. Furthermore, the second substrate 2 is manufactured by CVD while reducing the vanadium raw material gas.

[0031] Table 2 shows the results of theoretical calculations of the vanadium concentration and warpage of the substrate of the semiconductor device according to the second embodiment after thinning.

[0032] [Table 2]

[0033]

[0034] As in the first embodiment, the vanadium concentration at the interface between the second substrate 2 and the GaN-HEMT 20 is set to 1×10 17 cm －3 Below. Thus, the current collapse can be suppressed. In addition, by setting the vanadium concentration of the first substrate 1 to 1×10 18 cm －3 As a result, the average vanadium concentration of the SiC substrate 10 can be set to 1×10 17 ~1×10 19 cm －3 This can reduce the warping of the substrate.

[0035] Figure 4 This figure compares substrate warpage and current collapse in Embodiment 1 and Embodiment 2. To achieve the same current collapse, the average vanadium concentration in the Si substrate of Embodiment 2 is higher than that of Embodiment 1. Therefore, Embodiment 2 can reduce substrate warpage.

[0036] Furthermore, in the second embodiment, since the vanadium concentration of the second substrate 2 is continuously changed, defects in the second substrate 2 and the epitaxial layer of the GaN-HEMT 20 can be reduced compared to the first embodiment.

[0037] Since the most common polytype of SiC substrates is 4H-SiC or 6H-SiC, in Embodiments 1 and 2, the polytype of the first substrate 1 is set to 4H-SiC or 6H-SiC for cost reasons. On the other hand, the polytype of the second substrate 2 on the GaN-HEMT side is preferably set to 3C-SiC due to its high thermal conductivity. This improves heat dissipation. 3C-SiC can be produced by modifying CVD conditions, such as adjusting the carrier gas flow rate or lowering the growth temperature.

[0038] Description of Reference Numerals

[0039] 1...first substrate; 2...second substrate; 3...nucleation layer; 4...high-resistance layer; 5...channel layer; 6...electron supply layer; 7...gate electrode; 8...source electrode; 9...drain electrode; 10...SiC substrate; 20...GaN-HEMT (high electron mobility transistor).

Claims

1. A semiconductor device, characterized in that: The semiconductor device comprises: A SiC substrate doped with vanadium; and A high electron mobility transistor is formed on the SiC substrate. The SiC substrate includes a first substrate and a second substrate formed on the first substrate. The vanadium concentration of the first substrate is 1×10 18 cm －3 above, The vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is 1×10 17 cm －3 the following.

2. The semiconductor device according to claim 1, wherein The vanadium concentration of the second substrate at the interface between the second substrate and the high electron mobility transistor is 1×10 16 cm －3 the following.

3. The semiconductor device according to claim 1 or 2, wherein: The average vanadium concentration of the SiC substrate is 1×10 17 ~1×10 19 cm －3 .

4. The semiconductor device according to any one of claims 1 to 3, wherein The vanadium concentration of the first substrate is 1×10 18 ~1×10 19 cm －3 .

5. The semiconductor device according to any one of claims 1 to 4, wherein The vanadium concentration of the second substrate is equal to the vanadium concentration of the first substrate at the interface between the first substrate and the second substrate, and continuously decreases toward the high electron mobility transistor.

6. The semiconductor device according to any one of claims 1 to 5, wherein The polytype of the first substrate is 4H-SiC or 6H-SiC, The polytype of the second substrate is 3C-SiC.

7. A method for manufacturing a semiconductor device, wherein the method is a method for manufacturing the semiconductor device according to any one of claims 1 to 6, characterized in that: The second substrate is manufactured by a CVD method.

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