Fast and slow clock frequency detection method and system suitable for MCU
By detecting the frequency of the high-frequency clock to be measured by a low-frequency scale clock, combined with the alternating switching of the counter and the frequency division shift signal, the problems of complex circuits and high costs in the existing technology are solved, and efficient and low-power clock frequency detection and scale clock loss monitoring are achieved.
Patent Information
- Application Number
- CN202410332932.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-03-22
- Publication Date
- 2025-09-23
AI Technical Summary
Existing technologies rely on high-precision reference clock sources, which results in complex circuit design, high cost, and difficulty in quickly detecting scale clock loss, leading to inaccurate system error diagnosis.
A low-frequency ruler clock is used to detect the frequency of the high-frequency clock to be tested. The frequency detection parameters are obtained through the AHB bus signal. The up and down counters are switched alternately, combined with the frequency division and shift signals to identify the clock edge. The counting threshold is dynamically calculated or read to monitor the clock frequency and ruler clock loss.
It simplifies circuit design, reduces power consumption, improves the accuracy of clock frequency detection and the efficiency of solving abnormal problems, and can quickly identify clock frequency anomalies and ruler clock loss.
Smart Images
Figure CN120685965A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a method and system for detecting fast and slow clock frequencies applicable to an MCU. Background Art
[0002] With the advancement of modern integrated circuit design technology and the improvement of digital chip manufacturing, the functions that chips can implement are becoming increasingly rich, and chips are playing an increasingly important role in society. An MCU (Microcontroller Unit) is an integrated circuit that contains a processor core, memory, and programmable input / output peripherals. Clock frequency detection involves measuring and monitoring the frequency of the clock signal in the MCU. This signal determines the operating speed of the processor and other system components.
[0003] Clock frequency directly impacts MCU performance. Accurate frequency detection helps optimize system performance and ensures the processor runs at optimal speed. Unstable or inaccurate clock frequency can cause system errors. Frequency detection is critical to ensuring stable system operation. Abnormal clock frequency can be an early sign of system failure. Monitoring frequency allows for quick diagnosis and resolution of potential issues.
[0004] The prior art generally adopts standard counter method or time interval measurement method to realize clock frequency detection.In these methods, pulse counting within a fixed time window or measuring the time interval between consecutive pulses is generally used to determine the frequency.
[0005] Existing technical solutions often rely on an external high-precision reference clock source and a microcontroller unit MCU or microprocessor to process data. The circuit design is complex, the power consumption is high, and the cost is high. Moreover, they do not take into account the situation where the scale clock fails. The system errors caused by this situation are diagnosed as errors in the clock to be tested, making it difficult to quickly resolve the abnormal problem. Summary of the Invention
[0006] In view of the above analysis, the embodiments of the present invention aim to provide a fast and slow clock frequency detection method and system suitable for MCU, so as to solve the problems of using a high-precision high-frequency clock as a scale clock and being unable to detect whether the scale clock is lost, resulting in complex circuit design and inaccurate problem location.
[0007] On the one hand, an embodiment of the present invention provides a method for detecting fast and slow clock frequencies of an MCU, comprising the following steps:
[0008] Receive AHB bus signals and obtain frequency detection parameters;
[0009] After receiving the enable signal, the scale clock is divided to obtain a divided clock signal;
[0010] At each rising edge of the clock to be measured, the divided clock signal is shifted to obtain a shift signal, the edge of the scale clock is identified according to the shift signal, and the two counter flags are switched alternately according to the change of the edge;
[0011] The corresponding frequency counter is reloaded according to the current counter flag. After the reloaded frequency counter obtains and loads the corresponding counting threshold according to the frequency detection parameter, it counts on the rising edge of the clock to be measured to obtain the actual counting value. When the counter flag is switched, it is identified whether a clock frequency error occurs based on the actual counting value. If so, the number of errors is accumulated. When the number of consecutive errors reaches the alarm threshold in the frequency detection parameter, an error message is output.
[0012] Based on the further improvement of the above method, when the actual count value of the frequency counter no longer changes, the monitoring counter is reloaded, and after obtaining and loading the corresponding monitoring threshold according to the frequency detection parameter, the monitoring counter counts on the rising edge of the clock to be measured to obtain the monitoring count value. When the monitoring count value has reached the monitoring threshold but the counter flag has not been switched, a scale clock error is generated and the number of errors is accumulated.
[0013] Based on a further improvement of the above method, the frequency counter includes an up counter and a down counter; the two counter flags are switched alternately according to the change of the edge, including: when it is the rising edge of the scale clock, switching to the down counter flag; when it is the falling edge of the scale clock, switching to the up counter flag.
[0014] Based on a further improvement of the above method, the actual count value is obtained by counting on the rising edge of the clock to be measured, including: when the down counter is overloaded, the actual count value is decremented one by one from the counting threshold of the down counter every time a rising edge of the clock to be measured passes. When the actual count value is decremented to 0, if the counter flag is not switched, the actual count value remains unchanged at 0.
[0015] Based on a further improvement of the above method, the actual count value is obtained by counting on the rising edge of the clock to be measured, including: when the up counter is overloaded, the actual count value is incremented one by one starting from 0 every time a rising edge of the clock to be measured passes. When the actual count value increases to the counting threshold of the up counter, if the counter flag is not switched, the actual count value remains unchanged at the counting threshold of the up counter.
[0016] According to a further improvement of the above method, when the switching counter flag is switched from the down counter flag to the up counter flag, if the actual count value is not 0, a clock frequency error indicating that the clock to be measured is too slow is generated.
[0017] According to a further improvement of the above method, when the counter flag is switched from the up counter flag to the down counter flag, if the actual count value has reached the count threshold of the up counter, a clock frequency error of the clock to be measured being too fast is generated.
[0018] Based on further improvement of the above method, the frequency detection parameters include: high frequency gear of the clock to be measured, low frequency gear of the scale clock, allowable error of the clock to be measured, allowable error of the scale clock, frequency division ratio of the clock to be measured and alarm threshold.
[0019] A further improvement based on the above method is to obtain the corresponding counting threshold / monitoring threshold according to the frequency detection parameters, including: when the high frequency gear of the clock to be measured and the low frequency gear of the scale clock in the frequency detection parameters are not custom parameters, the counting threshold of each of the two frequency counters and the monitoring threshold of the monitoring counter are calculated by the following formula; otherwise, the counting threshold of each of the two frequency counters and the monitoring threshold of the monitoring counter are directly read from the register:
[0020]
[0021] Among them, CNTMAX represents the counting threshold of the up counter, CNTMIN represents the counting threshold of the down counter, CNTSPY represents the monitoring threshold of the monitoring counter, and f FH Indicates the frequency after the clock to be measured is divided, f FL Indicates the frequency after the scale clock is divided, CK1ERR indicates the allowable error of the scale clock, and CK2ERR indicates the allowable error of the clock to be measured.
[0022] On the other hand, an embodiment of the present invention provides a fast and slow clock frequency detection system suitable for an MCU, comprising: a numerical controller, a frequency divider, a shift comparator, a counting controller, and an interrupt signal controller;
[0023] A numerical controller is used to receive AHB bus signals and obtain frequency detection parameters;
[0024] A frequency divider, configured to divide the scale clock to obtain a divided clock signal after receiving an enable signal;
[0025] A shift comparator is used to shift the divided clock signal at each rising edge of the clock to be measured to obtain a shift signal, identify the edge of the scale clock according to the shift signal, and alternately switch the two counting flags according to the change of the edge;
[0026] A counting controller is configured to reload the corresponding frequency counter according to the current counter flag. The reloaded frequency counter obtains and loads the corresponding counting threshold according to the frequency detection parameter of the numerical controller, and then counts at the rising edge of the clock to be measured to obtain the actual counting value. When the counter flag is switched, whether a clock frequency error occurs is identified based on the actual counting value. If so, the number of errors is accumulated.
[0027] The interrupt signal controller is used to output error information when the number of consecutive errors reaches the alarm threshold in the frequency detection parameter.
[0028] Compared with the prior art, the present invention can achieve at least one of the following beneficial effects:
[0029] 1. The counting threshold is calculated according to the preset parameter value through the AHB bus signal, or the preset counting threshold is directly read. It is easy to operate, has diversified functions, and can dynamically adapt to different needs;
[0030] 2. A low-frequency scale clock is used to detect the frequency of the high-frequency clock. At the same time, it can also monitor whether the low-frequency scale clock is lost, which is convenient for accurately locating errors and improving the efficiency of solving abnormalities. It also has a simple structure and low power consumption.
[0031] In the present invention, the above-mentioned technical solutions can be combined with each other to achieve more preferred combinations. Other features and advantages of the present invention will be described in the following description, and some advantages will become apparent from the description or be learned through practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the contents particularly pointed out in the description and drawings. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] The accompanying drawings are only for the purpose of illustrating particular embodiments and are not to be considered limiting of the present invention. Like reference symbols denote like parts throughout the drawings.
[0033] Figure 1 This is a flow chart of a method for detecting fast and slow clock frequencies of an MCU in Example 1 of the present invention;
[0034] Figure 2 This is a structural diagram of a fast and slow clock frequency detection system suitable for MCU in Example 2 of the present invention. DETAILED DESCRIPTION
[0035] The preferred embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, wherein the accompanying drawings constitute a part of this application and are used together with the embodiments of the present invention to illustrate the principles of the present invention, and are not used to limit the scope of the present invention.
[0036] Example 1
[0037] A specific embodiment of the present invention discloses a method for detecting the fast and slow clock frequencies of an MCU. Figure 1 As shown, the following steps are included:
[0038] S1. Receive AHB bus signals and obtain frequency detection parameters.
[0039] It should be noted that the frequency detection parameters in this embodiment include: the high frequency gear of the clock to be measured, the low frequency gear of the scale clock, the allowable error of the clock to be measured, the allowable error of the scale clock, the frequency division ratio of the clock to be measured and the alarm threshold.
[0040] Each parameter has multiple options. The high-frequency gear of the clock to be tested and the low-frequency gear of the scale clock support custom parameters. For example, the options for the high-frequency gear FH of the clock to be tested include custom parameters, 10M, 20M, and 40M; the options for the low-frequency gear FL of the scale clock include custom parameters, 10k, 20k, and 40k; the options for the allowable error CK1ERR of the scale clock and the allowable error CK2ERR of the clock to be tested include 0, 1 / 2, 1 / 4, 1 / 8, 1 / 16, etc.; the options for the division ratio FDR of the clock to be tested include 2, 4, and 8, etc.; the options for the alarm threshold TWARN include 5 times, 10 times, 15 times, and 20 times.
[0041] Preferably, the frequency detection parameter also includes a system clock selection flag SYSCLK, whose options include: scale clock and clock to be tested. The clock to be tested is selected as the system clock by default. When an error occurs in the clock to be tested, the scale clock can be temporarily switched to the system clock.
[0042] When performing fast and slow clock frequency detection, the AHB bus signal is received to obtain the frequency detection parameters and write them into the register. It should be noted that the ruler clock tolerance must be greater than or equal to the tolerance of the clock to be measured. If the ruler clock tolerance is less than the tolerance of the clock to be measured, the tolerance of the clock to be measured will overwrite the ruler clock tolerance.
[0043] S2. After receiving the enable signal, the scale clock is divided to obtain a divided clock signal.
[0044] It should be noted that when the enable signal is set to 1, frequency detection is started, and the scale clock is used as the clock pulse, and the divided clock signal is obtained by dividing the frequency by 2.
[0045] S3. Shift the divided clock signal at each rising edge of the clock to be measured to obtain a shift signal, identify the edge of the scale clock according to the shift signal, and alternately switch the two counter flags according to the change of the edge.
[0046] It should be noted that the divided clock signal passes through four connected triggers in sequence and triggers the shift at the rising edge of the clock to be measured. The shift signal {CAPT1, CAPT2, CAPT3, CAPT4} is obtained based on the four signals CAPT1, CAPT2, CAPT3 and CAPT4 generated.
[0047] When the shift signal {CAPT1, CAPT2, CAPT3, CAPT4} = 4'b1101, it is recognized as a rising edge of the low-frequency scale; when the shift signal {CAPT1, CAPT2, CAPT3, CAPT4} = 4'b0011, it is recognized as a falling edge of the low-frequency scale. 4'b indicates a 4-bit binary number.
[0048] It should be noted that in this embodiment, the speed of the clock being measured is determined using two frequency counters: an up counter and a down counter. The up counter detects whether the clock being measured is too fast, while the down counter detects whether it is too slow. Two counter flags are assigned to each frequency counter, and the two counter flags are switched alternately with the rising and falling edges of the scale clock. In other words, the counter flags change with the period of the low-frequency scale clock.
[0049] Specifically, when it is the rising edge of the scale clock, it switches to the down counter flag; when it is the falling edge of the scale clock, it switches to the up counter flag.
[0050] Exemplarily, when the flag is switched to a down counter, RELOAD=1 is set; when the flag is switched to an up counter, RECNT=1 is set.
[0051] S4. Reload the corresponding frequency counter according to the current counter flag. After the reloaded frequency counter obtains and loads the corresponding counting threshold from the frequency detection parameter, it counts on the rising edge of the clock to be measured to obtain the actual counting value. When the counter flag is switched, it is identified whether a clock frequency error occurs according to the actual counting value. If so, the number of errors is accumulated. When the number of consecutive errors reaches the alarm threshold in the frequency detection parameter, the error information is output.
[0052] It should be noted that the counting thresholds of the two frequency counters are controlled by the AHB bus signal in step S1 and are obtained in different ways in different situations.
[0053] Specifically, when the high-frequency gear of the clock to be measured and the low-frequency gear of the scale clock in the frequency detection parameters obtained according to the AHB bus signal are not custom parameters, the counting thresholds of the two frequency counters are calculated according to the frequency detection parameters; otherwise, the counting thresholds of the two frequency counters written in advance are directly read from the register.
[0054] Furthermore, the counting threshold CNTMAX of the up counter and the counting threshold CNTMIN of the down counter are calculated by the following formula:
[0055]
[0056] Among them, f FH Indicates the frequency after the clock to be measured is divided, that is, the frequency after the clock to be measured is divided according to the division ratio, f FL Indicates the frequency after the ruler clock is divided, that is, the frequency after division by 2. CK1ERR indicates the allowable error of the ruler clock, and CK2ERR indicates the allowable error of the clock to be measured.
[0057] It should be emphasized that formula (1) can be implemented using shift registers, which reduces the required computing resources.
[0058] Reloading the corresponding frequency counter according to the counter flag set in step S3 includes:
[0059] ① The down counter flag is currently set, so the down counter is reloaded and the down counter's count threshold, DNTMIN, is loaded. With each rising edge of the clock to be measured, the actual count value decrements from the down counter's count threshold. When the actual count value decrements to 0, if the counter flag is not switched, the actual count value remains at 0. When the down counter flag is switched to the up counter flag, if the actual count value is not 0, a clock frequency error indicating the clock to be measured is too slow is generated. dw_less_flag is set to 1, and the number of errors is accumulated. Otherwise, a clock frequency error indicating the clock to be measured is not too slow is not generated, and the number of consecutive errors is reset to zero.
[0060] ② The up counter flag is currently set, so the up counter is reloaded and the up counter's count threshold, DNTMAX, is loaded. With each rising edge of the clock to be measured, the actual count value increments from 0. When the actual count value reaches the up counter's count threshold, if the counter flag is not switched, the actual count value remains unchanged at the up counter's count threshold. When the up counter flag is switched to the down counter flag, if the actual count value has reached the up counter's count threshold, a clock frequency error indicating the clock to be measured is too fast is generated. The up_more_flag is set to 1, and the number of errors is accumulated. Otherwise, a clock frequency error indicating the clock to be measured is not too fast is generated, and the number of consecutive errors is reset to zero.
[0061] It should be emphasized that this embodiment not only uses the low-frequency scale clock to detect the frequency speed of the high-frequency clock, but also uses the monitoring counter to monitor whether the low-frequency scale clock is lost, so as to avoid the system error caused by this situation being diagnosed as a frequency error of the clock to be tested, and the abnormal problem cannot be correctly solved.
[0062] Specifically, when the high-frequency gear of the clock to be measured and the low-frequency gear of the scale clock in the frequency detection parameters obtained from the AHB bus signal are not custom parameters, the monitoring threshold of the monitoring counter is calculated according to the frequency detection parameters. Otherwise, the monitoring threshold CNTSPY of the monitoring counter written in advance is directly read from the register:
[0063]
[0064] It should be noted that when the actual count value of the down counter remains unchanged at 0, or the actual count value of the up counter remains unchanged at the count threshold of the up counter, the watchdog counter is reloaded and the count threshold CNTSPY of the watchdog counter is loaded. The watchdog count value increments from 0 with each rising edge of the clock to be measured. When the watchdog count value reaches the watchdog threshold but the counter flag has not been switched, a scale clock error occurs, spy_err_flag is set to 1, and the number of errors is accumulated. If the counter flag is switched before the watchdog count value reaches the watchdog threshold, the watchdog counter is reset. After the next reload, the watchdog count value starts counting from 0, and the number of consecutive errors is cleared to zero.
[0065] The generated clock frequency error (dw_less_flag) indicating the clock under test is too slow, the clock frequency error (up_more_flag) indicating the clock under test is too fast, and the scale clock error (spy_err_flag) are recorded. If the errors are discontinuous, the number of consecutive errors is reset to zero. When the number of consecutive errors reaches the alarm threshold in the frequency detection parameters, the recorded error information is output. After processing the error information, the three counters are reset as needed, the enable signal is re-issued, and steps S1-S4 are re-executed to detect whether the clock under test is too fast or too slow, and whether the scale clock is missing.
[0066] Compared with the prior art, the present embodiment provides a fast and slow clock frequency detection method suitable for MCU, which calculates the counting threshold according to the preset parameter value through the AHB bus signal, or directly reads the preset counting threshold. It is easy to operate, has diversified functions, and can dynamically adapt to different needs. It uses a low-frequency scale clock to detect the frequency speed of the high-frequency clock. At the same time, it can also monitor whether the low-frequency scale clock is lost, which is convenient for accurately locating errors and improving the efficiency of resolving anomalies. It also has a simple structure and low power consumption.
[0067] Example 2
[0068] Another embodiment of the present invention discloses a fast and slow clock frequency detection system applicable to MCU, thereby realizing a fast and slow clock frequency detection method applicable to MCU in embodiment 1. The specific implementation of each module refers to the corresponding description in embodiment 1. Figure 2 As shown, the system includes: a numerical controller, a frequency divider, a shift comparator, a counting controller and an interrupt signal controller.
[0069] A numerical controller, used for obtaining frequency detection parameters according to an AHB bus signal;
[0070] A frequency divider, configured to divide the scale clock CK1 to obtain a divided clock signal FD_CK1 after receiving an enable signal EN;
[0071] A shift comparator is used to shift the divided clock signal at each rising edge of the clock to be measured CK2 to obtain a shift signal, identify the edge of the scale clock according to the shift signal, and alternately switch the two counting flags according to the change of the edge;
[0072] A counting controller is configured to reload the corresponding frequency counter according to the current counter flag. The reloaded frequency counter obtains and loads the corresponding counting threshold according to the frequency detection parameter of the numerical controller, and then counts at the rising edge of the clock to be measured to obtain the actual counting value. When the counter flag is switched, whether a clock frequency error occurs is identified based on the actual counting value. If so, the number of errors is accumulated.
[0073] The interrupt signal controller is used to output error information when the number of consecutive errors reaches the alarm threshold in the frequency detection parameter.
[0074] It should be noted that the frequency counter in the counting controller includes an up counter and a down counter. During frequency detection, if the actual count value of the frequency counter stops changing, the monitoring counter is reloaded. After obtaining and loading the corresponding monitoring threshold based on the frequency detection parameters, the monitoring counter counts on the rising edge of the clock to be measured to obtain the monitoring count value. If the monitoring count value reaches the monitoring threshold but the counter flag has not been switched, a scale clock error is generated and the number of errors is accumulated.
[0075] exist Figure 2 In the interrupt signal controller, the three error signals dw_less_flag, up_more_flag, and spy_err_flag output by the counter controller are received. When the number of consecutive errors reaches the alarm threshold TWARN, up_more_flag is assigned to CK2_LOSS[0], dw_less_flag is assigned to CK2_LOSS[1], and spy_err_flag is assigned to CK1_LOSS. Finally, the CK1_LOSS and CK2_LOSS signals are output. In other words, CK1_LOSS is a one-bit scale loss signal, 1 indicates that the scale clock is lost, and 0 indicates that the scale clock is normal; CK2_LOSS is a two-bit frequency error signal, 00 indicates that the clock to be measured is normal, 01 indicates that the clock to be measured is too fast, and 10 indicates that the clock to be measured is too slow.
[0076] At the same time, when any one of CK1_LOSS and CK2_LOSS is 1, the interrupt signal FDINT is set to 1, indicating a clock error, and FDINT is output to interrupt the MCU.
[0077] Since this embodiment and the aforementioned method for detecting the fast and slow clock frequencies of an MCU can be mutually referenced, the description here is repeated and will not be repeated here. Since the principles of this system embodiment and the aforementioned method embodiment are the same, this system embodiment also has the corresponding technical effects of the aforementioned method embodiment.
[0078] Those skilled in the art will appreciate that all or part of the process steps of the above-described embodiments can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium, such as a magnetic disk, an optical disk, a read-only memory, or a random access memory.
[0079] The above description is only a preferred specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed in the present invention should be covered by the scope of protection of the present invention.
Claims
1. A method for detecting fast and slow clock frequencies of MCU, characterized in that: The following steps are involved: Receive AHB bus signals and obtain frequency detection parameters; After receiving the enable signal, the scale clock is divided to obtain a divided clock signal; shifting the divided clock signal at each rising edge of the clock to be measured to obtain a shift signal, identifying an edge of the scale clock according to the shift signal, and alternately switching two counter flags according to changes in the edge; The corresponding frequency counter is reloaded according to the current counter flag. After the reloaded frequency counter obtains and loads the corresponding counting threshold according to the frequency detection parameter, it counts on the rising edge of the clock to be measured to obtain the actual counting value. When the counter flag is switched, it is identified according to the actual counting value whether a clock frequency error occurs. If so, the number of errors is accumulated. When the number of consecutive errors reaches the alarm threshold in the frequency detection parameter, an error message is output.
2. The method for detecting fast and slow clock frequencies of an MCU according to claim 1, wherein: When the actual count value of the frequency counter no longer changes, the monitoring counter is reloaded, and after obtaining and loading the corresponding monitoring threshold according to the frequency detection parameter, the monitoring counter counts at the rising edge of the clock to be measured to obtain the monitoring count value. When the monitoring count value has reached the monitoring threshold but the counter flag has not been switched, a scale clock error is generated and the number of errors is accumulated.
3. The method for detecting fast and slow clock frequencies of an MCU according to claim 1 or 2, wherein: The frequency counter includes an up counter and a down counter; The two counter flags are switched alternately according to the change of the edge, including: when it is a rising edge of the scale clock, switching to the down counter flag; when it is a falling edge of the scale clock, switching to the up counter flag.
4. The method for detecting fast and slow clock frequencies of an MCU according to claim 3, wherein: The method of counting at the rising edge of the clock to be measured to obtain the actual count value includes: when the down counter is overloaded, the actual count value is gradually decreased from the count threshold of the down counter every time a rising edge of the clock to be measured passes, and when the actual count value is decreased to 0, if the counter flag is not switched, the actual count value remains unchanged at 0.
5. The method for detecting fast and slow clock frequencies of an MCU according to claim 3, wherein: The method of obtaining an actual count value by counting at the rising edge of the clock to be measured includes: when the up counter is overloaded, the actual count value is incremented one by one starting from 0 each time a rising edge of the clock to be measured passes; when the actual count value is incremented to the count threshold of the up counter, if the counter flag is not switched, the actual count value remains unchanged at the count threshold of the up counter.
6. The method for detecting fast and slow clock frequencies of an MCU according to claim 4, wherein: When the switching counter flag is switched from the down counter flag to the up counter flag, if the actual count value is not 0, a clock frequency error is generated indicating that the clock to be measured is too slow.
7. The method for detecting fast and slow clock frequencies of an MCU according to claim 5, wherein: When the switching counter flag is switched from the up counter flag to the down counter flag, if the actual count value has reached the count threshold of the up counter, a clock frequency error of the clock to be measured being too fast is generated.
8. The method for detecting fast and slow clock frequencies of an MCU according to claim 2, wherein: The frequency detection parameters include: the high frequency gear of the clock to be measured, the low frequency gear of the scale clock, the allowable error of the clock to be measured, the allowable error of the scale clock, the frequency division ratio of the clock to be measured and the alarm threshold.
9. The method for detecting fast and slow clock frequencies of an MCU according to claim 8, wherein: Obtaining the corresponding counting threshold / monitoring threshold according to the frequency detection parameter, including: when the high frequency gear of the clock to be measured and the low frequency gear of the scale clock in the frequency detection parameter are not custom parameters, calculating the counting threshold of each of the two frequency counters and the monitoring threshold of the monitoring counter by the following formula; otherwise, directly reading the counting threshold of each of the two frequency counters and the monitoring threshold of the monitoring counter from the register: Among them, CNTMAX represents the counting threshold of the up counter, CNTMIN represents the counting threshold of the down counter, CNTSPY represents the monitoring threshold of the monitoring counter, and f FH Indicates the frequency after the clock to be measured is divided, f FL Indicates the frequency after the scale clock is divided, CK1ERR indicates the allowable error of the scale clock, and CK2ERR indicates the allowable error of the clock to be measured.
10. A fast and slow clock frequency detection system suitable for MCU, characterized in that: include: Numerical controller, frequency divider, shift comparator, counting controller and interrupt signal controller; The numerical controller is used to receive the AHB bus signal and obtain the frequency detection parameter; The frequency divider is used to divide the scale clock to obtain a divided clock signal after receiving the enable signal; The shift comparator is configured to shift the divided clock signal at each rising edge of the clock to be measured to obtain a shift signal, identify the edge of the scale clock according to the shift signal, and alternately switch the two counting flags according to the change of the edge; The counting controller is configured to reload the corresponding frequency counter according to the current counter flag, the reloaded frequency counter obtaining and loading the corresponding counting threshold according to the frequency detection parameter of the numerical controller, and then counting at the rising edge of the clock to be measured to obtain an actual counting value. When the counter flag is switched, whether a clock frequency error occurs is identified according to the actual counting value, and if so, the number of errors is accumulated; The interrupt signal controller is used to output error information when the number of consecutive errors reaches the alarm threshold in the frequency detection parameter.