Chip verification method and device, equipment and storage medium

Abstract

The invention provides a chip verification method and device, equipment and a storage medium, and relates to the technical field of chip verification, and the method comprises the steps: determining a static time sequence analysis result corresponding to a to-be-verified chip; according to the static time sequence analysis result, determining a plurality of target time sequence paths of which the time sequence allowances meet a preset time sequence allowance condition from the time sequence paths corresponding to the to-be-verified chip; and based on the target time sequence path, in combination with a preset verification strategy, executing a verification operation on the to-be-verified chip, the preset verification strategy is a verification strategy constructed based on low-power-consumption verification, gate-level simulation verification and interface verification. In this way, the target time sequence path can be screened out according to the static time sequence analysis result and the time sequence margin, targeted verification operation can be performed on the to-be-verified chip based on the target time sequence path, and the chip verification efficiency is improved; and chip verification is carried out in combination with multiple verification strategies, so that the chip verification effect can be further improved.

Description

Technical Field

[0001] The present invention relates to the field of chip verification technology, and in particular to a chip verification method, device, equipment and storage medium. Background Art

[0002] Currently, commonly used post-chip verification methods rely primarily on single verification methods, such as static timing analysis (STA) or simulation verification. However, these methods have significant limitations when dealing with complex chip designs. For example, while STA can analyze timing issues, it cannot cover dynamic variations (such as clock jitter and power supply noise). While simulation verification can simulate chip behavior, it is inefficient and struggles to cover all scenarios.

[0003] It can be seen that how to optimize the efficiency of chip verification is a problem to be solved in this field. Summary of the Invention

[0004] The purpose of the embodiments of the present invention is to provide a chip verification method, apparatus, device, and storage medium, which can solve the problem that chip verification is inefficient and cannot cover all situations. To solve the above technical problems, the embodiments of the present invention provide a chip verification method, including:

[0005] Determine the static timing analysis results corresponding to the chip to be verified;

[0006] According to the static timing analysis result, determining a plurality of target timing paths whose timing margins meet preset timing margin conditions from the timing paths corresponding to the chip to be verified;

[0007] Based on the target timing path, and in combination with a preset verification strategy, a verification operation is performed on the chip to be verified; the preset verification strategy is a verification strategy constructed based on low power verification, gate-level simulation verification and interface verification.

[0008] In some embodiments, determining, based on the static timing analysis result, a plurality of target timing paths whose timing margins meet preset timing margin conditions from the timing paths corresponding to the chip to be verified includes:

[0009] Sort the timing paths according to the timing margins corresponding to the timing paths according to the static timing analysis results to obtain a path sequence;

[0010] Based on a preset timing margin condition, the path sequence is traversed in order of timing margin from low to high to determine a number of target timing paths that meet the preset timing margin condition; the preset timing margin condition is a condition set based on a fixed number or a fixed percentage.

[0011] In some embodiments, performing a verification operation on the chip to be verified includes:

[0012] Using a first target test case generated for the target timing path, and forcibly triggering the target timing path according to a preset asynchronous clock domain interaction scenario and a preset process angle, to verify whether the chip to be verified has a timing violation; the preset asynchronous clock domain interaction scenario is a scenario of synchronous operation of read and write pointers in a FIFO or a scenario of cross-clock domain signal transmission based on a handshake protocol;

[0013] Based on the state retention and isolation unit behavior of the power domain switching process, combined with the transient response of the real-time switching of voltage and frequency, and the leakage current of the shutdown area in the standby mode, a low-power verification operation is performed on the chip to be verified to verify the power consumption level of the chip to be verified; the isolation unit behavior includes high-level isolation, low-level isolation and last-value isolation, and the last-value isolation is characterized by maintaining the last valid level before the power domain is turned off;

[0014] Performing verification operations on the chip to be verified through a preset gate-level simulation verification strategy to verify the function and timing of the chip to be verified in the gate-level circuit design;

[0015] Based on the time constraint rules and signal interaction protocols corresponding to data transmission between the hard-core IP and the user-defined logic circuit, interface verification is performed on the chip to be verified.

[0016] In some embodiments, performing a verification operation on the chip to be verified using a preset gate-level simulation verification strategy includes:

[0017] Determining, from the register verification results corresponding to the chip to be verified, a plurality of second target test cases whose coverage meets a preset coverage condition;

[0018] In combination with the second target test case, gate-level delay, reset glitch and clock jitter, the chip to be verified performs a gate-level simulation verification operation.

[0019] In some embodiments, the method further comprises:

[0020] A verification operation is performed on the chip to be verified based on a scan chain, a memory built-in self-test, and a boundary scan.

[0021] In some embodiments, the method further comprises:

[0022] Use gate-level simulation coverage tools to identify untriggered logic cones and generate targeted test cases based on pre-set risk objects.

[0023] Performing a verification operation on the chip to be verified based on the directed test case;

[0024] Among them, the preset risk objects include timing or functional regression risks introduced by code modification operations corresponding to the chip to be verified, chip interface compatibility risks that have not been verified in actual projects, and risks related to historical chip verification.

[0025] In some embodiments, the method further comprises:

[0026] Sorting the test time corresponding to each test case used to perform the verification operation to obtain a corresponding test case sequence; the test time is the time taken for the corresponding test case to run from the beginning to the completion of the test;

[0027] Based on current computing resources and the preset verification time expectation related to the chip to be verified, the test cases in the test case sequence are screened to obtain a final target sequence, so as to use the test cases in the target sequence to perform verification operations on the chip to be verified.

[0028] In a second aspect, the present invention provides a chip verification device, comprising:

[0029] A timing analysis result determination module is used to determine the static timing analysis result corresponding to the chip to be verified;

[0030] A timing path determination module, configured to determine, based on the static timing analysis result, a plurality of target timing paths corresponding to the chip to be verified, whose timing margins meet a preset timing margin condition;

[0031] A verification module is used to perform a verification operation on the chip to be verified based on the target timing path and in combination with a preset verification strategy; the preset verification strategy is a verification strategy constructed based on low power verification, gate-level simulation verification and interface verification.

[0032] In a third aspect, the present invention provides an electronic device, comprising:

[0033] Memory for storing computer programs;

[0034] A processor is used to execute the computer program to implement the steps of the chip verification method as described above.

[0035] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the steps of the chip verification method described above are implemented.

[0036] It can be seen from the above technical solution that the present application first determines the static timing analysis results corresponding to the chip to be verified; then, based on the static timing analysis results, several target timing paths whose timing margins meet the preset timing margin conditions are determined from the timing paths corresponding to the chip to be verified; then, based on the target timing paths, verification operations can be performed on the chip to be verified in combination with a preset verification strategy; the preset verification strategy is a verification strategy constructed based on low-power verification, gate-level simulation verification, and interface verification. In this way, the present application can filter out the target timing paths based on the static timing analysis results and the timing margin, and can perform targeted verification operations on the chip to be verified based on the target timing paths, thereby improving chip verification efficiency; and combining multiple verification strategies for chip verification can further improve the chip verification effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the embodiments of the present invention, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0038] Figure 1 A flow chart of a chip verification method provided by an embodiment of the present invention;

[0039] Figure 2 A flow chart of a specific chip verification method provided by an embodiment of the present invention;

[0040] Figure 3 A schematic diagram of a chip verification device provided by an embodiment of the present invention;

[0041] Figure 4 A schematic diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0042] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0043] The terms "including" and "having," as used in the present description and accompanying drawings, and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements and may include steps or elements that are not listed.

[0044] In order to enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0045] like Figure 1 As shown, an embodiment of the present invention discloses a chip verification method, including:

[0046] Step S11: Determine the static timing analysis result corresponding to the chip to be verified.

[0047] It is understood that during static timing analysis, potential timing issues are identified by calculating chip circuit delays and timing margins. Furthermore, static timing analysis can only analyze static timing characteristics and cannot account for dynamic changes, such as clock jitter and power supply noise. In this embodiment, static timing analysis can be performed on the chip to be verified to determine the corresponding static timing analysis results. The timing analysis results can then be combined for further chip verification.

[0048] Step S12: determining, based on the static timing analysis result, a plurality of target timing paths whose timing margins meet a preset timing margin condition from the timing paths corresponding to the chip to be verified.

[0049] In an embodiment of the present application, the above steps can be used to determine the static timing analysis results corresponding to the chip to be verified. Combined with the static timing analysis results, the timing margin of each timing path can be understood, and further based on the timing margin, several target timing paths that meet the preset timing margin conditions can be determined from each timing path; for example, several timing paths with poor timing margins can be screened out.

[0050] In a specific embodiment, according to the static timing analysis result, determining a number of target timing paths whose timing margins meet a preset timing margin condition from the timing paths corresponding to the chip to be verified may include: sorting each of the timing paths according to the timing margins corresponding to the static timing analysis result to obtain a path sequence; traversing the path sequence in order of timing margins from low to high based on the preset timing margin condition to determine a number of target timing paths that meet the preset timing margin condition; the preset timing margin condition is a condition set based on a fixed number or a fixed percentage. Specifically, the static timing result corresponds to the timing margin of each timing path, and the timing paths can be sorted based on the timing margin to obtain a corresponding path sequence; it should be noted that the preset timing margin condition can be a condition set based on a fixed number, such as taking a certain number of timing paths with poor timing margins as target timing paths; or a condition set based on a fixed percentage, such as taking 20% ​​of the timing paths with poor timing margins of the total timing paths as target timing paths. Furthermore, based on a preset timing margin condition, the path sequence obtained by sorting based on the timing margin may be traversed to screen out a target timing path that meets the preset timing margin condition.

[0051] In a specific embodiment, taking into account the historical verification of chips of the same type, the potential risks of the current chip can be marked in combination with a machine learning algorithm to obtain corresponding marking results; then, the marking results and the corresponding static timing analysis results are combined to screen out the corresponding target timing path; in this way, by combining the algorithm and the historical verification of the chip, a more suitable target timing path can be screened out, thereby improving the subsequent chip verification effect.

[0052] Step S13: performing a verification operation on the chip to be verified based on the target timing path and in combination with a preset verification strategy; the preset verification strategy is a verification strategy constructed based on low power verification, gate-level simulation verification, and interface verification.

[0053] In an embodiment of the present application, the above steps can be combined with the static timing analysis results to determine several target timing paths; then targeted verification can be performed on the target timing paths. To further improve the verification coverage, verification operations on the chip to be verified can be performed in combination with pre-set verification strategies.

[0054] In a specific embodiment, performing a verification operation on the chip to be verified may include: utilizing a first target test case generated for the target timing path, and forcibly triggering the target timing path according to a preset asynchronous clock domain interaction scenario and a preset process angle to verify whether the chip to be verified has a timing violation; the preset asynchronous clock domain interaction scenario is a scenario of synchronous operation of read and write pointers in a FIFO (First Input First Output, a first-in-first-out data structure) or a scenario of cross-clock domain signal transmission based on a handshake protocol; performing a low-power verification operation on the chip to be verified to verify the power consumption level of the chip to be verified based on the state retention and isolation unit behavior of the power domain switching process, combined with the transient response of real-time voltage and frequency switching, and the leakage current of the shutdown region in standby mode; the isolation unit behavior includes high-level isolation, low-level isolation, and last-value isolation, wherein the last-value isolation represents maintaining the last valid level before the power domain is turned off; performing a verification operation on the chip to be verified using a preset gate-level simulation verification strategy to verify the function and timing of the chip to be verified in the gate-level circuit design; and performing a low-power verification operation on the chip to be verified based on the state retention and isolation unit behavior of the power domain switching process, combined with the transient response of real-time voltage and frequency switching, and the leakage current of the shutdown region in the standby mode. Interface verification of the chip to be verified is performed by analyzing the timing constraints and signal interaction protocols for data transmission between a design layout (i.e., a layout that has been completed with layout and routing and silicon-proven) and user-defined logic circuits. Specifically, test cases can be designed for the target timing path to force triggering of the target timing path to verify whether there are timing violations. Furthermore, verification can be combined with timing-sensitive scenarios, specifically asynchronous clock domain interaction scenarios, such as synchronous read and write pointer operations in a FIFO, or cross-clock domain information transmission based on a handshake protocol, to verify the functionality and timing of the metastable state processing circuit. Furthermore, process corners can be combined to verify the chip's behavior at nominal frequency, overclocking, and low-frequency power-saving modes. Furthermore, for low-power verification, state retention and isolation unit behavior during power domain switching can be verified. Isolation unit behavior includes high-level isolation, low-level isolation, and last-value isolation (maintaining the last valid level before the power domain was shut down). The transient response of real-time voltage and frequency switching is combined to ensure the absence of glitches or control signal contention. The leakage current of the shutdown region in standby mode meets expectations, achieving low-power verification of the chip to be verified. Furthermore, gate-level simulation is performed on the chip to observe the chip design's functionality and timing within the gate-level circuits and verify the design's robustness. Furthermore, interface verification specifically verifies the interface timing between the hard-core IP and user logic (data transmission timing constraints and signal interaction protocols), such as calibration signals and data alignment, to achieve interface verification of the chip under verification.It can be understood that, through the above verification process, the chip to be verified can be comprehensively verified, and the target timing path can be specifically verified, which can improve the verification efficiency.

[0055] In a specific embodiment, performing verification operations on the chip to be verified using a pre-set gate-level simulation verification strategy may include: determining several second target test cases whose coverage meets preset coverage conditions from the register verification results corresponding to the chip to be verified; and performing gate-level simulation verification operations on the chip to be verified in combination with the second target test cases, gate-level delays, reset glitches, and clock jitter. Specifically, during the gate-level simulation verification process, some test cases from the register verification results may be screened, such as those with complete coverage (covering a certain percentage) and high pass rates, with a focus on verifying consistency in the gate-level netlist. Furthermore, in the simulation environment, gate-level delays, reset glitches, or clock jitter may be simulated to observe the robustness of the chip design.

[0056] In a specific embodiment, the method may further include performing a verification operation on the chip to be verified based on a scan chain, a memory built-in self-test, and a boundary scan. Specifically, during the verification of the chip to be verified, the scan chain, the memory built-in self-test, and the boundary scan may be combined to ensure that the manufacturing test logic is correct.

[0057] In another specific embodiment, the process may further include: using a gate-level simulation coverage tool to identify untriggered logic cones, and generating targeted test cases based on preset risk targets; performing verification operations on the chip to be verified based on the targeted test cases; wherein the preset risk targets include timing or functional regression risks introduced by code modifications corresponding to the chip to be verified, chip interface compatibility risks not verified in actual projects, and risks related to historical chip verification. Specifically, during the chip verification process, the gate-level simulation coverage tool may be used to identify untriggered logic cones to supplement relevant targeted testing; and corresponding targeted test cases may also be generated for existing risk targets. It is understood that risk targets may specifically include timing or functional regression risks introduced by chip code modifications, chip interface compatibility risks not verified in actual projects, and inherent risks related to historical chip verification. Based on these situations, targeted targeted test cases may be generated to supplement the corresponding chip verification operations. It should be noted that during the chip verification process, test cases that failed in pre-simulation or formal verification may also be included in post-simulation verification to confirm the effectiveness of the chip repair.

[0058] In another specific embodiment, the method may further include: sorting the test time corresponding to each test case used to perform the verification operation to obtain a corresponding test case sequence; the test time is the time taken for the corresponding test case to run from the start to complete the test; based on the current computing resources and the preset verification time expectation related to the chip to be verified, the test cases in the test case sequence are filtered to obtain a final target sequence, so as to use the test cases in the target sequence to perform the verification operation on the chip to be verified. Specifically, during the chip verification process, the test run time corresponding to different test cases is different, that is, the time required from the start of the test case to the completion of the test; here, the test time corresponding to each test case can be considered to sort each test case to obtain a corresponding test case sequence; then, based on the real-time status of the current computing resources and the verification time expectation for the chip to be verified (the time requirement for the chip verification process), the test cases in the target sequence are filtered to obtain a final target sequence; and then the test cases in the target sequence are used to perform the verification operation on the chip to be verified. It is understandable that when screening test cases from the target sequence, priority can be given to test cases that can be completed in a short time. For example, according to the length of the test time, start selecting from the test cases with the shortest test time until the number of test cases finally screened reaches a certain threshold; the number of screened test cases is less than the number of test cases in the target sequence; in this way, a part of the test cases can be sacrificed, that is, part of the verification coverage can be sacrificed to ensure the verification operation of the core functions of the chip and improve the efficiency of the overall chip verification.

[0059] It can be seen from this that this application can filter out the target timing path based on the static timing analysis results and the timing margin. Based on the target timing path, targeted verification operations can be performed on the chip to be verified, thereby improving the chip verification efficiency. Moreover, combining multiple verification strategies for chip verification can further improve the chip verification effect. Compared with the commonly used single verification method, this application can combine the static timing analysis results to filter out high-value test cases, further combine multiple verification strategies, optimize the verification efficiency of the simulation, and ensure the design reliability before the chip is tape-out.

[0060] like Figure 2 As shown, an embodiment of the present invention discloses a chip verification method, which specifically includes:

[0061] In this embodiment, during the verification of the chip to be verified, the critical paths can first be screened based on static timing analysis, and timing-sensitive scenario verification can be performed. Specifically, the static timing analysis report can be used to screen out the 10% paths with the worst timing margins. Corresponding test cases can be designed for these timing paths to force these paths to trigger and verify whether there are timing violations (Setup / Hold Violations). In addition, all asynchronous clock domain interaction scenarios (such as FIFO pointer synchronization and handshake protocols) can be covered to verify the functionality and timing of metastable processing circuits (such as dual-flip-flop synchronizers). The chip's behavior at nominal frequency, overclocking, and low-frequency energy-saving modes can be verified under the process voltage temperature corner.

[0062] Furthermore, the chip's low-power verification can verify the state retention register and isolation cell behavior during power domain switching. Design use cases also cover transient response during real-time voltage and frequency switching, ensuring the absence of glitches or control signal contention. Furthermore, in standby mode, the leakage current in the shutdown region is verified to be consistent with expectations (this requires integration with power analysis tools).

[0063] Accordingly, you can choose to reuse pre-simulation use cases. Specifically, select use cases with complete coverage (code coverage + functional coverage > 95%) and a high pass rate from RTL-level verification (Register Transfer Level) and focus on verifying their consistency in the gate-level netlist (circuit description file). In the simulation environment, you can also simulate gate-level delay (SDF (Standard Delay Format, a standardized format, here refers to the corresponding format file) back-annotation), reset glitch (signal transition), or clock jitter to observe the robustness of the design.

[0064] Furthermore, for system-level and interface verification, the interface timing between the hard-core IP and the user logic (such as calibration signals and data alignment) can be verified; and the verification process can include scan chain testing, MBIST (MemoryBIST, memory built-in self-test) and boundary scan to ensure that the manufacturing test logic is correct.

[0065] It should be noted that risk-driven and regression testing can be performed during the chip verification process. Specifically, targeted tests can be designed for areas with design changes (Engineering Change Order, ECO), third-party IP used for the first time, or modules with historically high defect rates. In addition, all use cases that failed in pre-simulation or formal verification can be included in post-simulation to confirm the effectiveness of the repair.

[0066] To balance coverage and efficiency during chip verification, gate-level simulation coverage tools can be used to identify untriggered logic cones to supplement targeted testing. Furthermore, if resources are limited, priority can be given to running test cases that can be completed within a short timeframe (e.g., 24 hours), sacrificing some coverage while ensuring core functionality is verified. Examples of coverage identification tools include JasperGold (a formal verification platform) and VCS Coverage (Verilog CompilerSimulator Coverage, used to verify the functionality and performance of integrated circuit designs).

[0067] It should be noted that in specific embodiments, machine learning algorithms can be used to automatically classify and analyze relevant verification results to improve verification efficiency and accuracy. For example, in artificial intelligence chip design, optimizing the relevant chip verification process through machine learning algorithms can shorten verification time. In addition, verification scenarios can be further expanded based on specific scenarios, such as the special needs of automotive electronics, high temperature, low temperature, and high reliability. For example, verification tests in high and low temperature environments can be added to ensure the reliability of electronic chips under extreme conditions, and corresponding design defects can be discovered and repaired. Furthermore, given the low power consumption and high integration characteristics of IoT chips, low-power verification strategies can be adopted to ensure the normal operation of IoT chips in low-power mode. By optimizing the verification strategy, verification coverage can be improved.

[0068] As can be seen, this embodiment improves verification efficiency by screening paths with the worst timing margins and designing targeted test cases. Verification comprehensiveness is significantly enhanced by covering asynchronous clock domain interaction scenarios and behaviors under various process corners. Resource consumption is effectively controlled by prioritizing use cases that can be completed quickly. Design reliability is significantly improved by verifying state retention and isolation unit behavior during power island switching. Furthermore, verification strategies can be further adjusted for specific scenarios to achieve corresponding improvements in verification efficiency or coverage.

[0069] like Figure 3 As shown, an embodiment of the present invention discloses a chip verification device, including:

[0070] The timing analysis result determination module 11 is used to determine the static timing analysis result corresponding to the chip to be verified;

[0071] A timing path determination module 12 is configured to determine, based on the static timing analysis result, a plurality of target timing paths whose timing margins meet a preset timing margin condition from the timing paths corresponding to the chip to be verified;

[0072] The verification module 13 is used to perform a verification operation on the chip to be verified based on the target timing path and in combination with a preset verification strategy; the preset verification strategy is a verification strategy constructed based on low power verification, gate-level simulation verification and interface verification.

[0073] It can be seen from this that the present application can screen out the target timing path based on the static timing analysis results and the timing margin, and perform targeted verification operations on the chip to be verified based on the target timing path to improve the chip verification efficiency; and combining multiple verification strategies for chip verification can further improve the chip verification effect.

[0074] In a specific embodiment, the timing path determination module 12 may include:

[0075] a timing path sorting unit, configured to sort the timing paths according to the timing margins corresponding to the timing paths according to the static timing analysis results, to obtain a path sequence;

[0076] The timing path determination unit is used to traverse the path sequence in order of timing margin from low to high based on a preset timing margin condition to determine a number of target timing paths that meet the preset timing margin condition; the preset timing margin condition is a condition set based on a fixed number or a fixed percentage.

[0077] In a specific embodiment, the verification module 13 may include:

[0078] A first verification unit is configured to utilize a first target test case generated for the target timing path and forcibly trigger the target timing path according to a preset asynchronous clock domain interaction scenario and a preset process angle to verify whether the chip to be verified has a timing violation; the preset asynchronous clock domain interaction scenario is a scenario of synchronous operation of read and write pointers in a FIFO or a scenario of cross-clock domain signal transmission based on a handshake protocol;

[0079] A second verification unit is configured to perform a low-power verification operation on the chip to be verified to verify the power consumption level of the chip to be verified based on the state retention and isolation unit behavior of the power domain switching process, combined with the transient response of the real-time switching of the voltage and frequency, and the leakage current of the shutdown area in the standby mode; the isolation unit behavior includes high-level isolation, low-level isolation, and last-value isolation, wherein the last-value isolation represents the retention of the last valid level before the power domain is turned off;

[0080] A third verification submodule is configured to perform a verification operation on the chip to be verified by using a preset gate-level simulation verification strategy to verify the function and timing of the chip to be verified in the gate-level circuit design;

[0081] The fourth verification unit is used to perform interface verification on the chip to be verified based on the time constraint rules and signal interaction protocols corresponding to data transmission between the hard-core IP and the user-defined logic circuit.

[0082] In another specific embodiment, the third verification submodule may include:

[0083] A test case determination unit, configured to determine, from the register verification results corresponding to the chip to be verified, a plurality of second target test cases whose coverage meets a preset coverage condition;

[0084] The third verification unit is used to perform gate-level simulation verification operations on the chip to be verified in combination with the second target test case, gate-level delay, reset glitch and clock jitter.

[0085] In a specific embodiment, the device may further include:

[0086] The fifth verification submodule is configured to perform a verification operation on the chip to be verified based on a scan chain, a memory built-in self-test, and a boundary scan.

[0087] In a specific embodiment, the device may further include:

[0088] A test case generation module is used to identify untriggered logic cones using gate-level simulation coverage tools and generate targeted test cases based on pre-set risk objects.

[0089] The sixth verification sub-module is used to perform verification operations on the chip to be verified based on the directed test case; wherein, the preset risk objects include timing or functional regression risks introduced due to code modification operations corresponding to the chip to be verified, chip interface compatibility risks that have not been verified in actual projects, and risks related to historical chip verification.

[0090] In a specific embodiment, the device may further include:

[0091] A test case sorting module is used to sort the test time corresponding to each test case used to perform the verification operation to obtain a corresponding test case sequence; the test time is the time taken for the corresponding test case to run from the beginning to the completion of the test;

[0092] A test case screening module is used to screen the test cases in the test case sequence based on current computing resources and the preset verification time expectation related to the chip to be verified, so as to obtain a final target sequence, so as to use the test cases in the target sequence to perform verification operations on the chip to be verified.

[0093] Furthermore, the embodiment of the present application also discloses an electronic device, Figure 4 This is a structural diagram of an electronic device according to an exemplary embodiment. The content in the diagram should not be considered as any limitation on the scope of use of this application. The electronic device may specifically include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 is used to store a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the chip verification method disclosed in any of the aforementioned embodiments. In addition, the electronic device in this embodiment may specifically be an electronic computer.

[0094] In this embodiment, the power supply 23 is used to provide operating voltage for various hardware devices on the electronic device; the communication interface 24 can create a data transmission channel between the electronic device and external devices. The communication protocol it follows is any communication protocol that can be applied to the technical solution of this application and is not specifically limited here; the input and output interface 25 is used to obtain external input data or output data to the outside world. Its specific interface type can be selected according to specific application needs and is not specifically limited here.

[0095] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or CD, etc. The resources stored thereon can include an operating system 221, a computer program 222, etc., and the storage method can be temporary storage or permanent storage.

[0096] The operating system 221 is used to manage and control the hardware devices on the electronic device and the computer program 222, which can be Windows Server, NetWare, Unix, Linux, etc. In addition to including a computer program capable of performing the chip verification method performed by the electronic device disclosed in any of the aforementioned embodiments, the computer program 222 can further include computer programs capable of performing other specific tasks.

[0097] Furthermore, this application also discloses a computer-readable storage medium for storing a computer program; wherein, when executed by a processor, the computer program implements the aforementioned chip verification method. The specific steps of this method can be referred to the corresponding contents disclosed in the aforementioned embodiments and will not be repeated here.

[0098] Furthermore, the present application also discloses a computer program product, including a computer program / instruction, which implements the aforementioned chip verification method when executed by a processor.

[0099] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from the other embodiments. Reference can be made to the descriptions of the identical or similar parts between the various embodiments. For the devices disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and the relevant parts can be referred to the descriptions of the methods.

[0100] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0101] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0102] Finally, it should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the element.

[0103] The above is a detailed introduction to the technical solution provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for those skilled in the art, according to the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip verification method, characterized in that: include: Determine the static timing analysis results corresponding to the chip to be verified; According to the static timing analysis result, determining a plurality of target timing paths whose timing margins meet preset timing margin conditions from the timing paths corresponding to the chip to be verified; Based on the target timing path, and in combination with a preset verification strategy, a verification operation is performed on the chip to be verified; the preset verification strategy is a verification strategy constructed based on low power verification, gate-level simulation verification and interface verification.

2. The chip verification method according to claim 1, characterized in that: Determining, based on the static timing analysis result, a plurality of target timing paths whose timing margins meet preset timing margin conditions from the timing paths corresponding to the chip to be verified, includes: Sort the timing paths according to the timing margins corresponding to the timing paths according to the static timing analysis results to obtain a path sequence; Based on a preset timing margin condition, the path sequence is traversed in order of timing margin from low to high to determine a number of target timing paths that meet the preset timing margin condition; the preset timing margin condition is a condition set based on a fixed number or a fixed percentage.

3. The chip verification method according to claim 1, characterized in that: The performing a verification operation on the chip to be verified includes: Using a first target test case generated for the target timing path, and forcibly triggering the target timing path according to a preset asynchronous clock domain interaction scenario and a preset process angle, to verify whether the chip to be verified has a timing violation; the preset asynchronous clock domain interaction scenario is a scenario of synchronous operation of read and write pointers in a FIFO or a scenario of cross-clock domain signal transmission based on a handshake protocol; Based on the state retention and isolation unit behavior of the power domain switching process, combined with the transient response of the real-time switching of voltage and frequency, and the leakage current of the shutdown area in the standby mode, a low-power verification operation is performed on the chip to be verified to verify the power consumption level of the chip to be verified; the isolation unit behavior includes high-level isolation, low-level isolation and last-value isolation, and the last-value isolation is characterized by maintaining the last valid level before the power domain is turned off; Performing verification operations on the chip to be verified through a preset gate-level simulation verification strategy to verify the function and timing of the chip to be verified in the gate-level circuit design; Based on the time constraint rules and signal interaction protocols corresponding to data transmission between the hard-core IP and the user-defined logic circuit, interface verification is performed on the chip to be verified.

4. The chip verification method according to claim 3, characterized in that: The performing verification operation on the chip to be verified by using a preset gate-level simulation verification strategy includes: Determining, from the register verification results corresponding to the chip to be verified, a plurality of second target test cases whose coverage meets a preset coverage condition; In combination with the second target test case, gate-level delay, reset glitch and clock jitter, the chip to be verified performs a gate-level simulation verification operation.

5. The chip verification method according to claim 3, characterized in that: Also includes: A verification operation is performed on the chip to be verified based on a scan chain, a memory built-in self-test, and a boundary scan.

6. The chip verification method according to any one of claims 1 to 5, characterized in that: Also includes: Use gate-level simulation coverage tools to identify untriggered logic cones and generate targeted test cases based on pre-set risk objects. Performing a verification operation on the chip to be verified based on the directed test case; Among them, the preset risk objects include timing or functional regression risks introduced by code modification operations corresponding to the chip to be verified, chip interface compatibility risks that have not been verified in actual projects, and risks related to historical chip verification.

7. The chip verification method according to any one of claims 1 to 5, characterized in that: Also includes: Sorting the test times corresponding to the test cases used to perform the verification operation to obtain a corresponding test case sequence; The test time is the time taken from the start of the test to the completion of the test. Based on current computing resources and the preset verification time expectation related to the chip to be verified, the test cases in the test case sequence are screened to obtain a final target sequence, so as to use the test cases in the target sequence to perform verification operations on the chip to be verified.

8. A chip verification device, characterized in that: include: A timing analysis result determination module is used to determine the static timing analysis result corresponding to the chip to be verified; A timing path determination module, configured to determine, based on the static timing analysis result, a plurality of target timing paths corresponding to the chip to be verified, whose timing margins meet a preset timing margin condition; A verification module is used to perform a verification operation on the chip to be verified based on the target timing path and in combination with a preset verification strategy; the preset verification strategy is a verification strategy constructed based on low power verification, gate-level simulation verification and interface verification.

9. An electronic device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the chip verification method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of the chip verification method according to any one of claims 1 to 7.

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