Statistical timing characterization of superconducting electronic circuit designs

Abstract

The present disclosure describes systems and methods for generating a timing library. The device comprises a memory and a processor. The processor determines a condition indicating whether the superconducting electronic circuit design passes the logical verification or the logical verification fails, and determines a failure edge value for a timing parameter of the superconducting electronic circuit design. The processor simulates the superconducting electronic circuit design using the failure edge value of the timing parameter and the first process change to produce a first timing value for the superconducting electronic circuit design, and simulates the superconducting electronic circuit design using the failure edge value of the timing parameter and the second process change to produce a second timing value for the superconducting electronic circuit design, and generating a second time sequence value designed for the superconducting electronic circuit. The processor generates a timing library for the superconducting electronic circuit design based at least in part on the first timing value and the second timing value.

Description

[0001] Government licensing rights

[0002] This invention was made with support from the United States (U.S.) Government under Contract No. W911NF-17-9-0001, awarded by the Intelligence Advanced Research Projects Activity (IARPA) in the Office of the Director of National Intelligence through the U.S. Army Research Office. The U.S. Government has certain rights in this invention. Technical Field

[0003] The present disclosure relates to electronic design automation (EDA) systems. In particular, the present disclosure relates to statistical timing characterization of superconducting electronic circuit designs. Background Art

[0004] Superconducting electronic components or circuits can conduct electricity with zero resistance and, when cooled to a critical temperature (T c ) or less, the magnetic flux is expelled (Meissner effect). For example, T of niobium c It can be around 9.7 Kelvin (K), and circuits including niobium can have a nominal operating temperature of 4.2 K, which can be achieved by immersion in liquid helium. Timing characterization can be performed using timing data from timing libraries for digital logic circuits. However, these timing libraries may not exist and may not be easily generated for superconducting electronic components or circuits. Summary of the Invention

[0005] The present disclosure describes a system and method for generating a timing library. According to an embodiment, a device for generating a timing library for a superconducting electronic circuit design includes a memory and a processor communicatively coupled to the memory. The processor determines a condition indicating whether the superconducting electronic circuit design passes logic verification or fails logic verification, and determines a failure margin value of a timing parameter for the superconducting electronic circuit design based on the condition. The processor simulates the superconducting electronic circuit design using the failure margin value of the timing parameter and a first process variation to generate a first timing value for the superconducting electronic circuit design, and simulates the superconducting electronic circuit design using the failure margin value of the timing parameter and a second process variation to generate a second timing value for the superconducting electronic circuit design. The processor generates a timing library for the superconducting electronic circuit design based at least in part on the first timing value and the second timing value.

[0006] The processor can use the timing library to perform static timing analysis on superconducting electronic circuit designs.

[0007] The timing parameter may be the arrival time of a signal in a superconducting electronic circuit design, or the timing separation between competing conditions in a superconducting electronic circuit design.

[0008] Determining the margin of failure value may include determining whether the superconducting electronic circuit design meets the condition for different values ​​of the timing parameter.

[0009] Simulating the superconducting electronic circuit design to generate the first timing value and the second timing value can be part of a Monte Carlo simulation of the superconducting electronic circuit design.

[0010] The processor may set a range for the timing parameter, and determining a failure margin value for the timing parameter may include scanning within the range.

[0011] The processor may add margin to the first timing value and the second timing value.

[0012] According to another embodiment, a method for generating a timing library for a superconducting electronic circuit design includes: determining a condition indicating whether the superconducting electronic circuit design passes logic verification or fails logic verification; and determining, by a processor, a failure margin value for a timing parameter for the superconducting electronic circuit design based on the condition. The method also includes: simulating, by the processor, the superconducting electronic circuit design using the failure margin value for the timing parameter and a first process variation to generate a first timing value for the superconducting electronic circuit design; and simulating, by the processor, the superconducting electronic circuit design using the failure margin value for the timing parameter and a second process variation to generate a second timing value for the superconducting electronic circuit design. The method also includes generating a timing library for the superconducting electronic circuit design based at least in part on the first timing value and the second timing value.

[0013] The method may include performing static timing analysis for the superconducting electronic circuit design using the timing library.

[0014] The timing parameter may be the arrival time of a signal in a superconducting electronic circuit design, or the timing separation between competing conditions in a superconducting electronic circuit design.

[0015] Determining the margin of failure value may include determining whether the superconducting electronic circuit design meets the condition for different values ​​of the timing parameter.

[0016] Simulating the superconducting electronic circuit design to generate the first timing value and the second timing value can be part of a Monte Carlo simulation of the superconducting electronic circuit design.

[0017] The method may include setting a range for the timing parameter. Determining a failure margin value for the timing parameter may include scanning within the range.

[0018] The method may include adding margin to the first timing value and the second timing value.

[0019] According to another embodiment, a non-transitory computer-readable medium stores instructions for generating a timing library for a superconducting electronic circuit design. When the instructions are executed by a processor, the processor determines values ​​of timing parameters for the superconducting electronic circuit design and simulates the superconducting electronic circuit design using the values ​​of the timing parameters and a plurality of process variations to generate a plurality of timing values ​​for the superconducting electronic circuit design. The processor also generates the timing library for the superconducting electronic circuit design based on the plurality of timing values.

[0020] The processor can use the timing library to perform static timing analysis on superconducting electronic circuit designs.

[0021] The timing parameter may be the arrival time of a signal in a superconducting electronic circuit design, or the timing separation between competing conditions in a superconducting electronic circuit design.

[0022] Determining the value may include determining, for different values ​​of the timing parameter, whether the superconducting electronic circuit design satisfies a condition indicating whether the superconducting electronic circuit design passes logic verification or fails logic verification.

[0023] Simulating the superconducting electronic circuit design to generate the plurality of timing values ​​may be part of a Monte Carlo simulation of the superconducting electronic circuit design.

[0024] The processor may set a range for the timing parameter. Determining the value of the timing parameter may include scanning within the range. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present disclosure will be more fully understood from the detailed description of the embodiments of the present disclosure and the accompanying drawings given below. These drawings are intended to provide knowledge and understanding of the embodiments of the present disclosure and are not intended to limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0026] Figure 1A An example system for generating a timing library for superconducting electronic circuit designs is shown.

[0027] Figure 1B Shown in Figure 1A An example of determining and using failure margin values ​​in a system.

[0028] Figure 2 Shown Figure 1A An example sequential device in a system determines the failure edge value.

[0029] Figure 3 Shown Figure 1A An example timing device in a system determines the timing value.

[0030] Figure 4 Shown Figure 1A Generate a timing library based on the example timing devices in your system.

[0031] Figure 5 is Figure 1A Flowchart of an example method performed in a system.

[0032] Figure 6 Flowcharts depicting various processes used during the design and fabrication of integrated circuits according to some embodiments of the present disclosure.

[0033] Figure 7 A diagram depicts an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0034] Various aspects of the present disclosure relate to statistical timing characterization of superconducting electronic circuit designs. Timing characterization can be performed using timing data in a timing library. Timing characterization can allow circuit designers to understand whether an electronic circuit design will meet or violate timing requirements. For example, a timing library can indicate the delays introduced by various circuit elements. These delays can be used to determine the overall delay introduced by different elements in the circuit design. However, timing libraries for superconducting electronic elements or circuits may not exist, and their generation can be challenging.

[0035] The present disclosure describes a system for generating a timing library for superconducting electronic components or circuits. Typically, the system determines whether a superconducting electronic component or circuit will pass logic verification or fail logic verification while changing timing parameters (e.g., signal arrival times or timing separations between competing conditions). Through this process, the system uses an optimizer to determine a failure margin value for a timing parameter, wherein a slight increase or decrease in the failure margin value causes the logic verification of the superconducting electronic component or circuit to fail. The system then uses the failure margin value and various process variations to simulate the superconducting electronic component or circuit to generate timing values ​​for the superconducting electronic component or circuit. The system can then use the timing values ​​to generate a timing library.

[0036] In certain embodiments, the system provides several technical advantages. For example, the system allows for timing analysis (e.g., static timing analysis) to be performed on superconducting electronic components or circuits. Additionally, the system can probabilistically add margin when generating a timing library, which can prevent failures and improve the performance or yield of superconducting electronic components or circuits.

[0037] Figure 1A An example system 100 is shown. Figure 1A As shown, system 100 includes one or more devices 104, a network 106, and a timing device 108. In general, system 100 can be used to generate a timing library for a superconducting electronic circuit design. These timing libraries can then be used to perform timing analysis (e.g., static timing analysis) on the superconducting electronic circuit design or its components.

[0038] User 102 can use device 104 to interact with other elements of system 100 or control other elements of system 100. For example, user 102 can use device 104 to instruct timing device 108 to generate a timing library for a superconducting electronic circuit design. In addition, user 102 can use device 104 to provide a superconducting electronic circuit design to timing device 108. Device 104 is any suitable device for communicating with elements of system 100 via network 106. By way of example and not limitation, device 104 can be a computer, laptop, wireless or cellular phone, electronic notebook, personal digital assistant, tablet computer, or any other device capable of receiving, processing, storing information, or transmitting information to other elements of system 100. Network 106 is any suitable network operable to facilitate communication between elements of system 100.

[0039] The timing device 108 may be a computer system (e.g., Figure 7 The timing device 108 generates a timing library for the superconducting electronic circuit design. Typically, the timing device 108 simulates the superconducting electronic circuit design using different values ​​of the timing parameters to determine the failure margin values ​​of the timing parameters. The timing device 108 can then simulate the superconducting electronic circuit design using the failure margin values ​​and different process variations to generate timing values ​​for the superconducting electronic circuit design. The timing device 108 can then use the timing values ​​to generate a timing library. Figure 1A As shown in FIG, the timing device 108 includes a processor 110 and a memory 112. The processor 110 and the memory 112 can perform the actions or functions of the timing device 108 described herein. The processor 110 and the memory 112 can be Figure 7 7. The processing device 702 and memory 704 of the computer system 700 are shown in FIG.

[0040] The timing device 108 receives a superconducting electronic circuit design 114 from the device 104. The superconducting electronic circuit design 114 may include a superconducting electronic circuit or a superconducting electronic circuit element. The superconducting electronic circuit or the superconducting electronic circuit element may include a superconducting material (e.g., niobium) that conducts electricity with zero resistance. These circuits or circuit elements may be used in quantum devices or quantum computers. For example, the superconducting electronic circuit design 114 may include a Josephson junction, an adiabatic quantum flux parametron (AQFP) logic, a rapid single flux quantum (RSFQ) logic, an energy-efficient rapid single flux quantum (ERSFQ) logic, or a reciprocal quantum logic (RQL). Typically, the timing device 108 may analyze the superconducting electronic circuit design 114 to generate a timing library for the superconducting electronic circuit design 114.

[0041] The sequential device 108 may receive or establish a condition 116 for the superconducting electronic circuit design 114. The condition 116 may be used to determine whether the superconducting electronic circuit design 114 passes logic verification or fails logic verification. For example, if the sequential device 108 determines that the superconducting electronic circuit design 114 satisfies the condition 116, then the sequential device 108 may determine that the superconducting electronic circuit design 114 passes logic verification. On the other hand, if the sequential device 108 determines that the superconducting electronic circuit design 114 does not satisfy the condition 116, then the sequential device 108 may determine that the superconducting electronic circuit design 114 fails logic verification.

[0042] In some embodiments, the conditions 116 may specify a set of inputs and a set of expected outputs or intermediate signal values. During logic verification, the set of inputs may be provided to the superconducting electronic circuit design 114, and the outputs or intermediate signal values ​​of the superconducting electronic circuit design 114 may be compared with the expected outputs or intermediate signal values ​​in the conditions 116. If the outputs or intermediate signal values ​​match the expected outputs or intermediate signal values, then the superconducting electronic circuit design 114 may pass logic verification. If the outputs or intermediate signal values ​​do not match the expected outputs or intermediate signal values, then the superconducting electronic circuit design 114 may fail logic verification.

[0043] The timing device 108 may use different values ​​of the timing parameters to perform logic verification on the superconducting electronic circuit design 114. For example, the timing device 108 may change the value of the timing parameter while providing a set of inputs to the superconducting electronic circuit design 114. The timing device 108 may then determine whether the superconducting electronic circuit design 114 passes or fails logic verification at the different values ​​of the timing parameters.

[0044] The timing parameter may be any suitable parameter that affects timing within the superconducting electronic circuit design 114. For example, the timing parameter may be an arrival time of a signal in the superconducting electronic circuit design 114, or a timing separation between two signals in the superconducting electronic circuit design 114. As the timing device 108 simulates the superconducting electronic circuit design 114, the timing device 108 may vary the value of the timing parameter to determine which values ​​of the timing parameter cause the superconducting electronic circuit design 114 to pass or fail logic verification.

[0045] The timing device 108 can track the values ​​of the timing parameters and use these values ​​to track whether the superconducting electronic circuit design 114 passes or fails logic verification. The timing device 108 can analyze these results to determine a failure edge value 118 for the timing parameter. Typically, the failure edge value 118 is the value of the timing parameter near or on the boundary between the superconducting electronic circuit design 114 passing or failing logic verification. For example, a small or slight adjustment to the failure edge value 118 may cause the superconducting electronic circuit design 114 to fail logic verification. As a result, the failure edge value 118 for the timing parameter indicates the value of the timing parameter at which the superconducting electronic circuit design 114 is close to failing logic verification. In some embodiments, the timing device 108 can determine multiple failure edge values ​​118 for the timing parameter.

[0046] After the timing device 108 determines the failure margin value 118 of the timing parameter, the timing device 108 can use the failure margin value 118 and different process variations to simulate the superconducting electronic circuit design 114. Figure 1A In the example of FIG. 1 , timing device 108 begins simulation 120 of superconducting electronic circuit design 114 using failure margin values ​​118 of timing parameters and different process variations 122. Generally, process variations 122 may be changes or variations in the process used to create or produce superconducting electronic circuit design 114. For example, process variations 122 may change the thickness of layers in the fabrication and processing steps of processing superconducting electronic circuit design 114. In some embodiments, variations 122 may include changes or variations in bias conditions or temperature conditions.

[0047] Timing device 108 can perform simulation 120 as a Monte Carlo simulation to take advantage of variations in the process or conditions used to generate or produce superconducting electronic circuit design 114. In other words, simulation 120 can be a process-aware Monte Carlo simulation of superconducting electronic circuit design 114 along one or more failure margin values ​​118 of the timing parameters. Process variations 122 can be generated for different runs of the Monte Carlo simulation.

[0048] The timing device 108 can generate timing values ​​124 via simulation 120. For example, the timing device 108 can measure the timing values ​​124 in the superconducting electronic circuit design 114 during each simulation 120 of the superconducting electronic circuit design 114. The timing values ​​124 can measure any suitable timing characteristics of the superconducting electronic circuit design 114. For example, the timing values ​​124 can indicate the delay, slew rate, and single flux quantum (SFQ) pulse amplitude and pulse width in the superconducting electronic circuit design 114 under the failure edge value 118 of the timing parameter and different process variations 122. As a result, the simulation 120 can indicate the effect of different process variations 122 on the delay and slew rate in the superconducting electronic circuit design 114 at the failure edge value 118 of the timing parameter. The result can be a delay distribution in which each sample passes at the failure edge.

[0049] Figure 1B Shown in Figure 1A An example of determining and using the failure margin value 118 in the system 100 is shown. Figure 1B Two graphs 130 and 132 are shown. Graph 130 plots samples of the amount of time it takes for the output signal of a register or flip-flop to stabilize after a clock edge (clk2q) on the y-axis, and plots samples of the amount of time it takes for the input signal to arrive at the register or flip-flop before a clock edge (d2clk) on the x-axis. As shown in graph 130, when the input signal arrives too late (e.g., approximately 4 picoseconds after the clock edge), the register or flip-flop may not produce a correct output within that clock cycle. System 100 can determine a fail edge value 118 as the minimum d2clk value that still allows the register or flip-flop to produce a correct output value within the clock cycle. Furthermore, as shown in graph 130, fail edge value 118 is a sample at a typical-typical (TT) angle. The TT angle can indicate a process target for a superconducting electronic circuit design (e.g., a Josephson junction, an inductor, or a molybdenum cutoff and bias resistor at a critical temperature). Graph 132 illustrates that fail edge value 118 can be one of many samples that form a fail edge. As discussed later, the system 100 may use the distribution of failure margin values ​​to probabilistically add margin to the timing in the superconducting electronic circuit design 114 away from failure.

[0050] return Figure 1A, the timing device 108 can use the timing values ​​124 to generate a timing library 126 for the superconducting electronic circuit design 114. For example, the timing library 126 can include the timing values ​​124, the failure margin values ​​118 of the timing parameters, and the corresponding process variations 122. The timing device 108 or another device in the system 100 can use the timing library 126 to perform timing analysis (e.g., static timing analysis) on the superconducting electronic circuit design 114. In this manner, the timing device 108 generates the timing library 126 for the superconducting electronic circuit design 114 and allows timing analysis to be performed on the superconducting electronic circuit design 114.

[0051] Figure 2 Shown Figure 1A An example timing device 108 in the system 100. Typically, Figure 2 The timing device 108 is shown determining a failure margin value 118 for a timing parameter.

[0052] The timing device 108 begins by receiving a superconducting electronic circuit design 114. The superconducting electronic circuit design 114 may include a superconducting electronic circuit or a superconducting electronic circuit element. The superconducting electronic circuit or superconducting electronic circuit element may include a superconducting material (e.g., niobium) that allows the superconducting electronic circuit or superconducting electronic circuit element to conduct electricity with zero resistance and to be heated to a temperature that is lower than the critical temperature (T) when cooled to a critical temperature. c ) or lower. For example, the superconducting electronic circuit design 114 may include a Josephson junction, AQFP logic, RSFQ logic, ERSFQ logic, or RQL. In some embodiments, the superconducting electronic circuit design 114 is part of a quantum device or a quantum computer.

[0053] The timing device 108 may also receive a condition 116 indicating whether the superconducting electronic circuit design 114 passes logic verification or fails logic verification. If the condition 116 is met, the timing device 108 determines that the superconducting electronic circuit design 114 passes logic verification. If the condition 116 is not met, the timing device 108 determines that the superconducting electronic circuit design 114 fails logic verification. The condition 116 may include any suitable information. For example, the condition 116 may include a set of inputs and a set of expected outputs or expected intermediate signal values. When these inputs are provided to the superconducting electronic circuit design 114, if the superconducting electronic circuit design 114 produces the expected outputs or expected intermediate signal values, the superconducting electronic circuit design 114 is determined to pass logic verification. Otherwise, the superconducting electronic circuit design 114 is determined to have failed logic verification.

[0054] The timing device 108 may receive a timing parameter 202. The timing parameter 202 may indicate any aspect of timing within the superconducting electronic circuit design 114. For example, the timing parameter 202 may be an arrival time of a signal in the superconducting electronic circuit design 114, or a timing separation between two signals in the superconducting electronic circuit design 114. The timing device 108 may receive or establish a range 204 of values ​​for the timing parameter 202. The timing device 108 may scan the range 204 of the timing parameter 202 while simulating the superconducting electronic circuit design 114 to determine whether the superconducting electronic circuit design 114 satisfies the condition 116. For example, the timing device 108 may simulate the superconducting electronic circuit design 114 using different values ​​of the timing parameter 202 within the range 204 to see whether the superconducting electronic circuit design 114 satisfies the condition 116. Figure 2 In the example shown in FIG2 , the timing device 108 uses different values ​​of the timing parameter 202 within the range 204 to determine a result 206 of the logic verification. The result 206 indicates that the superconducting electronic circuit design 114 passes the logic verification using three different values ​​of the timing parameter 202, and fails the logic verification at another value of the timing parameter 202.

[0055] The timing device 108 analyzes the result 206 and the value of the timing parameter 202 to determine a failure margin value 118 for the timing parameter 202. Typically, the failure margin value 118 may be within a range 204. Alternatively, the failure margin value 118 may be a value of the timing parameter 202 at which the superconducting electronic circuit design 114 passes logic verification, but a small or slight adjustment to the failure margin value 118 causes the superconducting electronic circuit design 114 to fail logic verification. Thus, the failure margin value 118 for the timing parameter 202 is at the boundary or border between the superconducting electronic circuit design 114 passing logic verification and failing logic verification. In some embodiments, the timing device 108 includes or implements an optimizer that uses a bisection method to solve for the failure margin value 118. The optimizer may test midpoints in the range 204 as potential failure margin values ​​118 and then, depending on the results of the testing, halve the range 204. This process may continue until the optimizer locates the failure margin value 118. The timing device 108 may then use the failure margin value 118 during subsequent simulations of the superconducting electronic circuit design 114 .

[0056] Figure 3 Shown Figure 1A An example timing device 108 in the system 100. Typically, Figure 3The timing device 108 is shown determining a timing value 124. The timing device 108 simulates the superconducting electronic circuit design 114 using the failure margin value 118 and different process variations 122 to generate the timing value 124. For example, the timing device 108 may simulate the superconducting electronic circuit design 114 using the failure margin value 118 and a first process variation 122 to generate one or more timing values ​​124. The timing device 108 may then simulate the superconducting electronic circuit design 114 using the failure margin value 118 and a second process variation 122 to generate one or more timing values ​​124. In this manner, the timing device 108 simulates the superconducting electronic circuit design using the failure margin value 118 and different process variations 122 to generate the timing value 124. The process variations 122 may affect the process or conditions used to produce or manufacture the superconducting electronic circuit design 114. For example, the process variations 122 may affect the thickness of layers in the superconducting electronic circuit design 114. The simulation 120 may be part of a Monte Carlo simulation using different process variations 122. Thus, the simulation 120 may be part of a process-aware Monte Carlo simulation.

[0057] Timing values ​​124 can measure any suitable timing characteristic within superconducting electronic circuit design 114. For example, timing values ​​124 can be slew rates, SFQ pulse amplitudes and widths, or delays within superconducting electronic circuit design 114. Timing device 108 can measure timing values ​​124 during simulation 120. As a result, timing values ​​124 can represent different slew rates or delays that occur within superconducting electronic circuit design 114 at failure margin 118 and different process variations 122. Thus, simulation 120 reveals the effects of different process variations 122 on slew rates and delays within superconducting electronic circuit design 114 at failure margin 118. Timing device 108 can use timing values ​​124 to generate a timing library for superconducting electronic circuit design 114.

[0058] Figure 4 Shown Figure 1A An example timing device 108 in the system 100. Typically, Figure 4 The timing device 108 is shown using the timing values ​​124 to generate a timing library 126. The timing library 126 can then be used to perform timing analysis (eg, static timing analysis) on the superconducting electronic circuit design 114.

[0059] The timing device 108 can use the timing values ​​124 and the margins 402 to generate the timing library 126. As discussed above, the timing values ​​124 are generated using the failure edge values ​​118 of the timing parameters. As a result, the timing values ​​124 are generated using sampling at the failure edge of the superconducting electronic circuit design 114. The timing device 108 can introduce margins 402 to prevent failures. The timing device 108 can then use the margined timing values ​​to generate the timing library 126.

[0060] The timing device 108 can determine the margin 402 statistically or probabilistically. For example, the timing device 108 can determine how much timing slack is needed to fill the timing value 124 to prevent timing violations (e.g., setup and hold or race conditions). The timing device 108 can determine the average timing value and the distribution of timing values ​​that cause the superconducting electronic circuit design 114 to fail. The timing device 108 can then determine the standard deviation of the timing values ​​124. The timing device 108 can determine the margin 402 as the timing slack measure required to push a specific number of standard deviations (e.g., 4 standard deviations) away from failure. By adding the margin 402, the timing device 108 can ensure that there is sufficient timing slack without causing failure.

[0061] Figure 5 is Figure 1A Flowchart of an example method 500 performed in the system 100 of FIG. 1 . In certain embodiments, the timing device 108 performs the method 500. By performing the method 500, the timing device 108 generates the timing library 126 for the superconducting electronic circuit design 114.

[0062] At 502, the sequential device 108 determines a condition 116. The condition 116 may indicate whether the superconducting electronic circuit design 114 passes or fails logic verification. For example, the condition 116 may include a set of inputs and a set of expected outputs or expected intermediate signal values. When the inputs are provided to the superconducting electronic circuit design 114, if the superconducting electronic circuit design 114 produces the expected outputs or expected intermediate signal values, then the superconducting electronic circuit design 114 passes logic verification. If the superconducting electronic circuit design 114 does not produce the expected outputs or expected intermediate signal values, then the superconducting electronic circuit design 114 fails logic verification.

[0063] At 504, the timing device 108 determines the failure margin value 118 for the timing parameter 202. For example, the timing device 108 can simulate the superconducting electronic circuit design 114 while scanning the range 204 of values ​​for the timing parameter 202 to see whether the superconducting electronic circuit design 114 passes or fails logic verification. The timing device 108 can simulate the superconducting electronic circuit design 114 any suitable number of times for any suitable number of values ​​for the timing parameter 202. The timing device 108 can analyze the values ​​of the timing parameter 202 and the results 206 of the logic verification to determine the failure margin value 118 for the timing parameter 202. The failure margin value 118 can represent the value of the timing parameter 202 at which the superconducting electronic circuit design 114 is on the boundary or border between failing and passing logic verification. As a result, a slight adjustment or change to the failure margin value 118 for the timing parameter 202 can cause the superconducting electronic circuit design 114 to transition from passing logic verification to failing logic verification.

[0064] At 506, the timing device 108 simulates the superconducting electronic circuit design 114 using the failure margin value 118 and the different process variations 122 to generate timing values ​​124. The timing device 108 can simulate the superconducting electronic circuit design 114 using the failure margin value 118 and any suitable number of process variations 122. For example, the timing device 108 can simulate the superconducting electronic circuit design 114 using the failure margin value 118 and a first process variation 122 to generate one or more timing values ​​124. The timing device 108 can then simulate the superconducting electronic circuit design 114 using the failure margin value 118 and a second process variation 122 to generate one or more timing values ​​124. The timing device 108 can determine the different process variations 122 based on the Monte Carlo simulation. As a result, the simulation can be part of a process-aware Monte Carlo simulation of the superconducting electronic circuit design 114.

[0065] Timing value 124 can be a measure of any timing characteristic of superconducting electronic circuit design 114. For example, timing value 124 can be a slew rate or delay measured within superconducting electronic circuit design 114. Because failure edge value 118 is used during simulation, timing value 124 can be a distribution of timing values ​​124 at the failure edge of superconducting electronic circuit design 114. Simulation 120 can reveal the effects of different process variations 122 on the slew rate or delay of superconducting electronic circuit design 114 at the failure edge.

[0066] At 508, the timing device 108 uses the timing values ​​124 to generate a timing library 126 for the superconducting electronic circuit design 114. In some embodiments, the timing device 108 can introduce margin 402, or slack, to the timing values ​​124 when generating the timing library 126. By introducing slack or margin 402, the timing device 108 avoids mean failure and can ensure that the timing margin in the superconducting electronic circuit design 114 is sufficient. The timing device 108 or another device can use the timing library 126 to perform timing analysis (e.g., static timing analysis) on the superconducting electronic circuit design 114.

[0067] Figure 6 A set of example processes 600 are shown for transforming and verifying design data and instructions representing an article of manufacture, such as an integrated circuit, during the design, verification, and fabrication of the article of manufacture. Each of these processes can be structured and implemented as multiple modules or operations. The term "EDA" stands for "electronic design automation." The processes begin by creating a product concept 610 using information provided by a designer, transforming that information to create an article of manufacture using a set of EDA processes 612. When the design is finalized, the design is tape-out 634, which is when the artwork (e.g., geometric pattern) of the integrated circuit is sent to a fabrication facility to fabricate a mask set, which is then used to manufacture the integrated circuit. After tape-out, the semiconductor die 636 is processed, and packaging and assembly processes 638 are performed to produce the finished integrated circuit 640.

[0068] The specification of a circuit or electronic structure can range from low-level transistor material layout to a high-level description language. Circuits and systems can be designed using a high-level representation using a hardware description language (HDL), such as VHDL, Verilog, SystemVerilog, SystemC, MyHDL, or OpenVera. The HDL description can be transformed into a logic-level register transfer level (RTL) description, a gate-level description, a layout-level description, or a mask-level description. Each lower level of representation, being a more detailed description, adds more useful detail to the design description, for example, more detail for the module that comprises the description. The lower levels of representation, being a more detailed description, can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language for specifying a lower level of representation language that is a more detailed description is SPICE (Simulation Program for Integrated Circuits), which is used to describe circuits with many simulated elements in detail. The description of each level of representation is implemented for use by the corresponding system for that layer (e.g., a formal verification system). The design process can use Figure 6 The described process is implemented by an EDA product (or EDA system).

[0069] During system design 614, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical area and / or line of code area), cost reduction, etc. At this stage, the design can be partitioned into different types of modules or components.

[0070] During logic design and functional verification 616, modules or components in a circuit are specified in one or more descriptive languages ​​and the functional accuracy of the specifications is checked. For example, the components of a circuit can be verified to generate outputs that match the specifications of the circuit or system being designed. Functional verification can use simulators and other programs such as test bench generators, static HDL checkers, and formal verifiers. In some embodiments, specialized component systems called "simulators" or "prototyping systems" are used to accelerate functional verification.

[0071] During synthesis and design for test 618, the HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where the edges of the graph represent the elements of the circuit and the nodes of the graph represent how the elements are interconnected. Both the HDL code and the netlist are hierarchically structured artifacts that can be used by EDA products to verify that the integrated circuit performs according to the specified design during manufacture. The netlist can be optimized for the target semiconductor manufacturing technology. Additionally, the completed integrated circuit can be tested to verify that the integrated circuit meets the specification requirements.

[0072] During netlist verification 620, the netlist is checked for compliance with timing constraints and consistency with the HDL code. During design planning 622, the overall floor plan of the integrated circuit is constructed and analyzed for timing and top-level routing.

[0073] During layout or physical implementation 624, physical placement (positioning of circuit elements such as transistors or capacitors) and routing (connecting circuit elements by means of multiple conductors) are performed, and selection of cells from a library to implement a specific logic function may be performed. As used herein, the term "cell" may specify a group of transistors, other elements, and interconnects that provide a Boolean logic function (e.g., "and," "or," "not," "exclusive or") or a storage function (such as a flip-flop or latch). As used herein, a circuit "block" may refer to two or more cells. Both cells and circuit blocks may be referred to as modules or elements and are implemented as both physical structures and simulations. Parameters such as size are specified for the selected cell (based on a "standard cell") and made accessible in a database for use by EDA products.

[0074] During analysis and extraction 626, circuit functionality is verified at the layout level, which allows the layout design to be refined. During physical verification 628, the layout design is checked to ensure that manufacturing constraints (such as DRC constraints, electrical constraints, and lithography constraints) are correct and that the circuit functionality matches the HDL design specifications. During resolution enhancement 630, the layout geometry is transformed to improve the fabrication of the circuit design.

[0075] During tape-out, data is created for use in the production of lithographic masks (after applying lithographic enhancements, if appropriate).During mask data preparation 632, the "tape-out" data is used to generate lithographic masks, which are used to produce the finished integrated circuit.

[0076] Computer systems (such as Figure 7 The storage subsystem of the computer system 700) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as programs and data structures used by products used to develop units of the library and physical and logical designs that use the library.

[0077] Figure 7 An example computer system 700 is shown within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0078] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specifies actions to be taken by the machine. Further, while a single machine is shown, the term "machine" shall also be construed to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0079] The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM)), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 718 in communication with each other via a bus 730.

[0080] The processing device 702 represents one or more processors, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 702 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 702 may be configured to execute instructions 726 for performing the operations and steps described herein.

[0081] The computer system 700 may also include a network interface device 708 for communicating over a network 720. The computer system 700 may also include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), a graphics processing unit 722, a signal generating device 716 (e.g., a speaker), a graphics processing unit 722, a video processing unit 728, and an audio processing unit 732.

[0082] The data storage device 718 may include a machine-readable storage medium 724 (also referred to as a non-transitory computer-readable medium) having stored thereon one or more sets of instructions 726 or software embodying any one or more of the methodologies or functionality described herein. During execution of the instructions 726 by the computer system 700, the instructions 726 may also reside, completely or at least partially, within the main memory 704 and / or the processing device 702, which also constitute machine-readable storage media.

[0083] In some embodiments, the instructions 726 include instructions for implementing functions corresponding to the present disclosure. Although the machine-readable storage medium 724 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions executed by a machine and cause the machine and processing device 702 to perform any one or more of the methods of the present disclosure. Accordingly, the term "machine-readable storage medium" should include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0084] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are those requiring physical manipulation of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0085] It should be remembered, however, that all of these terms and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise specifically stated, it will be apparent from this disclosure that throughout this specification, it will be understood that certain terms refer to the actions and processes of computer systems or similar electronic computing devices that manipulate data represented as physical (electronic) quantities within the computer system's registers and memories and transform it into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0086] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, each coupled to a computer system bus, such as, but not limited to, any type of magnetic disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical card, or any type of medium suitable for storing electronic instructions.

[0087] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various other systems may be used together with the program according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be understood that the teachings of the present disclosure described herein may be implemented using various programming languages.

[0088] The present disclosure may be provided as a computer program product or software, wherein the computer program product or software may include a machine-readable medium having instructions stored thereon, which instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory (ROM), a random access memory (RAM), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0089] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the following claims. Where the present disclosure relates to some singular elements, more than one element may be depicted in the accompanying drawings, and the same elements may be marked with the same numbers. Accordingly, the present disclosure and the accompanying drawings should be regarded as illustrative, not restrictive.

Claims

1. A device for generating a timing library for superconducting electronic circuit design, the device comprising: Memory; as well as a processor communicatively coupled to the memory, the processor configured to: determining conditions indicating whether a superconducting electronic circuit design passes or fails logic verification; Determining a failure margin value of a timing parameter designed for the superconducting electronic circuit according to the condition; simulating the superconducting electronic circuit design using the failure margin value of the timing parameter and a first process variation to generate a first timing value for the superconducting electronic circuit design; simulating the superconducting electronic circuit design using the failure margin value of the timing parameter and a second process variation to generate a second timing value for the superconducting electronic circuit design; as well as A timing library for the superconducting electronic circuit design is generated based at least in part on the first timing value and the second timing value. 2 . The apparatus according to claim 1 , wherein the processor is further configured to: perform static timing analysis on the superconducting electronic circuit design using the timing library. 3 . The apparatus of claim 1 , wherein the timing parameter is a signal arrival time in the superconducting electronic circuit design, or a timing separation between competing conditions in the superconducting electronic circuit design.

4. The apparatus of claim 1 , wherein determining the failure margin value comprises: For different values ​​of the timing parameter, it is determined whether the superconducting electronic circuit design meets the condition. 5 . The apparatus of claim 1 , wherein simulating the superconducting electronic circuit design to generate the first timing value and the second timing value is part of a Monte Carlo simulation of the superconducting electronic circuit design. 6 . The apparatus of claim 1 , wherein the processor is further configured to set a range for the timing parameter, wherein determining the failure margin value of the timing parameter comprises scanning within the range. 7 . The apparatus of claim 1 , wherein the processor is further configured to add margin to the first timing value and the second timing value.

8. A method for generating a timing library for a superconducting electronic circuit design, the method comprising: determining conditions indicating whether a superconducting electronic circuit design passes or fails logic verification; The processor determines, according to the condition, a failure margin value of a timing parameter designed for the superconducting electronic circuit; simulating, by the processor, the superconducting electronic circuit design using the failure margin value of the timing parameter and a first process variation to generate a first timing value for the superconducting electronic circuit design; simulating, by the processor, the superconducting electronic circuit design using the failure margin value of the timing parameter and a second process variation to generate a second timing value for the superconducting electronic circuit design; as well as A timing library for the superconducting electronic circuit design is generated based at least in part on the first timing value and the second timing value.

9. The method according to claim 8, further comprising: Using the timing library, a static timing analysis is performed on the superconducting electronic circuit design.

10. The method of claim 8, wherein the timing parameter is a signal arrival time in the superconducting electronic circuit design, or a timing separation between competing conditions in the superconducting electronic circuit design.

11. The method of claim 8, wherein determining the failure margin value comprises: For different values ​​of the timing parameter, it is determined whether the superconducting electronic circuit design meets the condition.

12. The method of claim 8, wherein simulating the superconducting electronic circuit design to generate the first timing value and the second timing value is part of a Monte Carlo simulation of the superconducting electronic circuit design.

13. The method according to claim 8, further comprising: A range is set for the timing parameter, wherein determining the failure margin value of the timing parameter includes scanning within the range.

14. The method according to claim 8, further comprising: Margin is added to the first timing value and the second timing value.

15. A non-transitory computer-readable medium storing instructions for generating a timing library for a superconducting electronic circuit design, wherein when the instructions are executed by a processor, the processor: determining values ​​of timing parameters for a superconducting electronic circuit design; simulating the superconducting electronic circuit design using the value of the timing parameter and a plurality of process variations to generate a plurality of timing values ​​for the superconducting electronic circuit design; as well as A timing library designed for the superconducting electronic circuit is generated based on the plurality of timing values.

16. The medium of claim 15, wherein the processor further uses the timing library to perform static timing analysis on the superconducting electronic circuit design.

17. The medium of claim 15, wherein the timing parameter is a signal arrival time in the superconducting electronic circuit design, or a timing separation between competing conditions in the superconducting electronic circuit design.

18. The medium of claim 15, wherein determining the value comprises: For different values ​​of the timing parameter, it is determined whether the superconducting electronic circuit design satisfies a condition indicating whether the superconducting electronic circuit design passes logic verification or fails logic verification.

19. The medium of claim 15, wherein simulating the superconducting electronic circuit design to generate the plurality of timing values ​​is part of a Monte Carlo simulation of the superconducting electronic circuit design.

20. The medium of claim 15, wherein the processor further sets a range for the timing parameter, wherein determining the value of the timing parameter comprises scanning within the range.

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