Data carrying method and device, chip, storage medium and electronic equipment

Abstract

The invention discloses a data handling method and device, a chip, a storage medium and electronic equipment. The data handling method comprises the following steps: in response to a direct memory access controller, receiving a data handling trigger signal from a data node, and handling data between the direct memory access controller and the data node; counting the total data volume of the carried data; and in response to detecting that the receiving state of the direct memory access controller on the data transfer trigger signal is an abnormal state before the total data volume reaches the predetermined data volume, executing a data transfer ending operation. According to the embodiment of the invention, the direct memory access controller is prevented from being in a waiting state all the time, and the central processing unit does not need to continuously poll a state register in the direct memory access controller, so that the overhead of the central processing unit is reduced.

Description

Technical Field

[0001] The present disclosure relates to data transmission technology, and in particular to a data transport method, device, chip, storage medium and electronic device. Background Art

[0002] When using a Direct Memory Access (DMA) controller to move data, the controller will theoretically receive multiple trigger signals before the data transfer task is completed. If the controller does not receive any trigger signals for a long period before the data transfer task is completed, it will remain in a waiting state. In this case, the controller will not notify the CPU of the completion of the data transfer task. The CPU will then need to continuously poll the status register in the controller, which will incur significant CPU overhead. Summary of the Invention

[0003] In order to solve the above technical problems, the present disclosure provides a data transport method, device, chip, storage medium and electronic device.

[0004] According to one aspect of an embodiment of the present disclosure, a data transport method is provided, including: In response to a direct memory access controller receiving a data transfer trigger signal from a data node, transferring data between the direct memory access controller and the data node; Counting the total amount of the data that has been moved; In response to detecting that the direct memory access controller receives the data transfer trigger signal in an abnormal state before the total data amount reaches a predetermined data amount, a data transfer end operation is executed.

[0005] According to another aspect of an embodiment of the present disclosure, there is provided a data handling device, comprising: a transport module, configured to transport data between the direct memory access controller and the data node in response to the direct memory access controller receiving a data transport trigger signal from the data node; A statistics module, configured to count the total amount of the data moved by the moving module; The execution module is configured to execute a data transfer end operation in response to detecting that the direct memory access controller receives the data transfer trigger signal in an abnormal state before the total data amount counted by the statistics module reaches a predetermined data amount.

[0006] According to another aspect of the embodiments of the present disclosure, a chip is provided, including: Data node, used to generate data transfer trigger signals; A direct memory access controller is configured to, in response to receiving the data transfer trigger signal from the data node, transfer data between the direct memory access controller and the data node, and to count a total amount of the transferred data; and, in response to detecting that a reception status of the direct memory access controller in response to the data transfer trigger signal is abnormal before the total amount of data reaches a predetermined amount, execute a data transfer termination operation.

[0007] According to another aspect of the embodiments of the present disclosure, a computer-readable storage medium is provided, wherein the storage medium stores a computer program, and the computer program is executed by a processor to perform the above-mentioned data transport method.

[0008] According to another aspect of the embodiments of the present disclosure, an electronic device is provided, the electronic device including: processor; a memory for storing instructions executable by the processor; The processor is used to read the executable instructions from the memory and execute the instructions to implement the above-mentioned data transfer method.

[0009] According to another aspect of the embodiments of the present disclosure, a computer program product is provided. When instructions in the computer program product are executed by a processor, the above-mentioned data transport method is performed.

[0010] Based on the data transfer method, device, chip, storage medium, electronic device and program product provided by the above embodiments of the present disclosure, when the direct memory access controller receives a data transfer trigger signal from a data node, data can be transferred between the direct memory access controller and the data node. Theoretically, before the total amount of data transferred between the direct memory access controller and the data node reaches a predetermined amount of data, the direct memory access controller will receive a data transfer trigger signal from the data node at regular intervals, and the time interval between two adjacent receptions of the data transfer trigger signal is within the allowed time range. If the direct memory access controller receives the data transfer trigger signal in an abnormal state, this indicates that the direct memory access controller did not receive the data transfer trigger signal from the data node as expected before the predetermined amount of data was transferred between the direct memory access controller and the data node. This is obviously inconsistent with the theoretical situation, and it can be inferred that there is an abnormality in the data node. For example, the abnormal situation may be that the data node is hung. In the case of an abnormality in the data node, a data transfer termination operation can be performed, for example, the data transfer task can be terminated. This helps avoid the direct memory access controller being in a waiting state all the time. The direct memory access controller can notify the central processor that the data transfer task is completed. Accordingly, the central processor does not need to constantly poll the status register in the direct memory access controller, which helps reduce the overhead of the central processor. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a system architecture diagram applicable to the embodiments of the present disclosure.

[0012] Figure 2 This is one of the flow charts of the data handling method provided by some exemplary embodiments of the present disclosure.

[0013] Figure 3 is a schematic diagram of handshake communication between a data source node and a direct memory access controller in some exemplary embodiments of the present disclosure.

[0014] Figure 4 is a schematic diagram of handshake communication between a direct memory access controller and a data destination node in some exemplary embodiments of the present disclosure.

[0015] Figure 5 This is the second flowchart of the data transfer method provided by some exemplary embodiments of the present disclosure.

[0016] Figure 6 This is the third flow chart of the data transfer method provided by some exemplary embodiments of the present disclosure.

[0017] Figure 7This is the fourth flow chart of the data transfer method provided by some exemplary embodiments of the present disclosure.

[0018] Figure 8 This is the fifth flow chart of the data transfer method provided by some exemplary embodiments of the present disclosure.

[0019] Figure 9 This is the sixth flowchart of the data transfer method provided by some exemplary embodiments of the present disclosure.

[0020] Figure 10-1 This is the seventh flow chart of the data transfer method provided by some exemplary embodiments of the present disclosure.

[0021] Figure 10-2 This is the eighth flow chart of the data transfer method provided by some exemplary embodiments of the present disclosure.

[0022] Figure 11 This is one of the structural diagrams of the data handling device provided by some exemplary embodiments of the present disclosure.

[0023] Figure 12 This is the second structural schematic diagram of the data handling device provided by some exemplary embodiments of the present disclosure.

[0024] Figure 13 It is a structural diagram of a determination module in a data handling device provided by some exemplary embodiments of the present disclosure.

[0025] Figure 14 It is a structural diagram of a first control module in a data handling device provided by some exemplary embodiments of the present disclosure.

[0026] Figure 15 This is one of the structural diagrams of the execution module in the data handling device provided by some exemplary embodiments of the present disclosure.

[0027] Figure 16 This is the second structural diagram of the execution module in the data handling device provided by some exemplary embodiments of the present disclosure.

[0028] Figure 17 It is a schematic diagram of the structure of a chip provided by some exemplary embodiments of the present disclosure.

[0029] Figure 18 is a schematic structural diagram of an electronic device provided by some exemplary embodiments of the present disclosure. DETAILED DESCRIPTION

[0030] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0031] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0032] Application Overview Currently, the application of chips is becoming more and more extensive. For example, in the field of driving technology, the application of smart driving chips and smart cockpit chips is becoming more and more widespread.

[0033] It is understandable that the direct memory access controller is the key hardware in the chip for achieving efficient data transmission. The direct memory access controller can perform data transfer tasks, so there is no need for the central processing unit to perform all data transfer tasks, which helps reduce the overhead of the central processing unit.

[0034] In the process of implementing the present disclosure, the inventors discovered that when using a direct memory access controller to transfer data, the direct memory access controller will theoretically receive data transfer trigger signals multiple times before the data transfer task is completed. If the direct memory access controller does not actually receive the data transfer trigger signal for a long period of time before the data transfer task is completed, the direct memory access controller will remain in a waiting state. In this case, the direct memory access controller cannot notify the central processing unit (CPU) of the completion of the data transfer task, nor can it notify the CPU to process the transferred data. The CPU needs to continuously poll the status register in the direct memory access controller to process the transferred data based on the information stored in the status register. This will incur significant CPU overhead, which is contrary to the original intention of reducing CPU overhead by introducing the direct memory access controller.

[0035] Exemplary Systems Figure 1 This is a system architecture diagram applicable to the embodiments of the present disclosure, including a data source node, a direct memory access controller and a data destination node; wherein the direct memory access controller can obtain data from the data source node and store it in a cache inside the direct memory access controller, and the direct memory access controller can also take out the data in the cache and write it to the data destination node.

[0036] Alternatively, a data source node can be understood as a node within a chip that generates or provides data. Examples of data source nodes include a Universal Asynchronous Receiver / Transmitter (UART) or Static Random Access Memory (SRAM). A data source node can also be referred to as a source end or source terminal.

[0037] Alternatively, a data destination node can be understood as a node in a chip responsible for receiving data and performing further processing on the received data. Examples of further processing include storage processing, transmission processing, and computational processing. Examples of data destination nodes include Double Data Rate Synchronous Dynamic Random Access Memory (DDR), an audio bus, and computational circuits. A data destination node can also be referred to as a destination end or destination terminal.

[0038] Exemplary Methods Figure 2 It is a flowchart of a data handling method provided by some exemplary embodiments of the present disclosure. Figure 2 The method shown can be applied, for example, to a direct memory access controller. Figure 2 The illustrated method may include step 210 , step 220 , and step 230 .

[0039] Step 210 : In response to the direct memory access controller receiving a data transfer trigger signal from the data node, data is transferred between the direct memory access controller and the data node.

[0040] Optionally, the data nodes involved in step 210 include Figure 1 The data source node shown, and / or including Figure 1 The data destination node is shown.

[0041] If the data node involved in step 210 is a data source node, the data source node may send a data transfer trigger signal to the direct memory access controller. The data transfer trigger signal may be represented as follows: Figure 3 DMA_RX_REQ shown. Upon receiving a data transfer trigger signal from a data source node, the direct memory access controller can read a preset amount of data from the data source node and transfer the read data to a cache within the direct memory access controller; the preset amount of data can be a pre-set single transfer amount of data, such as 1 byte, 4 bytes, etc. In an optional example, the data source node can be a Universal Asynchronous Receiver / Transmitter (UART), and the data read by the direct memory access controller from the data source node can be Global Positioning System (GPS) positioning data.

[0042] If the data node involved in step 210 is a data destination node, the data destination node may send a data transfer trigger signal to the direct memory access controller. The data transfer trigger signal may be represented as follows: Figure 4 DMA_TX_REQ shown. Upon receiving a data transfer trigger signal from a data destination node, the direct memory access controller may transfer a preset amount of data in a cache within the direct memory access controller to the data destination node. In an optional example, the data destination node may be an audio bus, and the data transferred by the direct memory access controller to the audio bus may be audio data.

[0043] Step 220: Count the total amount of data that has been transferred.

[0044] Optionally, the amount of data moved can be accumulated based on the amount of data (e.g., a preset amount of data) moved by the direct memory access controller in response to a received data transfer trigger signal and the number of transfers by the direct memory access controller, thereby recording the total amount of data moved.

[0045] Step 230 , in response to detecting that the direct memory access controller receives the data transfer trigger signal in an abnormal state before the total data amount reaches the predetermined data amount, executing a data transfer end operation.

[0046] Optionally, the predetermined data volume can be the total amount of data that should theoretically be transferred between the DMA controller and the data node for this data transfer task. The predetermined data volume can be configured, for example but not limited to, in a register or linked list of the DMA controller by the central processing unit. Whether the total data volume reaches the predetermined data volume is determined by comparing the total data volume with the predetermined data volume.

[0047] Optionally, the direct memory access controller may have two states of reception of a data transfer trigger signal: a normal state and an abnormal state. If, before the data transfer of a predetermined amount of data is completed between the direct memory access controller and the data node, the direct memory access controller receives a data transfer trigger signal from the data node at regular intervals, and the time interval between two adjacent receptions of the data transfer trigger signal is within an allowed time range, it can be determined that the direct memory access controller is in a normal state of reception of the data transfer trigger signal. If, before the data transfer of a predetermined amount of data is completed between the direct memory access controller and the data node, after the last reception of the data transfer trigger signal from the data node, the direct memory access controller fails to receive a data transfer trigger signal from the data node again within an allowed time range, it can be determined that the direct memory access controller is in an abnormal state of reception of the data transfer trigger signal.

[0048] Optionally, executing the data transfer end operation may be understood as ending the current data transfer task. As an example, the direct memory access controller may notify the central processing unit that the data transfer task is ended.

[0049] In an embodiment of the present disclosure, when a direct memory access controller receives a data transfer trigger signal from a data node, data can be transferred between the direct memory access controller and the data node. Theoretically, before the total amount of data transferred between the direct memory access controller and the data node reaches a predetermined amount, the direct memory access controller will receive data transfer trigger signals from the data node at regular intervals, and the time interval between two consecutive data transfer trigger signal receptions is within an allowable time range. If the direct memory access controller's reception status of the data transfer trigger signal is abnormal, this indicates that the direct memory access controller did not receive the data transfer trigger signal from the data node as expected before the predetermined amount of data transfer between the direct memory access controller and the data node was completed. This is obviously inconsistent with the theoretical situation, and it can be inferred that there is an abnormality in the data node, for example, the abnormality may be that the data node is hung. In the event of an abnormality in the data node, a data transfer termination operation can be executed, for example, the current data transfer task can be terminated. This helps avoid the direct memory access controller being in a waiting state. The direct memory access controller can notify the central processor of the end of the data transfer task. Accordingly, the central processor does not need to continuously poll the status register in the direct memory access controller, thereby helping to reduce the CPU's overhead.

[0050] In some optional examples, before the total data volume reaches a predetermined data volume, such as Figure 5 As shown, the method provided by the embodiment of the present disclosure may further include step 510 , step 520 and step 530 .

[0051] Step 510 : After the direct memory access controller receives the data transfer trigger signal for the first time, the timer is controlled to start timing from a preset initial timing value.

[0052] Optionally, a timer may be provided in the direct memory access controller, and the preset initial timing value may be an initial value loaded into the timer when the timer is started or reset. The preset initial timing value may be zero or a non-zero value. The direct memory access controller may control the timer to start timing from the preset initial timing value at the time when the direct memory access controller first receives the data transfer trigger signal, or at a time later than the time but relatively close to the time.

[0053] Step 520 : After the timer starts timing for the first time, in response to the direct memory access controller receiving a data transfer trigger signal, the timer is controlled to restart timing from a preset initial timing value.

[0054] Optionally, after the timer starts timing for the first time, when the direct memory access controller receives a data transfer trigger signal from the data node, the direct memory access controller may trigger the timer to clear the current timing value and restart timing from a preset initial timing value.

[0055] Step 530: Determine the receiving status of the data transfer trigger signal by the direct memory access controller based on the current timing value and timing type of the timer.

[0056] Optionally, the timer can have two timing types: a countdown type and a countdown type. If the timer is a countdown type, the time value recorded by the timer can gradually change from small to large, and the time value recorded by the timer can represent the accumulated time of the countdown. If the timer is a countdown type, the time value recorded by the timer can gradually change from large to small, and the time value recorded by the timer can represent the remaining time of the countdown.

[0057] Optionally, the current timing value of the timer may be a time value currently recorded by the timer.

[0058] Alternatively, as Figure 6 As shown, step 530 may include step 610 , step 620 and step 630 .

[0059] Step 610: Determine a preset timing threshold corresponding to the timing type of the timer.

[0060] Optionally, the longest time interval between two consecutive data transfer trigger signals sent by the data node to the direct memory access controller when no data node is abnormal can be determined in advance through experiments. For the sake of description, this longest time interval may be referred to as the target time interval in the following text.

[0061] If the timing type of the timer is a positive timing type, the corresponding preset timing threshold may be greater than the preset initial timing value, and the time interval between the corresponding preset timing threshold and the preset initial timing value may be greater than or equal to the target time interval.

[0062] If the timing type of the timer is a countdown type, the corresponding preset timing threshold may be smaller than the preset initial timing value, and the time interval between the preset initial timing value and the corresponding preset timing threshold may be greater than or equal to the target time interval.

[0063] Step 620: Determine the numerical relationship between the current timing value of the timer and the preset timing threshold.

[0064] Optionally, a magnitude relationship between the current timing value of the timer and the preset timing threshold in step 610 may be determined, and the determined magnitude relationship may be used as the numerical value relationship in step 620 .

[0065] Step 630: Determine the receiving status of the data transfer trigger signal by the direct memory access controller based on the timing type and the value relationship.

[0066] In some optional embodiments of the present disclosure, step 630 may include: In response to the timing type being a positive timing type and the numerical relationship being used to indicate that the current timing value is greater than or equal to a preset timing threshold, it is determined that the receiving state of the data transfer trigger signal by the direct memory access controller is an abnormal state.

[0067] In some other optional implementations of the present disclosure, step 630 may include: In response to the timing type being a countdown type and the numerical relationship being used to indicate that the current timing value is less than a preset timing threshold, it is determined that the receiving state of the data transfer trigger signal by the direct memory access controller is an abnormal state.

[0068] If the timing type of the timer is a positive timing type, and the numerical relationship is used to represent that the current timing value is greater than or equal to the preset timing threshold, this indicates that after the direct memory access controller last received a data transfer trigger signal from the data node, the direct memory access controller did not receive a data transfer trigger signal from the data node again within the allowed time range, so that the time value recorded by the timer increases from small to large to reach the preset timing threshold. Therefore, it can be determined that the direct memory access controller's reception status of the data transfer trigger signal is abnormal.

[0069] If the timing type of the timer is a countdown type, and the numerical relationship is used to represent that the current timing value is less than the preset timing threshold, this indicates that after the direct memory access controller last received the data transfer trigger signal from the data node, the direct memory access controller received the data transfer trigger signal from the data node again within the allowed time range, so that the time value recorded by the timer does not reach the preset timing threshold due to the occurrence of the zeroing operation. Therefore, it can be determined that the direct memory access controller's reception status of the data transfer trigger signal is normal.

[0070] In this way, when the timing type of the timer is known, by determining the preset timing threshold corresponding to the timing type of the timer, and further determining the numerical relationship between the current timing value of the timer and the preset timing threshold, an effective reference can be provided for the direct memory access controller to determine the receiving status of the data transfer trigger signal, thereby determining the receiving status efficiently and reliably.

[0071] In some embodiments, the ratio between the current timing value of the timer and the preset timing threshold in step 610 may also be determined, and the determined ratio may be used as the numerical relationship in step 620. In this case, in response to the timing type being a positive timing type, and the numerical relationship being used to indicate that the ratio between the current timing value and the preset timing threshold is greater than or equal to a preset ratio (e.g., 1, 1.1, etc.), it may be determined that the direct memory access controller's reception status of the data transfer trigger signal is abnormal. In response to the timing type being a countdown type, and the numerical relationship being used to indicate that the ratio between the current timing value and the preset timing threshold is less than the preset ratio, it may be determined that the direct memory access controller's reception status of the data transfer trigger signal is normal.

[0072] In an embodiment of the present disclosure, after a direct memory access controller receives a data transfer trigger signal for the first time, a timer can be controlled to start timing from a preset initial timing value, and the direct memory access controller's receipt of the data transfer trigger signal can be used as a condition for triggering the timer to restart timing from the preset initial timing value. In this way, the current timing value of the timer will be affected by the direct memory access controller's reception of the data transfer trigger signal. Therefore, by combining the timer's current timing value and timing type, the direct memory access controller's reception status of the data transfer trigger signal can be efficiently and reliably inferred.

[0073] In some optional examples, such as Figure 7 As shown, step 510 may include step 710 and step 720 .

[0074] Step 710 : In response to the direct memory access controller receiving the data transfer trigger signal and after transferring data between the direct memory access controller and the data node, the direct memory access controller returns a confirmation signal to the data node.

[0075] Optionally, after the direct memory access controller responds to the received data transfer trigger signal and transfers data (e.g., a preset amount of data) between the direct memory access controller and the data node, the direct memory access controller may return a confirmation signal to the data node to indicate that the data transfer has been completed. If the data node is a data source node, the confirmation signal may be expressed as Figure 3If the data node is the data destination node, the confirmation information can be expressed as Figure 4 DMA_TX_ACK in .

[0076] Step 720 : In response to the first confirmation signal being returned to the data node via the direct memory access controller, control the timer to start timing from a preset initial timing value.

[0077] Optionally, after the direct memory access controller first receives a data transfer trigger signal from the data node, it may be detected whether the direct memory access controller returns an acknowledgment signal (i.e., a first acknowledgment signal) to the data node in response to the data transfer trigger signal. If it is detected that the direct memory access controller has returned the first acknowledgment signal to the data node, a timing start control signal may be provided to the timer, causing the timer to start timing from a preset initial timing value in response to the timing start control signal. If it is detected that the direct memory access controller has not yet returned the first acknowledgment signal to the data node, it may continue to detect whether the direct memory access controller has returned the first acknowledgment signal to the data node.

[0078] In an embodiment of the present disclosure, the first confirmation signal returned by the direct memory access controller to the data node can be used to efficiently and quickly determine when the timer starts timing from a preset initial timing value. In addition, by transmitting the data transfer trigger signal and the confirmation signal between the direct memory access controller and the data node, a handshake communication between the direct memory access controller and the data node can be effectively implemented, so that data transfer between the direct memory access controller and the data node can be implemented based on the handshake communication. For example, the data node can send a data transfer trigger signal to the direct memory access controller, and the direct memory access controller can transfer a preset amount of data between the direct memory access controller and the data node when receiving the data transfer trigger signal, and return a confirmation signal to the data node when the transfer of the preset amount of data is completed; when receiving the confirmation signal from the direct memory access controller, the data node can determine that the transfer of the previous preset amount of data has been completed, then the data node can send a new data transfer trigger signal to the direct memory access controller; and so on and so forth until the transfer of the predetermined amount of data between the direct memory access controller and the data node is completed.

[0079] In some optional examples, the data node may be a data source node; The data transfer between the direct memory access controller and the data node in step 210 may include: Transporting data from a data source node to a direct memory access controller; like Figure 8As shown, the data transfer end operation in step 230 may include steps 810 and 820 .

[0080] Step 810: Stop transferring data from the data source node to the direct memory access controller.

[0081] Here, since the transfer of data from the data source node to the direct memory access controller is stopped, the direct memory access controller may exit the waiting state, ie, is no longer prepared to continue to transfer data from the data source node.

[0082] Step 820 : After all the data in the direct memory access controller are transferred to the data destination node, an interrupt signal is sent to a predetermined object, so that the predetermined object processes the data in the data destination node in response to the interrupt signal.

[0083] Alternatively, the predetermined object may be a circuit in a chip used for data processing, such as a central processing unit (CPU) or a graphics processing unit (GPU). Here, the DMA controller may transfer all cached data (e.g., data transferred from a data source node) to a data destination node. After the data transfer is complete, the controller sends an interrupt signal to the destination node via the electrical connection between the DMA controller and the predetermined object, notifying the destination node of the completion of the data transfer task. At this point, the predetermined object may process the data in the data destination node. For example, if the chip containing both the DMA controller and the CPU is an intelligent driving chip, and the data transferred by the DMA controller to the data destination node is GPS positioning data, the CPU may use the GPS positioning data to perform calculations to determine the driving strategy of the vehicle equipped with the intelligent driving chip, such as whether to stop, slow down, or turn. In some embodiments, the data transferred by the DMA controller to the data destination node may also be an environmental image. The CPU may use the environmental image to perform calculations to obtain a perception of the vehicle's surroundings and determine the vehicle's driving strategy accordingly.

[0084] In an embodiment of the present disclosure, before a predetermined amount of data is transferred between a direct memory access controller and a data source node, if it is detected that the direct memory access controller is in an abnormal state in receiving a data transfer trigger signal, not only can the direct memory access controller be prevented from being placed in a waiting state, but an interrupt signal can also be generated and sent to enable the predetermined object to perform data processing normally, thereby ensuring the normal operation of the chip where the direct memory access controller and the data source node are located as much as possible.

[0085] In some optional examples, the data node may be a data destination node; The data transfer between the direct memory access controller and the data node in step 210 may include: Transfer data from the direct memory access controller to the data destination node; like Figure 9 As shown, the data transfer end operation in step 230 may include steps 910 and 920 .

[0086] Step 910: Stop transferring data from the DMA controller to the data destination node.

[0087] Here, since the data transfer from the direct memory access controller to the data destination node is stopped, the direct memory access controller may exit the waiting state, ie, is no longer prepared to continue transferring data to the data destination node.

[0088] Step 920: Send an interrupt signal to a predetermined object, so that the predetermined object processes the data in the data destination node in response to the interrupt signal.

[0089] Optionally, the predetermined object may be a circuit in a chip for data processing, such as a central processing unit, a graphics processing unit, etc. Through the electrical connection between the direct memory access controller and the predetermined object, an interrupt signal may be sent to the predetermined object to notify the predetermined object that the data transfer task is complete. At this time, the predetermined object may process the data in the data destination node. The specific processing method may refer to Figure 8 The relevant introduction in the illustrated embodiment will not be repeated here.

[0090] In an embodiment of the present disclosure, before a predetermined amount of data is transferred between a direct memory access controller and a data destination node, if it is detected that the direct memory access controller is in an abnormal state in receiving a data transfer trigger signal, not only can the direct memory access controller be prevented from being placed in a waiting state, but an interrupt signal can also be generated and sent to enable the predetermined object to perform data processing normally, thereby ensuring the normal operation of the chip where the direct memory access controller and the data source node are located as much as possible.

[0091] In some optional examples, such as Figure 10-1 As shown, the CPU can initialize the DMA controller. For example, the CPU can configure the address of the data to be read (which can be the address of the source end), the address of the data to be written (which can be the address of the destination end), and the total amount of data to be transferred (equivalent to the predetermined amount of data mentioned above) into the registers or linked list of the DMA controller.

[0092] The source end may have data that needs to be moved, and the source end can send it to the DMA controller Figure 3Each time the DMA controller receives a DMA_RX_REQ from the source, it can retrieve a preset amount of data from the source. After successfully retrieving the data, the DMA controller can return a response to the source. Figure 3 The DMA controller can determine whether the total amount of data transferred between it and the source has reached a predetermined amount of data configured in the DMA controller. Furthermore, the DMA controller can detect the reception status of the DMA_RX_REQ before the total amount of data transferred reaches the predetermined amount of data. For example, after the DMA controller first receives the DMA_RX_REQ, it can control a timer to start timing from a preset initial value. Subsequently, in response to the DMA controller receiving the DMA_RX_REQ, it can clear the current timer value and restart timing from the preset initial value. In this way, the DMA controller's reception status of the DMA_RX_REQ can be determined based on the current timer value and timing type. If the DMA controller's reception status of the DMA_RX_REQ is abnormal, it can execute a data transfer termination operation, such as terminating data transfer from the source, transferring data cached within the DMA controller to the destination, writing the transferred data amount to a descriptor or register, and then generating an interrupt signal to notify the CPU so that the CPU can process the data transferred to the destination.

[0093] In an optional example, when the DMA controller is transferring data from the source end, it may happen that after transferring several data sets, the DMA controller does not receive the DMA_RX_REQ for a long time. For example, the smart driving chip can use the UART to receive the GPS positioning data collected by the GPS device, and then use the DMA controller to transfer the GPS positioning data at the UART (which serves as the data source node). When the vehicle equipped with the smart driving chip encounters a traffic light, it will temporarily stop, so that the GPS device does not transmit GPS positioning data to the UART for a period of time. If the UART does not receive the GPS positioning data, it will not send DMA_RX_REQ to the DMA controller. Because the DMA controller has not completed the data transfer of the predetermined amount of data, it cannot stop transferring data to notify the CPU. However, the vehicle needs to update its location. Therefore, in the related technology, the CPU will poll the status register in the DMA controller, which will occupy the CPU bandwidth and increase the CPU overhead. In view of this, in an embodiment of the present disclosure, if the DMA controller does not receive the DMA_RX_REQ from the UART for a long time before completing the data transfer of a predetermined amount of data, it can execute a data transfer end operation, for example, it can stop transferring data and notify the CPU, thereby avoiding the DMA controller from being in a waiting state all the time, and the CPU does not need to constantly poll the status register in the DMA controller, which is conducive to reducing CPU overhead.

[0094] In other optional examples, such as Figure 10-2 As shown, the CPU can initialize the DMA controller. For example, the CPU can configure the address of the data to be read (which can be the address of the source end), the address of the data to be written (which can be the address of the destination end), and the predetermined data amount into the register or linked list of the DMA controller.

[0095] If there is free space on the destination side, the destination side can send the data to the DMA controller. Figure 4 When the DMA controller receives the DMA_TX_REQ from the destination, it can move the preset amount of data in the DMA controller's internal buffer to the destination and return it to the source. Figure 4DMA_TX_ACK shown. The DMA controller can determine whether the total amount of data transferred between it and the destination end has reached the predetermined data amount configured in the DMA controller. In addition, the DMA controller's reception status for DMA_TX_REQ can be detected before the total amount of data transferred reaches the predetermined data amount. For example, after the DMA controller receives the DMA_TX_REQ for the first time, the control timer can be controlled to start timing from a preset initial timing value. Thereafter, in response to the DMA controller receiving the DMA_TX_REQ, the current timing value of the timer can be cleared and the timing can be restarted from the preset initial timing value. In this way, the DMA controller's reception status for DMA_TX_REQ can be determined in combination with the timer's current timing value and timing type. If the DMA controller's reception status for DMA_TX_REQ is an abnormal state, a data transfer termination operation can be performed, for example, data transfer to the destination end can be terminated, and an interrupt signal can be generated to notify the CPU so that the CPU processes the data that has been transferred to the destination end.

[0096] In one example, when a DMA controller transfers data to a destination, it may fail to receive a DMA_TX_REQ for a long time after transferring several data entries. For example, a smart cockpit chip can use the DMA controller to write audio data to an audio bus (which serves as the data destination node) and then use the audio bus to write the audio data to an audio device to play music. During this process, if the user turns off the audio device, the audio bus cannot write the audio data to the audio device. As there is no free space on the audio bus to store new audio data, the audio bus will not send a DMA_TX_REQ to the DMA controller. In the related art, the CPU polls the status register in the DMA controller, which consumes CPU bandwidth and increases CPU overhead. Therefore, in an embodiment of the present disclosure, if the DMA controller fails to receive a DMA_TX_REQ from the audio bus for a long time before completing the transfer of a predetermined amount of data, the controller can execute a data transfer termination operation, such as stopping data transfer and notifying the CPU. This prevents the DMA controller from being in a waiting state. Accordingly, the CPU does not need to continuously poll the status register in the DMA controller, thereby reducing CPU overhead.

[0097] Exemplary devices Figure 11 It is a structural diagram of a data handling device provided by some exemplary embodiments of the present disclosure. Figure 11 The apparatus shown may include: A transfer module 1110 is configured to transfer data between the direct memory access controller and the data node in response to the direct memory access controller receiving a data transfer trigger signal from the data node; A statistics module 1120 is used to count the total amount of data moved by the moving module 1110; The execution module 1130 is configured to execute a data transfer end operation in response to detecting that the direct memory access controller receives the data transfer trigger signal in an abnormal state before the total data amount counted by the statistics module 1120 reaches a predetermined data amount.

[0098] In some optional examples, such as Figure 12 As shown, the apparatus provided by the embodiment of the present disclosure further includes: The first control module 1210 is configured to control the timer to start timing from a preset initial timing value after the direct memory access controller receives a data transfer trigger signal for the first time before the total data amount counted by the statistics module 1120 reaches a predetermined data amount; The second control module 1220 is configured to control the timer to restart timing from a preset initial timing value in response to the direct memory access controller receiving a data transfer trigger signal after the timer starts timing for the first time; The determination module 1230 is configured to determine a receiving status of the direct memory access controller for the data transfer trigger signal based on a current timing value and a timing type of the timer.

[0099] In some optional examples, such as Figure 13 As shown, the determination module 1230 includes: A first determining submodule 1310 is configured to determine a preset timing threshold corresponding to a timing type of the timer; The second determining submodule 1320 is configured to determine a numerical relationship between a current timing value of the timer and the preset timing threshold determined by the first determining submodule 1310; The third determining submodule 1330 is configured to determine a receiving status of the direct memory access controller for the data transfer trigger signal based on the timing type and the numerical relationship determined by the second determining submodule 1320 .

[0100] In some optional examples, the third determining submodule 1330 includes: a first determining unit configured to determine that a receiving status of the data transfer trigger signal by the direct memory access controller is an abnormal state in response to the timing type being a positive timing type and the numerical relationship determined by the second determining submodule 1320 being used to indicate that the current timing value is greater than or equal to a preset timing threshold; or, The second determining unit is configured to determine that the receiving status of the data transfer trigger signal by the direct memory access controller is an abnormal state in response to the timing type being a countdown type and the numerical relationship determined by the second determining submodule 1320 being used to represent that the current timing value is less than a preset timing threshold.

[0101] In some optional examples, such as Figure 14 As shown, the first control module 1210 includes: a return submodule 1410 for returning a confirmation signal to the data node via the direct memory access controller in response to the direct memory access controller receiving a data transfer trigger signal and after transferring data between the direct memory access controller and the data node; The control submodule 1420 is configured to control the timer to start timing from a preset initial timing value in response to the first confirmation signal being returned to the data node via the direct memory access controller.

[0102] In some optional examples, the data node is a data source node; A transport module 1110 is configured to transport data from a data source node to a direct memory access controller; like Figure 15 As shown, the execution module 1130 includes: A first suspending submodule 1510 is configured to suspend the transfer of data from the data source node to the direct memory access controller; The first execution submodule 1520 is configured to send an interrupt signal to a predetermined object after transferring all data in the direct memory access controller to the data destination node, so that the predetermined object processes the data in the data destination node in response to the interrupt signal.

[0103] In some optional examples, the data node is a data destination node; A transport module 1110 is configured to transport data from a direct memory access controller to a data destination node; like Figure 16 As shown, the execution module 1130 includes: The second terminating submodule 1610 is configured to terminate the transfer of data from the direct memory access controller to the data destination node; The second execution submodule 1620 is configured to send an interrupt signal to a predetermined object, so that the predetermined object processes the data in the data destination node in response to the interrupt signal.

[0104] In the device of the present disclosure, various optional embodiments, optional implementation methods and optional examples disclosed in the above exemplary method part can be flexibly selected and combined as needed to achieve corresponding functions and effects, and the present disclosure does not list them one by one.

[0105] The beneficial technical effects corresponding to the exemplary embodiment of this device can be found in the corresponding beneficial technical effects of the above exemplary method part, which will not be repeated here.

[0106] Exemplary Chips Figure 17 It is a schematic diagram of the structure of a chip provided by some exemplary embodiments of the present disclosure. Figure 17 The chips shown may include: Data node, which is used to generate data transfer trigger signals; The direct memory access controller is used to transfer data between the direct memory access controller and the data node in response to receiving a data transfer trigger signal from the data node, and to count the total amount of data that has been transferred. In response to detecting that the direct memory access controller's reception status of the data transfer trigger signal is abnormal before the total amount of data reaches a predetermined amount of data, the direct memory access controller executes a data transfer end operation.

[0107] In some optional examples, the direct memory access controller is further used to control the timer to start timing from a preset initial timing value after receiving a data transfer trigger signal for the first time before the total data amount reaches a predetermined data amount; after the timer starts timing for the first time, in response to receiving a data transfer trigger signal, control the timer to restart timing from the preset initial timing value; and determine the reception status of the direct memory access controller for the data transfer trigger signal based on the current timing value and timing type of the timer.

[0108] In some optional examples, the direct memory access controller is configured to determine a reception status of the direct memory access controller for the data transfer trigger signal based on a current timing value and a timing type of the timer, including: The direct memory access controller is used to determine a preset timing threshold corresponding to the timing type of the timer; determine the numerical relationship between the current timing value of the timer and the preset timing threshold; and determine the receiving status of the direct memory access controller for the data transfer trigger signal based on the timing type and the numerical relationship.

[0109] In some optional examples, the direct memory access controller is configured to determine a reception status of the direct memory access controller for a data transfer trigger signal based on a timing type and a numerical value relationship, including: The direct memory access controller is configured to, in response to the timing type being a positive timing type and the numerical relationship being used to indicate that the current timing value is greater than or equal to a preset timing threshold, determine that a receiving state of the direct memory access controller for the data transfer trigger signal is an abnormal state; or, The DMA controller is configured to determine that the receiving state of the data transfer trigger signal by the DMA controller is abnormal in response to the timing type being a countdown type and the numerical relationship being used to represent that the current timing value is less than a preset timing threshold.

[0110] In some optional examples, the direct memory access controller is configured to control the timer to start timing from a preset initial timing value after receiving the data transfer trigger signal for the first time, including: The direct memory access controller is used to respond to receiving a data transfer trigger signal and, after transferring data between the direct memory access controller and the data node, return a confirmation signal to the data node through the direct memory access controller; in response to the first confirmation signal having been returned to the data node, control the timer to start timing from a preset initial timing value.

[0111] In some optional examples, the data node is a data source node; The DMA controller is used to transfer data between the DMA controller and the data nodes, including: The direct memory access controller is used to transfer data from the data source node to the direct memory access controller; The direct memory access controller is used to perform data transfer end operations, including: The direct memory access controller is used to stop transferring data from the data source node to the direct memory access controller; after transferring all the data in the direct memory access controller to the data destination node, an interrupt signal is sent to a predetermined object so that the predetermined object responds to the interrupt signal and processes the data in the data destination node.

[0112] In some optional examples, the data node is a data destination node; The DMA controller is used to transfer data between the DMA controller and the data nodes, including: The direct memory access controller is used to move data from itself to the data destination node; The direct memory access controller is used to perform data transfer end operations, including: The direct memory access controller is used to stop transferring data from the direct memory access controller to the data destination node; and send an interrupt signal to a predetermined object so that the predetermined object responds to the interrupt signal and processes the data in the data destination node.

[0113] In the chip disclosed in the present invention, various optional embodiments, optional implementation methods and optional examples disclosed in the above exemplary method part can be flexibly selected and combined as needed to achieve corresponding functions and effects, and are not listed one by one in this disclosure.

[0114] The beneficial technical effects corresponding to the exemplary embodiment of this chip can be found in the corresponding beneficial technical effects of the exemplary method section above, which will not be repeated here.

[0115] Exemplary electronic devices Figure 18 18 is a block diagram of an electronic device according to an embodiment of the present disclosure. The electronic device 1800 includes one or more processors 1810 and a memory 1820 .

[0116] The processor 1810 may be a central processing unit (CPU) or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 1800 to perform desired functions.

[0117] Memory 1820 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory. Non-volatile memory may include, for example, read-only memory (ROM), a hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 1810 may execute one or more computer program instructions to implement the methods of the various embodiments of the present disclosure described above and / or other desired functions.

[0118] In one example, the electronic device 1800 may further include an input device 1830 and an output device 1840 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0119] The input device 1830 may also include, for example, a keyboard, a mouse, and the like.

[0120] The output device 1840 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output device, etc.

[0121] Of course, to simplify, Figure 18 Only some of the components related to the present disclosure in the electronic device 1800 are shown, and components such as buses, input / output interfaces, etc. are omitted. In addition, the electronic device 1800 may further include any other appropriate components according to specific application scenarios.

[0122] Exemplary computer program products and computer-readable storage media In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions that, when executed by a processor, enable the processor to perform the steps of the method according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.

[0123] The computer program product may be written in any combination of one or more programming languages ​​to implement the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, and conventional procedural programming languages ​​such as C or similar programming languages. The program code may be executed entirely on the user's computing device, partially on the user's computing device, as a stand-alone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0124] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, causes the processor to execute the steps of the method according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0125] The computer-readable storage medium may be any combination of one or more readable media. The readable medium may be a readable signal medium or a readable storage medium. The readable storage medium may include, for example, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any combination thereof. More specific examples (a non-exhaustive list) of readable storage media include: an electrical connection having one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof.

[0126] The basic principles of the present disclosure have been described above in conjunction with specific embodiments. However, the advantages, strengths, and effects mentioned in this disclosure are merely illustrative and non-limiting, and should not be construed as necessarily possessed by each embodiment of the present disclosure. The specific details disclosed above are provided for illustrative purposes and to facilitate understanding, and are not intended to be limiting. The above details do not limit the present disclosure to necessarily being implemented using the above specific details.

[0127] Those skilled in the art may make various changes and modifications to the present disclosure without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present disclosure and their equivalents, the present disclosure is intended to include these modifications and variations.

Claims

1. A data transport method, comprising: In response to a direct memory access controller receiving a data transfer trigger signal from a data node, transferring data between the direct memory access controller and the data node; Counting the total amount of the data that has been moved; In response to detecting that the direct memory access controller receives the data transfer trigger signal in an abnormal state before the total data amount reaches a predetermined data amount, a data transfer end operation is executed.

2. The method according to claim 1, wherein Before the total data amount reaches the predetermined data amount, the method further includes: After the direct memory access controller receives the data transfer trigger signal for the first time, controlling the timer to start timing from a preset initial timing value; After the timer starts timing for the first time, in response to the direct memory access controller receiving the data transfer trigger signal, controlling the timer to restart timing from the preset initial timing value; A reception status of the data transfer trigger signal by the direct memory access controller is determined based on a current timing value and a timing type of the timer.

3. The method according to claim 2, wherein: The determining, based on the current timing value and the timing type of the timer, a receiving status of the data transfer trigger signal by the direct memory access controller includes: determining a preset timing threshold corresponding to a timing type of the timer; Determining a numerical relationship between a current timing value of the timer and the preset timing threshold; Based on the timing type and the numerical relationship, a reception status of the data transfer trigger signal by the direct memory access controller is determined.

4. The method according to claim 3, wherein: The determining, based on the timing type and the numerical relationship, a reception status of the data transfer trigger signal by the direct memory access controller includes: In response to the timing type being a positive timing type and the numerical relationship being used to indicate that the current timing value is greater than or equal to the preset timing threshold, determining that a receiving state of the data transfer trigger signal by the direct memory access controller is an abnormal state; or, In response to the timing type being a countdown type and the numerical relationship being used to represent that the current timing value is less than the preset timing threshold, it is determined that the receiving state of the data transfer trigger signal by the direct memory access controller is an abnormal state.

5. The method according to claim 2, wherein: After the direct memory access controller receives the data transfer trigger signal for the first time, controlling the timer to start timing from a preset initial timing value includes: In response to the direct memory access controller receiving the data transfer trigger signal and after transferring the data between the direct memory access controller and the data node, returning a confirmation signal to the data node through the direct memory access controller; In response to the first confirmation signal being returned to the data node via the direct memory access controller, the timer is controlled to start timing from a preset initial timing value.

6. The method according to claim 1, wherein The data node is a data source node; The transferring of data between the direct memory access controller and the data node includes: Transporting data from the data source node to the direct memory access controller; The data transfer end operation includes: Stopping the transfer of data from the data source node to the direct memory access controller; After all the data in the direct memory access controller are transferred to the data destination node, an interrupt signal is sent to a predetermined object, so that the predetermined object processes the data in the data destination node in response to the interrupt signal.

7. The method according to claim 1, wherein The data node is a data destination node; The transferring of data between the direct memory access controller and the data node includes: Transferring data from the direct memory access controller to the data destination node; The data transfer end operation includes: Stopping the transfer of data from the direct memory access controller to the data destination node; An interrupt signal is sent to a predetermined object, so that the predetermined object processes the data in the data destination node in response to the interrupt signal.

8. A data handling device comprising: a transport module, configured to transport data between the direct memory access controller and the data node in response to the direct memory access controller receiving a data transport trigger signal from the data node; A statistics module, configured to count the total amount of the data moved by the moving module; The execution module is configured to execute a data transfer end operation in response to detecting that the direct memory access controller receives the data transfer trigger signal in an abnormal state before the total data amount counted by the statistics module reaches a predetermined data amount.

9. A chip comprising: Data node, used to generate data transfer trigger signals; A direct memory access controller is configured to, in response to receiving the data transfer trigger signal from the data node, transfer data between the direct memory access controller and the data node, and to count a total amount of the transferred data; and, in response to detecting that a reception status of the direct memory access controller in response to the data transfer trigger signal is abnormal before the total amount of data reaches a predetermined amount, execute a data transfer termination operation.

10. A computer-readable storage medium storing a computer program, wherein the computer program is executed by a processor to execute the data transport method according to any one of claims 1 to 7.

11. An electronic device, comprising: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the data handling method described in any one of claims 1 to 7.

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