Differential read-write circuit, memory and read-write method of differential read-write circuit

Abstract

The invention discloses a differential read-write circuit, a memory and a read-write method of the differential read-write circuit, which are applied to the technical field of integrated circuits. An array circuit of the differential read-write circuit is a multi-row and N-column bit array, wherein N is greater than 3. If a plurality of columns exist in the first sub-array or the second sub-array, the source lines and the bit lines of the respective columns are connected through switches; and the source line and the bit line at the two ends in the sub-array are respectively grounded and accessed to the input end of the comparator. The first sub-array and the second sub-array are respectively connected to different input ends of the comparator, and the comparator is used for respectively and correspondingly connecting two input ends of the comparator, all columns in the two sub-arrays and the ground during read operation. Due to the fact that multiple columns exist in each row of the first sub-array and the second sub-array, when part of bits in one row of one sub-array fail due to breakdown, the resistance values of the remaining bits are still effective, and therefore it is guaranteed that data are read out correctly, and the read-write reliability of the differential read-write circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a differential read / write circuit, a memory, and a read / write method of the differential read / write circuit. Background Art

[0002] Figure 1 Schematic diagram of the traditional differential read and write circuit structure; Figure 1 As shown in the figure, in non-volatile magnetic random access memory (MRAM), differential storage utilizes two memory cells to store one bit of data. MRAM uses magnetic tunnel junctions (MTJs) as memory cells, recording binary data by changing the magnetization direction. A differential cell consists of two bits with identical structures connected to the same word line (WL) signal. The two bits are connected to two write drivers via switches and to the ends of a sense amplifier (SA). During a write operation, the write drivers write opposite data to the two bits, resulting in different resistance values ​​for the MTJs of the two bits. During a read operation, the SA reads the data through the bits connected to it, specifically the resistance values ​​of the MTJs of the two bits (the bit with higher resistance is in the ap state, with resistance Rap; the bit with lower resistance is in the p state, with resistance Rp). By comparing the resistance values ​​of the two bits, the differential cell can be read as 0 or 1. Differential storage has the advantages of fast reading speed, high reliability and wide temperature range adaptability.

[0003] However, due to wear and tear, the MTJ will break down after a certain number of read and write operations. After breakdown, the resistance Rbd of the MTJ is several hundred ohms, which is relatively small compared to Rp and Rap. If the MTJ of any bit in a differential cell breaks down, the entire differential cell becomes inoperable, resulting in low reliability of existing differential read and write circuits.

[0004] It can be seen that how to improve the read and write reliability of the differential read and write circuit is an urgent problem to be solved by those skilled in the art. Summary of the Invention

[0005] The purpose of this application is to provide a differential read / write circuit, a memory, and a read / write method for the differential read / write circuit to solve the problem of low reliability of existing differential read / write circuits.

[0006] To solve the above technical problems, the present application provides a differential read / write circuit, comprising: an array circuit, a plurality of write drive circuits, and a comparator;

[0007] The array circuit is a bit array with multiple rows and N columns, where N is greater than 3;

[0008] The bit cells of each column of the array circuit are connected in parallel via the source line and the bit line of the corresponding column, and each column of the bit cells corresponds to a write driver circuit, and the write driver circuit is used to connect the source line and the bit line corresponding to each column to write data to the corresponding bit cell during a write operation;

[0009] The array circuit is divided into a first sub-array and a second sub-array by column; if there are multiple columns in the sub-array, the source lines and bit lines of each column are connected via switches; the source lines and bit lines at both ends of the sub-array are grounded and connected to the input end of the comparator, respectively;

[0010] The first subarray and the second subarray are respectively connected to different input terminals of the comparator. The comparator is used to connect its two input terminals, all columns in the two subarrays and the ground respectively during a read operation to read data in each row of the array circuit.

[0011] Preferably, N is 4, and the first sub-array and the second sub-array each have two columns.

[0012] Preferably, the method further comprises: two ends of the write driver circuit are connected to the source line and the bit line of the corresponding column in the array circuit via a switch respectively.

[0013] Preferably, the two input terminals of the comparator are connected to the bit lines at both ends of the first sub-array and the second sub-array respectively through a switch, and the source lines at both ends of the first sub-array and the second sub-array are grounded respectively through a switch.

[0014] Preferably, each element of the array circuit is composed of a MOS transistor and a magnetic tunnel junction connected in series.

[0015] In order to solve the above technical problems, the present application also provides a memory including the above differential read-write circuit.

[0016] To solve the above technical problems, the present application further provides a writing method for a differential read / write circuit, which is applied to the above differential read / write circuit, and the method includes:

[0017] monitoring an operation instruction for the differential read / write circuit;

[0018] If a write operation instruction is monitored, the write driver circuit is connected to the source line and bit line corresponding to each column;

[0019] The write driver circuit is controlled to write data into the corresponding bit element.

[0020] Preferably, controlling the write driver circuit to write data to the corresponding bit element includes:

[0021] The write driver circuit is controlled to write the same data to all bits in the same row of the first subarray and the same data to all bits in the same row of the second subarray; wherein the data in the same row of the first subarray and the second subarray are opposite.

[0022] To solve the above technical problems, the present application further provides a reading method of a differential read / write circuit, which is applied to the above differential read / write circuit, and the method includes:

[0023] monitoring an operation instruction for the differential read / write circuit;

[0024] If a read operation instruction is monitored, the two input terminals of the comparator itself, all columns in the two sub-arrays and the ground are connected accordingly;

[0025] The read data is determined according to the magnitude of the current at the two input terminals of the comparator.

[0026] Preferably, determining the read data according to the current magnitudes of the two input terminals of the comparator includes:

[0027] Obtaining a comparison result of the current magnitudes of the two input terminals of the comparator;

[0028] Determine the bit resistance value of each row of the first sub-array and the second sub-array according to the comparison result;

[0029] The data stored in each row of the array circuit is determined according to the bit resistance values ​​of each row of the first sub-array and the second sub-array.

[0030] To solve the above technical problems, the present application further provides a writing device for a differential read / write circuit, comprising:

[0031] A monitoring module, configured to monitor operation instructions for the differential read / write circuit;

[0032] A connection module, configured to connect the write drive circuit to the source lines and bit lines corresponding to each column if a write operation instruction is monitored;

[0033] The control module is used to control the write driver circuit to write data to the corresponding bit element.

[0034] To solve the above technical problems, the present application further provides a reading device of a differential read / write circuit, comprising:

[0035] The monitoring module is further configured to monitor operation instructions for the differential read / write circuit;

[0036] The connection module is further configured to connect the two input terminals of the comparator, all columns in the two sub-arrays, and the ground accordingly if a read operation instruction is monitored;

[0037] The determination module is used to determine the read data according to the current magnitudes of the two input terminals of the comparator.

[0038] To solve the above technical problems, the present application also provides a read / write device of a differential read / write circuit, comprising: a storage unit for storing a computer program;

[0039] The processor is used to implement the steps of the reading and writing method of the differential reading and writing circuit when executing a computer program.

[0040] To solve the above technical problems, the present application also provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of the reading and writing method of the above differential read and write circuit are implemented.

[0041] The present application provides a differential read / write circuit, comprising: an array circuit, a plurality of write driver circuits, and a comparator; wherein the array circuit is a bit array of multiple rows and N columns, where N is greater than 3. The bits of each column of the array circuit are connected in parallel through the source line and the bit line of the corresponding column, and each column of the bits corresponds to a write driver circuit, which is used to connect to the source line and the bit line corresponding to each column during a write operation to write data to the corresponding bit. By writing opposite data (1 and 0) to the bits of the same row of the first sub-array and the second sub-array through the write driver circuit, one bit of data can be saved in each row of the array circuit. The array circuit is divided into a first sub-array and a second sub-array according to the column; if there are multiple columns in the sub-array, the source line and the bit line of each column are connected by a switch; the source line and the bit line at both ends of the sub-array are respectively grounded and connected to the input end of the comparator. The first and second subarrays are connected to different inputs of a comparator. During a read operation, the comparator connects its two inputs, all columns in the two subarrays, and ground. By comparing the current in the same row of the first and second subarrays, the resistance value of the corresponding row is determined, allowing data to be read from each row of the array circuit. Because each row of the first and second subarrays may have multiple columns, even if some bits in a row of a subarray fail due to breakdown, the resistance values ​​of the remaining bits remain valid, ensuring accurate data reading and improving the read / write reliability and durability of the differential read / write circuit.

[0042] The present application also provides a memory and a reading and writing method of a differential reading and writing circuit, which corresponds to the above-mentioned differential reading and writing circuit and thus has the same beneficial effects as the above-mentioned differential reading and writing circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 Schematic diagram of the traditional differential read and write circuit structure;

[0045] Figure 2 A schematic diagram of the structure of a differential read / write circuit provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of a write operation of a differential read / write circuit provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of a read operation of a differential read / write circuit provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of an actual write operation of a differential read / write circuit provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of the actual read operation of a differential read / write circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] The core of this application is to provide a differential read-write circuit, a memory, and a read-write method for the differential read-write circuit to solve the problem of low reliability of existing differential read-write circuits.

[0052] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0053] by Figure 1For example, the principle of a traditional differential read / write circuit is to write opposite data into two bits in a row. When the MTJ of the bit is in the ap state, it is 1, and when the MTJ of the bit is in the p state, it is 0. Under the premise that the two bits have the same structure, the resistance Rap of the ap state is greater than the resistance Rp of the p state. Then, when reading the data, the resistance of the two MTJs can be obtained by comparing the current flowing through the two bits, and the bit recording 1 and the bit recording 0 can be determined. Then, according to pre-set rules, the data recorded in the row can be obtained based on the position of the two bits 1 and 0 recorded in a row. It can be seen that when reading data, it is necessary to compare the resistance of the MTJs of the two bits. If one of the MTJs is broken down, its resistance becomes very small. Therefore, the method of comparing the resistance of the MTJs of the two bits cannot guarantee the correctness of the read data.

[0054] In order to improve the read and write reliability and durability of the differential read and write circuit, an embodiment of the present application provides a differential read and write circuit, which includes: an array circuit, multiple write driver circuits, and a comparator. The array circuit is a bit array with multiple rows and N columns, where N is greater than 3; the bits in each column of the array circuit are connected in parallel through the source line and bit line of the corresponding column, and each column of the bit corresponds to a write driver circuit, which is used to connect to the source line and bit line corresponding to each column during a write operation to write data to the corresponding bit. The array circuit is divided into a first sub-array and a second sub-array according to the column; if there are multiple columns in the sub-array, the source line and bit line of each column are connected through a switch; the source line and bit line at both ends of the sub-array are respectively connected to the ground and connected to the input end of the comparator. The first sub-array and the second sub-array are respectively connected to different input ends of the comparator. The comparator is used to connect its own two input ends, all columns in the two sub-arrays, and the ground respectively during a read operation to read the data of each row of the array circuit. The differential read / write circuit of this embodiment is simple in design and easy to implement; it has a wide range of applications and can be used in various resistive memories.

[0055] The array circuit provided in the embodiments of the present application is a bit array having multiple rows and N columns, where N is greater than 3. The array circuit is divided into a first sub-array and a second sub-array by column, and at least one of the first sub-array and the second sub-array has a column number greater than 1. During a read operation, even if the MTJs of some bits are broken down, the MTJs of the remaining bits still have normal resistance values, ensuring that data can still be read normally.

[0056] It should be noted that this application does not limit the type and number of devices used. For example, a comparator can use a sensitive amplifier. In a specific implementation, the number of rows and columns of the array circuit can be set according to the needs (such as 1023 rows), and the size of N and the number of columns of the first sub-array and the second sub-array are not specifically limited. As mentioned above, assuming that the structure of each bit is the same, the resistance Rap of the MTJ in the ap state is greater than the resistance Rp of the MTJ in the p state, and there is a certain difference between the two resistance values. If the number of columns of the first sub-array and the second sub-array is the same, then after the MTJ of some bits of the first sub-array in a row is broken down, only the resistance of the MTJ of the remaining bits is valid. As long as the difference between Rp and Rap is large enough, even if only one MTJ with a resistance of Rp is still valid, the total resistance of the sub-array in the p state in the row is still greater than the total resistance of the sub-array in the ap state; that is, when the difference between Rp and Rap is large enough, the number of columns of the first sub-array and the second sub-array does not need to be limited. However, due to the different devices used, and considering that in some cases multiple Rap values ​​are greater than Rp, it is best to set the number of columns in the first and second subarrays to be the same, and the structural type of each element to avoid affecting the reading results. Each element of the array circuit can be composed of a metal-oxide-semiconductor field-effect transistor (MOS) and an MTJ in series.

[0057] Normally, the greater the number of columns in an array circuit, the lower the probability of complete bit corruption in a row of a subarray, and the higher the accuracy of data read. However, this increases hardware cost. To maximize the read / write reliability of the differential read / write circuit while reducing hardware cost, the array circuit can be configured with four columns (N = 4), with both the first and second subarrays having two columns. Figure 2 A schematic diagram of a differential read / write circuit according to an embodiment of the present application is shown; Figure 2 As shown in FIG, the differential read / write circuit is composed of an array circuit, a write drive circuit, a sense amplifier SA and several switches. nThe array has 4 rows and 4 columns, and the 4 bits in the same row constitute a differential unit. These 4 bits have the same structure. It is assumed that the first sub-array includes the columns where bits 0 and 1 are located, and the second sub-array includes the columns where bits 2 and 3 are located. The write driver circuit is connected to the BL and SL of each column in the array circuit through switches, where two write driver circuits write the same bit of data, and two write driver circuits write opposite data. That is, the bit line (BL, including BL0, BL1, BLB0, BLB1) and source line (SL, including SL0, SL1, SLB0, SLB1) of each bit are connected to the corresponding write driver (circuit) through switches S4, S5, S6, S7, S10, S11, S12 and S13 respectively. Specifically, BL0 is connected to one end of write driver 0 via S4, and SL0 is connected to the other end of write driver 0 via S5. BL1 is connected to one end of write driver 1 via S6, and SL1 is connected to the other end of write driver 1 via S7. BLB0 is connected to one end of write driver B0 via S10, and SLB0 is connected to the other end of write driver B0 via S11. BLB1 is connected to one end of write driver B1 via S12, and SLB1 is connected to the other end of write driver B1 via S13. BL0 and BLB0 are connected to both ends of SA via switches S3 and S9. SL0 and BL1 are connected to each other via switch S1, and SLB0 and BLB1 are connected to each other via switch S2. SL1 and SLB1 are connected to ground via switches S8 and S14. The structure of each bit is not limited. In this embodiment, all bits are composed of N-type metal-oxide-semiconductor field-effect transistors (NMOS transistors) and MTJs. The gates of all NMOS transistors in a row are connected to the word line (WL) corresponding to the row. When reading data in a row, all NMOS transistors in the row are controlled to be turned on.

[0058] Below is Figure 2 The differential read and write circuit in the MCU performs write and read operations. Figure 3 A schematic diagram of a write operation of a differential read / write circuit provided in an embodiment of the present application; Figure 3 As shown, during a write operation, switches S4, S5, S6, S7, S10, S11, S12, and S13 are closed, and switches S1, S2, S3, S8, S9, and S14 are open. Write drivers 0 and 1 write the same data to corresponding bits 0 and 1, while write drivers B0 and B1 write opposite data to corresponding bits 2 and 3. Figure 4 A schematic diagram of a read operation of a differential read / write circuit provided in an embodiment of the present application; Figure 4As shown in the figure, during a read operation, switches S1, S2, S3, S8, S9, and S14 are closed, while switches S4, S5, S6, S7, S10, S11, S12, and S13 are open. Through switches S1 and S2, the two ends of the sense amplifier SA are connected to the BLs of two columns in the array circuit. The read currents at both ends flow through the two bits in sequence, and the corresponding values ​​are output based on the relationship between the currents, allowing the data to be correctly read. Assume that the MTJs of bits 0 and 1 are in the P state with a resistance of Rp, and the MTJs of bits 2 and 3 are in the AP state with a resistance of Rap. The resistance of the breakdown MTJ is Rbd. Generally, Rap > 2Rp >> Rbd. During a normal read operation, the SA read current flows through two Rp terminals on one end and two Rap terminals on the other end, allowing the data to be correctly read. When one of the MTJs is broken down, then: 1. If the one that is broken down is Rp, the SA read current passes through 1 Rp and 1 Rbd at one end, and passes through 2 Rap at the other end, and the data can be read correctly (that is, the differential unit can still be used normally). 2. If the one that is broken down is Rap, the SA read current passes through 2 Rps at one end, and passes through 1 Rap and 1 Rbd at one end, and the data can be read correctly. When two of the MTJs are broken down, then: 1. If one is Rp and the other is Rap, the SA read current passes through 1 Rp and 1 Rbd at one end, and passes through 1 Rap and 1 Rbd at one end, and the data can be read correctly. 2. If it is other cases, SA cannot read the data correctly.

[0059] The present application provides a differential read / write circuit, comprising: an array circuit, a plurality of write driver circuits, and a comparator; wherein the array circuit is a bit array of multiple rows and N columns, where N is greater than 3. The bits of each column of the array circuit are connected in parallel through the source line and the bit line of the corresponding column, and each column of the bits corresponds to a write driver circuit, which is used to connect to the source line and the bit line corresponding to each column during a write operation to write data to the corresponding bit. By writing opposite data (1 and 0) to the bits of the same row of the first sub-array and the second sub-array through the write driver circuit, one bit of data can be saved in each row of the array circuit. The array circuit is divided into a first sub-array and a second sub-array according to the column; if there are multiple columns in the sub-array, the source line and the bit line of each column are connected by a switch; the source line and the bit line at both ends of the sub-array are respectively grounded and connected to the input end of the comparator. The first and second subarrays are connected to different inputs of a comparator. During a read operation, the comparator connects its two inputs, all columns in the two subarrays, and ground. By comparing the current in the same row of the first and second subarrays, the resistance value of the corresponding row is determined, allowing data to be read from each row of the array circuit. Because each row of the first and second subarrays may have multiple columns, even if some bits in a row of a subarray fail due to breakdown, the resistance values ​​of the remaining bits remain valid, ensuring accurate data reading and improving the read / write reliability and durability of the differential read / write circuit.

[0060] The embodiment of the present application provides a specific implementation method. In this embodiment, the differential array circuit includes 1023 rows and 4 columns of bits, and the 4 bits in each row constitute a differential unit. Figure 5 Schematic diagram of actual write operation of a differential read-write circuit provided in an embodiment of the present application; Figure 5 As shown, during the write operation, switches S4, S5, S6, S7, S10, S11, S12 and S13 are closed, and switches S1, S2, S3, S8, S9 and S14 are opened. Write driver 0 writes and write driver 1 writes the corresponding bits to the P state, and write driver B0 writes and write driver B1 writes the corresponding bits to the AP state.

[0061] Figure 6 Schematic diagram of actual read operation of a differential read / write circuit provided in an embodiment of the present application; Figure 6 As shown, during a read operation, switches S1, S2, S3, S8, S9, and S14 are closed, and switches S4, S5, S6, S7, S10, S11, S12, and S13 are open. Through S1 and S2, the read current at both ends of the SA passes through two bits in sequence, allowing correct data reading. When the MTJ of bit 0 or bit 1 is broken down, the SA read current passes through one Rp and one Rbd on one end and two Raps on the other end, allowing correct data reading. When the MTJ of bit 2 or bit 3 is broken down, the SA read current passes through one Rap and one Rbd on one end and two Rp on the other end, allowing correct data reading. When either of the MTJs in bit 0 or bit 1 and either of the MTJs in bit 2 or bit 3 is broken down, the SA read current passes through one Rp and one Rbd on one end and one Rap and one Rbd on the other end, allowing correct data reading.

[0062] The above embodiments mentioned that multiple switches can be used to connect the write driver circuit, array circuit, sense amplifier, and ground. This embodiment provides a specific solution. For example, the two ends of the write driver circuit can be connected to the source line and bit line of the corresponding column in the array circuit through a switch. The two input ends of the sense amplifier can be connected to the bit lines at the two ends of the first sub-array and the second sub-array through a switch, respectively. The source lines at the two ends of the first sub-array and the second sub-array are grounded through a switch. One specific solution can be seen in Figure 2 .

[0063] In order to solve the above technical problems, an embodiment of the present application further provides a memory, including the differential read and write circuit in the above embodiment.

[0064] Since the embodiments of the memory portion correspond to the embodiments of the differential read / write circuit portion, the embodiments of the memory portion may refer to the description of the embodiments of the differential read / write circuit portion, which will not be described in detail here.

[0065] The memory provided in this embodiment corresponds to the above-mentioned differential read / write circuit, and thus has the same beneficial effects as the above-mentioned differential read / write circuit.

[0066] To solve the above technical problems, an embodiment of the present application further provides a writing method for a differential read / write circuit, which is applied to the differential read / write circuit in the above embodiment. The method includes the following steps:

[0067] Step 1: Monitor the operation instructions for the differential read / write circuit.

[0068] Step 2: If a write operation instruction is monitored, the write driver circuit is connected to the source line and bit line corresponding to each column.

[0069] Step 3: Control the write driver circuit to write data to the corresponding bit.

[0070] The writing method of the differential read / write circuit provided in this embodiment corresponds to the above-mentioned differential read / write circuit, and thus has the same beneficial effects as the above-mentioned differential read / write circuit.

[0071] In actual applications, when controlling the write driver circuit to write data to the corresponding bit, the same data is generally written to all bits in the same row of the first sub-array, and the same data is written to all bits in the same row of the second sub-array; while the data in the same row of the first sub-array and the second sub-array are opposite, thereby ensuring that the data is accurately stored.

[0072] To solve the above technical problems, an embodiment of the present application further provides a reading method of a differential read / write circuit, which is applied to the differential read / write circuit in the above embodiment. The method includes the following steps:

[0073] Step 4: Monitor the operation instructions for the differential read and write circuit.

[0074] Step 5: If a read operation instruction is monitored, the two input terminals of the comparator itself, all columns in the two sub-arrays, and the ground are connected accordingly.

[0075] Step 6: Determine the read data based on the current magnitudes of the two input terminals of the comparator.

[0076] When actually reading data, after obtaining the current comparison results of the two input terminals of the comparator, the bit resistance values ​​of each row of the first sub-array and the second sub-array can be determined based on the comparison results. Finally, the data stored in each row of the array circuit can be determined based on the bit resistance values ​​of each row of the first sub-array and the second sub-array.

[0077] The reading method of the differential read / write circuit provided in this embodiment corresponds to the above-mentioned differential read / write circuit, and thus has the same beneficial effects as the above-mentioned differential read / write circuit.

[0078] In the above embodiments, the read / write method of the differential read / write circuit is described in detail. This application also provides corresponding embodiments of the read / write device of the differential read / write circuit. It should be noted that this application describes the embodiments of the device from two perspectives: one is based on the functional module perspective, and the other is based on the hardware perspective.

[0079] From the perspective of functional modules, this embodiment provides a writing device for a differential read / write circuit, the device comprising:

[0080] A monitoring module, used for monitoring operation instructions for the differential read and write circuit;

[0081] A connection module, configured to connect the write drive circuit to the source lines and bit lines corresponding to each column if a write operation instruction is monitored;

[0082] The control module is used to control the write driver circuit to write data to the corresponding bit element.

[0083] This embodiment provides a reading device of a differential read / write circuit, the device comprising:

[0084] Since the embodiments of the apparatus part correspond to the embodiments of the method part, please refer to the description of the embodiments of the method part for the embodiments of the apparatus part, and they will not be repeated here.

[0085] The monitoring module is also used to monitor operation instructions for the differential read and write circuit;

[0086] The connection module is further configured to connect the two input terminals of the comparator, all columns in the two sub-arrays and the ground accordingly if a read operation instruction is monitored;

[0087] The determination module is used to determine the read data according to the current magnitudes of the two input terminals of the comparator.

[0088] The read / write device of the differential read / write circuit provided in this embodiment corresponds to the above method and thus has the same beneficial effects as the above method.

[0089] From a hardware perspective, this embodiment provides another read / write device of a differential read / write circuit, the read / write device of the differential read / write circuit comprising: a storage unit for storing a computer program;

[0090] The processor is used to implement the steps of the reading and writing method of the differential reading and writing circuit mentioned in the above embodiment when executing the computer program.

[0091] Among them, the processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor can be implemented in at least one hardware form of a digital signal processor (DSP), a field programmable gate array (FPGA), and a programmable logic array (PLA). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a central processing unit (CPU); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a graphics processing unit (GPU), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an artificial intelligence (AI) processor, which is used to process computing operations related to machine learning.

[0092] The storage unit may include one or more computer-readable storage media, which may be non-transitory. The storage unit may also include a high-speed random access storage unit, and a non-volatile storage unit, such as one or more disk storage devices, flash memory storage devices. In this embodiment, the storage unit is at least used to store the following computer program, wherein, after the computer program is loaded and executed by the processor, it can implement the relevant steps of the read and write method of the differential read and write circuit disclosed in any of the aforementioned embodiments. In addition, the resources stored in the storage unit may also include an operating system and data, etc., and the storage method may be temporary storage or permanent storage. Among them, the operating system may include Windows, Unix, Linux, etc. The data may include but is not limited to data involved in the read and write method of the differential read and write circuit, etc.

[0093] In some embodiments, the read / write device of the differential read / write circuit may further include a communication bus, an input / output interface, a communication interface, and a power supply.

[0094] Those skilled in the art will appreciate that the structure shown in the figure does not limit the read / write device of the differential read / write circuit, and may include more or fewer components than shown in the figure.

[0095] The read / write device of the differential read / write circuit provided in an embodiment of the present application includes a storage unit and a processor. When the processor executes the program stored in the storage unit, it can implement the following method: a read / write method of the differential read / write circuit.

[0096] The read / write device of the differential read / write circuit provided in this embodiment corresponds to the above method and thus has the same beneficial effects as the above method.

[0097] Finally, the present application also provides an embodiment corresponding to a computer-readable storage medium. The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps described in the above method embodiment.

[0098] It is understood that if the methods in the above embodiments are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product, which is stored in a storage medium and executes all or part of the steps of the methods described in the various embodiments of this application.

[0099] The computer-readable storage medium provided in this embodiment corresponds to the above method and thus has the same beneficial effects as the above method.

[0100] The above describes in detail a differential read / write circuit, a memory, and a read / write method of a differential read / write circuit provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the present application.

[0101] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or device comprising the aforementioned elements.

Claims

1. A differential read / write circuit, characterized in that: include: array circuit, multiple write driver circuits, and comparators; The array circuit is a bit array with multiple rows and N columns, where N is greater than 3; The bit cells of each column of the array circuit are connected in parallel via the source line and the bit line of the corresponding column, and each column of the bit cells corresponds to a write driver circuit, and the write driver circuit is used to connect the source line and the bit line corresponding to each column to write data to the corresponding bit cell during a write operation; The array circuit is divided into a first sub-array and a second sub-array by column; if there are multiple columns in the sub-array, the source lines and bit lines of each column are connected via switches; the source lines and bit lines at both ends of the sub-array are grounded and connected to the input end of the comparator, respectively; The first subarray and the second subarray are respectively connected to different input terminals of the comparator. The comparator is used to connect its two input terminals, all columns in the two subarrays and the ground respectively during a read operation to read data in each row of the array circuit.

2. The differential read / write circuit according to claim 1, wherein: N is 4, and both the first sub-array and the second sub-array have two columns.

3. The differential read / write circuit according to claim 1 or 2, wherein: Also includes: Two ends of the write driving circuit are connected to the source line and the bit line of the corresponding column in the array circuit through a switch respectively.

4. The differential read / write circuit according to claim 3, wherein: The two input terminals of the comparator are connected to the bit lines at both ends of the first sub-array and the second sub-array through a switch respectively. The source lines at both ends of the first sub-array and the second sub-array are grounded through a switch respectively.

5. The differential read / write circuit according to claim 1, wherein: Each element of the array circuit is composed of a MOS tube and a magnetic tunnel junction connected in series.

6. A memory, characterized in that: The differential read / write circuit comprises the differential read / write circuit according to any one of claims 1 to 5.

7. A writing method for a differential read / write circuit, characterized in that: Applied to the differential read / write circuit according to any one of claims 1 to 5, the method comprising: monitoring an operation instruction for the differential read / write circuit; If a write operation instruction is monitored, the write driver circuit is connected to the source line and bit line corresponding to each column; The write driver circuit is controlled to write data into the corresponding bit element.

8. The writing method of the differential read / write circuit according to claim 7, characterized in that: The controlling the write driver circuit to write data to the corresponding bit element comprises: The write driver circuit is controlled to write the same data to all bits in the same row of the first subarray and the same data to all bits in the same row of the second subarray; wherein the data in the same row of the first subarray and the second subarray are opposite.

9. A reading method for a differential read / write circuit, characterized in that: Applied to the differential read / write circuit according to any one of claims 1 to 5, the method comprising: monitoring an operation instruction for the differential read / write circuit; If a read operation instruction is monitored, the two input terminals of the comparator itself, all columns in the two sub-arrays and the ground are connected accordingly; The read data is determined according to the magnitude of the current at the two input terminals of the comparator.

10. The reading method of the differential read / write circuit according to claim 9, characterized in that: The step of determining the read data according to the current magnitudes of the two input terminals of the comparator includes: Obtaining a comparison result of the current magnitudes of the two input terminals of the comparator; Determine the bit resistance value of each row of the first sub-array and the second sub-array according to the comparison result; The data stored in each row of the array circuit is determined according to the bit resistance values ​​of each row of the first sub-array and the second sub-array.

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