Gallium nitride TVS tube interference suppression circuit

Abstract

The invention relates to the technical field of gallium nitride TVS tubes, in particular to a gallium nitride TVS tube interference suppression circuit which comprises an input driving circuit which comprises a transistor Q1, a transistor Q2, a voltage stabilizing diode Z1, a resistor R4, a resistor R2, a thermistor R3, a capacitor C2, a capacitor C3, a diode D1, an inductor L1, a power supply VCC and a primary transformer T2. A signal GT is input into one end of the Zener diode Z1, the other end of the Zener diode Z1 is connected with the resistor R4, the resistor R4 is connected with the capacitor C2 in parallel, and one end of the resistor R4 is connected with the base electrode of the transistor Q1 and the base electrode of the transistor Q2. Interference from the outside is absorbed through the TVS tube Z1 and the TVS tube Z2, the two TVS tubes are connected in a back-to-back mode, interference from an external circuit is effectively absorbed, meanwhile, interference from a transformer is also absorbed, in addition, parasitic oscillation of the driving circuit is attenuated through the capacitive characteristic of the two TVS tubes, work abnormity of gallium nitride is avoided, and the driving circuit is safe and reliable. The stability of the whole circuit is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of gallium nitride TVS tubes, and in particular to a gallium nitride TVS tube interference suppression circuit. Background Art

[0002] Gallium nitride (GaN) TVS diodes are transient voltage suppressor (TVS) diodes with advantages such as fast response, high power absorption, low leakage current, and stable clamping voltage. They can clamp transient voltages and surges caused by lightning, device switching, electromagnetic pulses, and static electricity, reducing the risk of semiconductor device burnout or breakdown within devices and systems, thereby ensuring the reliability of electronic circuits and precision components. GaN TVS diodes are manufactured using the third-generation wide-bandgap semiconductor material, GaN. GaN offers significant advantages in TVS device applications, including high current density, low parasitic resistance, and low turn-on voltage.

[0003] However, existing GaN TVS tubes often suffer from low driving efficiency and insufficient stability. Traditional circuits are susceptible to interference during signal transmission, resulting in drive signal distortion and affecting the normal operation of power devices. Some circuit protection mechanisms are imperfect, and components are easily damaged by overvoltage and overcurrent, reducing the reliability and service life of the circuit. To this end, we propose a GaN TVS tube interference suppression circuit. Summary of the Invention

[0004] The object of the present invention is to provide a gallium nitride TVS tube interference suppression circuit to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions: GaN TVS tube interference suppression circuit, including: An input drive circuit, the input drive circuit comprising: Transistor Q1, transistor Q2, Zener diode Z1, resistor R4, resistor R2, thermistor R3, capacitor C2, capacitor C3, diode D1, inductor L1, power supply VCC, and transformer T2 primary; One end of the voltage stabilizing diode Z1 is input with the signal GT, and the other end is connected to the resistor R4. The resistor R4 is connected in parallel with the capacitor C2. One end of the resistor R4 is connected to the base of the transistor Q1 and the base of the transistor Q2. The emitter of the transistor Q1 is connected to the emitter of the transistor Q2 , the collector of the transistor Q2 is connected to the thermistor R3 , and one end of the thermistor R3 is grounded.

[0006] Preferably, it also includes: The filter circuit consists of an inductor L1, a capacitor C1, and a resistor R1. One end of the inductor L1 is connected to the positive terminal of the power module, and the other end is connected to the gate of the MOS tube through the resistor R2. The capacitor C1 and the resistor R1 are connected in parallel, with one end connected between the inductor L1 and the resistor R2, and the other end is grounded. MOS tube, the MOS tube uses the model SI2302 MOS tube, its drain is connected to the positive electrode of the power module, the source is connected to the collector of the transistor Q1, and the gate is connected to the output end of the filter circuit through the resistor R2; the MOS tube has an integrated protection diode connected between the drain and source; The transistor Q1 has an emitter connected to the ground, a base receiving an external input signal, and a collector connected to the source of the MOS tube.

[0007] Preferably, the input drive circuit includes: Transformer T2, terminal 1 of the primary transformer T2 is connected to capacitor C3, the capacitor C3 is connected in parallel with diode D1, and one end of the capacitor C3 is connected to the emitter of transistor Q1 and the emitter of transistor Q2; Terminal 2 of the primary transformer T2 is connected to a resistor R5 , and one end of the resistor R5 is grounded.

[0008] Preferably, it also includes: An isolation drive circuit, the isolation drive circuit comprising: The transformer T2 has its winding terminals 3 and 4 connected to the drain terminal D and source terminal S of the integrated circuit U1 respectively; The integrated circuit U1 has a feedback terminal FB, a bootstrap terminal BP and a plurality of source terminals S, wherein the source terminals S are connected to each other and to ground; The feedback circuit is composed of a resistor R6, a capacitor C4, and a resistor R12. One end of the resistor R6 is connected to a diode D2. After the resistor R6 and the capacitor C4 are connected in parallel, one end is connected to the feedback FB terminal, and the other end is grounded through the resistor R12. The bootstrap circuit is composed of a capacitor C7 and a resistor R11 in parallel, and is connected between the bootstrap BP terminal and ground.

[0009] Preferably, it also includes: A power output circuit, comprising: Resistor R8, resistor R9, resistor R10, capacitor C5, capacitor C6, TVS tube Z2, TVS tube Z3, diode D4, field effect tube Q5 and transformer T1.

[0010] Preferably, the power output circuit further includes: a field effect transistor Q5, wherein the gate of the field effect transistor Q5 is connected to the emitter of the transistor Q4, the collector of the transistor Q4 is connected to a resistor R8, one end of the resistor R8 is input with a high voltage HV, the base of the transistor Q4 is connected to a resistor R9, and the resistor R9 is connected in parallel with a capacitor C5; The emitter of the transistor Q4 is further connected to a diode D4 , and one end of the diode D4 is grounded.

[0011] Preferably, TVS tubes Z2 and Z3 are connected between the field effect tube Q5 and terminal 5 of the transformer T.

[0012] Preferably, the source of the field effect transistor Q5 is grounded, the field effect transistor Q5 is connected in parallel with a resistor R10 and a capacitor C6, and one end of the capacitor C6 is connected between the drain of the field effect transistor Q5 and terminal 5 of the transformer T.

[0013] Preferably, one end of the resistor R12 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to the resistor R7, one end of the resistor R7 is connected to the diode D2, the collector of the transistor Q3 is connected to the diode D3, and one end of the diode D3 is connected to the terminal 3 of the transformer T2.

[0014] Preferably, winding terminals 1 and 2 of the transformer T2 are primary windings for receiving input voltage, and winding terminals 3 and 4 are secondary windings, which together with the integrated circuit U1 form a power conversion unit.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention absorbs interference from the outside world through TVS tubes Z1 and Z2. The two TVS tubes are connected back to back. This connection method can effectively absorb interference from the external circuit and also absorb interference from the transformer. In addition, the capacitive characteristics of the two TVS tubes are used to attenuate parasitic oscillations in the driving circuit, preventing gallium nitride from operating abnormally and improving the stability of the entire circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a structural schematic diagram of the present invention. DETAILED DESCRIPTION

[0017] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0018] See also Figure 1, GaN TVS tube interference suppression circuit, including: Input drive circuit, the input drive circuit includes: Transistor Q1, transistor Q2, Zener diode Z1, resistor R4, resistor R2, thermistor R3, capacitor C2, capacitor C3, diode D1, inductor L1, power supply VCC, and transformer T2 primary; One end of the voltage zener diode Z1 is connected to the input signal GT, and the other end is connected to the resistor R4. The resistor R4 is connected in parallel with the capacitor C2. One end of the resistor R4 is connected to the base of the transistor Q1 and the base of the transistor Q2. The emitter of the transistor Q1 is connected to the emitter of the transistor Q2, the collector of the transistor Q2 is connected to the thermistor R3, and one end of the thermistor R3 is grounded.

[0019] In the above technical solution, the input signal terminal GT is connected to the voltage regulator Z1 and the resistor R4. Z1 is used to suppress input overvoltage and protect subsequent circuits. Capacitor C2 and R4 work together to filter out high-frequency noise and ensure the purity of the input signal.

[0020] The GaN TVS tube interference suppression circuit also includes: The filter circuit consists of an inductor L1, a capacitor C1, and a resistor R1. One end of the inductor L1 is connected to the positive terminal of the power module, and the other end is connected to the gate of the MOS tube through the resistor R2. The capacitor C1 and the resistor R1 are connected in parallel, with one end connected between the inductor L1 and the resistor R2, and the other end is grounded. MOS tube, the MOS tube uses the model SI2302 MOS tube, its drain is connected to the positive electrode of the power module, the source is connected to the collector of the transistor Q1, and the gate is connected to the output end of the filter circuit through the resistor R2; the MOS tube has an integrated protection diode connected between the drain and source; Transistor Q1, whose emitter is grounded, base receives external input signal, and collector is connected to the source of MOS tube; One end of the resistor R12 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to the resistor R7, one end of the resistor R7 is connected to the diode D2, the collector of the transistor Q3 is connected to the diode D3, and one end of the diode D3 is connected to the terminal 3 of the transformer T2.

[0021] In the above technical solution, the filter circuit achieves power supply noise suppression through L1 and C1, and the resistor R1 is used to discharge C1. When the transistor Q1 is turned on, the source (S) of MOS1 is grounded, and the gate (G) is driven by the filter circuit to turn on MOS1, realizing the circuit on-off control between the drain (D) and the source (S). VCC is filtered by inductor L1, and capacitor C1 further filters out high-frequency noise. Resistor R1 ensures that capacitor C1 discharges after power is cut off to stabilize the gate voltage.

[0022] Resistor R2 limits the gate current. MOS1 (N-channel) turns on when the gate (G) voltage is higher than the source (S). The internal protection diode prevents damage from reverse voltage.

[0023] Transistor Q1 acts as a switch, and the base input signal controls its conduction state, thereby determining the source potential of MOS1, thereby controlling the conduction / cutoff of MOS1 and forming a high-efficiency switching circuit.

[0024] Input drive circuit, including: Transformer T2, terminal 1 of the primary transformer T2 is connected to capacitor C3, capacitor C3 is connected in parallel with diode D1, and one end of capacitor C3 is connected to the emitter of transistor Q1 and the emitter of transistor Q2; Terminal 2 of the primary transformer T2 is connected to a resistor R5, and one end of the resistor R5 is grounded.

[0025] In the above technical solution, the amplified signal is input to transformer T2 via capacitor C3. T2 isolates and couples the signal, enhancing the circuit's anti-interference capabilities. Diode D1 and C3 form a clamping circuit, suppressing the reverse voltage on the transformer's primary side and protecting Q1 and Q2.

[0026] Isolation drive circuit, the isolation drive circuit includes: The transformer T2 has its winding terminals 3 and 4 connected to the drain terminal D and source terminal S of the integrated circuit U1 respectively; The integrated circuit U1 has a feedback FB terminal, a bootstrap BP terminal and a plurality of source S terminals, wherein the source S terminals are connected to each other and to the ground; The feedback circuit is composed of a resistor R6, a capacitor C4 and a resistor R12. One end of the resistor R6 is connected to the diode D2. After the resistor R6 and the capacitor C4 are connected in parallel, one end is connected to the feedback FB terminal, and the other end is grounded through the resistor R12. The bootstrap circuit is composed of capacitor C7 and resistor R11 in parallel, connected between the bootstrap BP terminal and ground; The winding terminals 1 and 2 of transformer T2 are primary windings, which are used to connect to the input voltage. The winding terminals 3 and 4 are secondary windings, which together with integrated circuit U1 form a power conversion unit. Resistor R6 and capacitor C4 in the feedback circuit form a phase compensation network, which together with resistor R12 realizes feedback regulation of the output voltage; C7 and R11 in the bootstrap circuit are the bootstrap capacitor and current-limiting resistor of the integrated circuit U1, which are used to provide power for the internal drive circuit.

[0027] In the above technical solution, Transformer T2 and integrated circuit U1 form a flyback switching power supply topology to achieve isolated conversion from input voltage to output voltage.

[0028] The feedback circuit (resistor R6, capacitor C4, and resistor R12) samples the output voltage and feeds it back to the FB pin of U1, dynamically adjusting the duty cycle or frequency of the switching tube to ensure stable output voltage and adapt to a wide load range. The typical voltage regulation accuracy can reach within ±5%.

[0029] R6 and C4 form a phase compensation network to offset the phase lag caused by the transformer leakage inductance, the output capacitor equivalent series resistance, etc., so that the phase margin of the feedback loop is ≥45°, effectively suppressing high-frequency oscillations, improving the stability of the system during high-frequency operation, and avoiding excessive output voltage ripple or circuit failure.

[0030] The bootstrap circuit (capacitor C7 and resistor R11) provides a floating power supply for the internal drive circuit of U1, which is quickly charged during the switching cycle to ensure stable drive voltage, reduce drive loss, and improve switching efficiency.

[0031] Resistor R11 limits the current to protect the bootstrap capacitor C7, preventing damage from overcurrent during power-on or high-frequency switching. This enhances the circuit's surge resistance and makes it suitable for scenarios with power grid fluctuations.

[0032] Transformer T2 achieves input and output electrical isolation, meets safety standards, and is suitable for scenarios with high isolation requirements, such as medical and industrial control.

[0033] Power output circuit, power output circuit, comprising: Resistor R8, resistor R9, resistor R10, capacitor C5, capacitor C6, TVS tube Z2, TVS tube Z3, diode D4, field effect tube Q5 and transformer T1.

[0034] The power output circuit further includes: Field effect transistor Q5, the gate of field effect transistor Q5 is connected to the emitter of transistor Q4, the collector of transistor Q4 is connected to resistor R8, one end of resistor R8 is input with high voltage HV, the base of transistor Q4 is connected to resistor R9, and resistor R9 is connected in parallel with capacitor C5; the emitter of transistor Q4 is also connected to diode D4, one end of diode D4 is grounded, TVS tubes Z2 and TVS tubes Z3 are connected between field effect transistor Q5 and terminal 5 of transformer T, the source of field effect transistor Q5 is grounded, and resistor R10 and capacitor C6 are connected in parallel to field effect transistor Q5, and one end of capacitor C6 is connected between the drain of field effect transistor Q5 and terminal 5 of transformer T.

[0035] In the above technical solution, the processed signal drives Q4, which in turn drives power transistor Q5 (XG65T230HS1) via resistor R9. Zener diodes Z2 and Z3 stabilize Q4's operating voltage, while capacitor C5 filters out high-frequency interference. Diode D4 prevents reverse voltage surges and protects Q5. Resistor R10 and capacitor C6 form a snubber circuit, optimizing Q5's switching characteristics. Transformer T1 delivers power output, completing energy conversion.

[0036] While embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions, and variations may be made to these embodiments without departing from the principles and spirit of the invention, and that the scope of the invention is defined by the appended claims and their equivalents.

Claims

1. Gallium nitride TVS tube interference suppression circuit, characterized in that: include: An input drive circuit, the input drive circuit comprising: Transistor Q1, transistor Q2, Zener diode Z1, resistor R4, resistor R2, thermistor R3, capacitor C2, capacitor C3, diode D1, inductor L1, power supply VCC, and transformer T2 primary; One end of the voltage stabilizing diode Z1 is input with the signal GT, and the other end is connected to the resistor R4. The resistor R4 is connected in parallel with the capacitor C2. One end of the resistor R4 is connected to the base of the transistor Q1 and the base of the transistor Q2. The emitter of the transistor Q1 is connected to the emitter of the transistor Q2 , the collector of the transistor Q2 is connected to the thermistor R3 , and one end of the thermistor R3 is grounded.

2. The gallium nitride TVS tube interference suppression circuit according to claim 1, characterized in that: Also includes: The filter circuit consists of an inductor L1, a capacitor C1, and a resistor R1. One end of the inductor L1 is connected to the positive terminal of the power module, and the other end is connected to the gate of the MOS tube through the resistor R2. The capacitor C1 and the resistor R1 are connected in parallel, with one end connected between the inductor L1 and the resistor R2, and the other end is grounded. MOS tube, the MOS tube uses the model SI2302 MOS tube, its drain is connected to the positive electrode of the power module, the source is connected to the collector of the transistor Q1, and the gate is connected to the output end of the filter circuit through the resistor R2; the MOS tube has an integrated protection diode connected between the drain and source; The transistor Q1 has an emitter connected to the ground, a base receiving an external input signal, and a collector connected to the source of the MOS tube.

3. The gallium nitride TVS tube interference suppression circuit according to claim 2, characterized in that: The input drive circuit includes: Transformer T2, terminal 1 of the primary transformer T2 is connected to capacitor C3, the capacitor C3 is connected in parallel with diode D1, and one end of the capacitor C3 is connected to the emitter of transistor Q1 and the emitter of transistor Q2; Terminal 2 of the primary transformer T2 is connected to a resistor R5 , and one end of the resistor R5 is grounded.

4. The gallium nitride TVS tube interference suppression circuit according to claim 3, characterized in that: Also includes: An isolation drive circuit, the isolation drive circuit comprising: The transformer T2 has its winding terminals 3 and 4 connected to the drain terminal D and source terminal S of the integrated circuit U1 respectively; The integrated circuit U1 has a feedback terminal FB, a bootstrap terminal BP and a plurality of source terminals S, wherein the source terminals S are connected to each other and to ground; The feedback circuit is composed of a resistor R6, a capacitor C4, and a resistor R12. One end of the resistor R6 is connected to a diode D2. After the resistor R6 and the capacitor C4 are connected in parallel, one end is connected to the feedback FB terminal, and the other end is grounded through the resistor R12. The bootstrap circuit is composed of a capacitor C7 and a resistor R11 in parallel, and is connected between the bootstrap BP terminal and ground.

5. The gallium nitride TVS tube interference suppression circuit according to claim 4, characterized in that: Also includes: A power output circuit, comprising: Resistor R8, resistor R9, resistor R10, capacitor C5, capacitor C6, TVS tube Z2, TVS tube Z3, diode D4, field effect tube Q5 and transformer T1.

6. The gallium nitride TVS tube interference suppression circuit according to claim 5, characterized in that: The power output circuit further includes: a field effect transistor Q5, wherein the gate of the field effect transistor Q5 is connected to the emitter of the transistor Q4, the collector of the transistor Q4 is connected to a resistor R8, one end of the resistor R8 is input with a high voltage HV, the base of the transistor Q4 is connected to a resistor R9, and the resistor R9 is connected in parallel with a capacitor C5; The emitter of the transistor Q4 is further connected to a diode D4 , and one end of the diode D4 is grounded.

7. The gallium nitride TVS tube interference suppression circuit according to claim 6, characterized in that: TVS tubes Z2 and Z3 are connected between the field effect tube Q5 and terminal 5 of the transformer T.

8. The gallium nitride TVS tube interference suppression circuit according to claim 7, characterized in that: The source of the field effect tube Q5 is grounded. The field effect tube Q5 is connected in parallel with a resistor R10 and a capacitor C6. One end of the capacitor C6 is connected between the drain of the field effect tube Q5 and the terminal 5 of the transformer T.

9. The gallium nitride TVS tube interference suppression circuit according to claim 4, characterized in that: One end of the resistor R12 is connected to the base of the transistor Q3, the emitter of the transistor Q3 is connected to the resistor R7, one end of the resistor R7 is connected to the diode D2, the collector of the transistor Q3 is connected to the diode D3, and one end of the diode D3 is connected to terminal 3 of the transformer T2.

10. The gallium nitride TVS tube interference suppression circuit according to claim 4, characterized in that: The winding terminals 1 and 2 of the transformer T2 are primary windings for receiving input voltage, and the winding terminals 3 and 4 are secondary windings, which together with the integrated circuit U1 form a power conversion unit.

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