Endoscope host equipment with multiple matched handles

Abstract

The invention discloses endoscope host equipment with multiple matched handles, which comprises an interface module and a signal processing system, the interface module is constructed as an MXM interface and is used for receiving image data acquired by a handle image sensor, and the interface module comprises a digital interface and an analog interface which are respectively used for connecting a digital signal line and an analog signal line. The signal processing system is connected to the interface module and comprises an analog-to-digital converter, a synchronous FIFO module, a row cache module and an output port. Wherein the analog-to-digital converter is connected to the analog interface and is used for receiving an analog signal and converting the analog signal into a digital signal; the synchronous FIFO module is connected to the analog-to-digital converter and the digital interface and is used for receiving digital signals and realizing data buffering; the line cache module is connected to the synchronous FIFO module and is used for rearranging the image data to form the image data in the RAWData format and caching the image data; and the output port is connected to the line cache module and is used for outputting the digital signal.

Description

Technical Field

[0001] The present invention relates to the field of medical auxiliary technology, and in particular to an endoscope host device with multiple handles. Background Art

[0002] In current electronic endoscope systems, it is crucial for the host to be compatible with multiple handles. This not only improves the flexibility and efficiency of the operation, but also meets the different surgical needs and doctor preferences. If the endoscope host is compatible with multiple handles, doctors can quickly change handles on the same host according to different surgical steps and needs, thereby improving surgical efficiency, reducing surgical time, and improving the safety and success rate of the operation. In addition, according to different medical teaching and scientific research experimental scenarios, the host's compatibility with multiple handles can provide more resources and convenience, improve the effectiveness of teaching and scientific research, and provide a common platform for teaching and scientific research personnel to facilitate their various experiments and research, and promote the continuous innovation and development of endoscopic technology.

[0003] However, the signal transmission protocols and electrical parameters of different handles are different. For example, some handles use analog signals to transmit images and control information, while others use digital signals, and the encoding methods of digital signals are also different. The resolution, frame rate, color mode, etc. of the images captured by the camera modules of different handles are also different. In addition, the physical interface connecting the handle and the host varies in shape, size, pin definition, etc. For example, some endoscope handles use USB (Universal Serial Bus) interface, while others may use SDI (serial digital interface) interface or a dedicated custom interface. However, the current endoscope host only supports a single signal transmission protocol, which is difficult to be compatible with handles with different signal transmission protocols; and usually only has a single type of interface, which is difficult to be compatible with handles with different types of interfaces. Therefore, a host can often only be matched with a dedicated handle, and the compatibility is poor. In order to solve the above problems, there is an urgent need for an endoscope host device with multi-handle matching function. Summary of the Invention

[0004] The purpose of the present invention is to provide an endoscope host device with multi-handle matching, which is used to address the problem that the physical interfaces, signal transmission protocols, digital signal encoding methods, etc. of different handles are different, which makes the endoscope host device difficult to be compatible with multiple handles. By setting an interface module constructed as an MXM (Mobile PCI Express Module) interface to be compatible with different types of physical interfaces, and by setting a signal processing system to be compatible with different signal transmission protocols and encoding methods at the same time, the function of multi-handle matching is realized.

[0005] In order to achieve the above objectives, the present invention is implemented through the following technical solutions:

[0006] The present invention provides a multi-handle matching endoscope host device, comprising:

[0007] An interface module, the interface module being constructed as an MXM interface for receiving image data collected by the handle image sensor, the interface module comprising a digital interface and an analog interface, respectively used to connect a digital signal line and an analog signal line; and

[0008] A signal processing system, connected to the interface module, comprising:

[0009] an analog-to-digital converter, connected to the analog interface, for receiving an analog signal and converting it into a digital signal;

[0010] A synchronous FIFO (First Input First Output) module, connected to the analog-to-digital converter and the digital interface, for receiving digital signals and implementing data buffering;

[0011] a line buffer module, connected to the synchronous FIFO module, for rearranging the image data to form image data in a RAWData format, and buffering the image data; and

[0012] The output port is connected to the row buffer module and is used to output a digital signal.

[0013] Optionally, the interface protocol of the interface module is compatible with the MIPI (Mobile Industry Processor Interface) standard protocol.

[0014] Optionally, a synchronization module is further provided between the analog-to-digital converter and the synchronization FIFO module, for coordinating synchronization operations between the analog-to-digital converter and the synchronization FIFO module.

[0015] Optionally, a functional module is further provided between the line buffer module and the output port, and the functional module has at least dark noise processing, bad pixel correction, white balance, lens correction and digital noise reduction functions.

[0016] Optionally, the output port includes at least one of a DVP (Digital Video Port) port, an LVDS (Low Voltage Differential Signaling) port and a MIPI port.

[0017] Optionally, the signal processing system further includes a timing generator and a system control logic module, which are used to generate and output synchronous timing signals and control signals.

[0018] Optionally, in the signal processing system, the internal register group is written through an IIC (Inter-Integrated Circuit) interface.

[0019] Optionally, the endoscope host device further includes a CML signal conversion system for converting the MIPI signal into a CML (Current Mode Logic) signal.

[0020] Optionally, the CML signal conversion system includes a single-channel LVDS chip and a dual-channel LVDS chip, and an isolation circuit is provided between the single-channel LVDS chip and the dual-channel LVDS chip via a MIPI strobe switch;

[0021] The register attributes of the single-channel LVDS chip and the dual-channel LVDS chip are configured through an IIC interface.

[0022] Optionally, the endoscope host device further includes a power management system, which is used to provide a variety of voltage and current outputs for other systems and modules of the endoscope host device, and provide overvoltage, overcurrent, and overheating protection functions.

[0023] The present invention has at least the following technical effects:

[0024] By adopting the standardized card slot design of the MXM interface, it is possible to support the rapid replacement of hardware modules with different interfaces, making it convenient to expand or change the interface type according to needs and achieve compatibility with controllers with different types of physical interfaces;

[0025] By building a powerful signal processing system, the system is compatible with video signals of varying formats, resolutions, and frame rates output by a variety of image sensors. It can process control command signals from a variety of controllers, enabling precise responses to different controller functions while ensuring low latency and high fidelity in signal transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A logic diagram of a signal processing system provided by an embodiment of the present invention;

[0027] Figure 2 A schematic diagram of the steps for configuring register properties through IIC provided in one embodiment of the present invention.

[0028] Description of reference numerals:

[0029] 10: Interface module;

[0030] 11: digital interface;

[0031] 12: Analog interface;

[0032] 20: Signal processing system;

[0033] 21: analog-to-digital converter;

[0034] 22: Synchronous FIFO module;

[0035] 23: row cache module;

[0036] 24: Timing generator and system control logic module;

[0037] 25: synchronization module;

[0038] 26: IIC interface;

[0039] 31: DVP output port;

[0040] 32: LVDS output port

[0041] 33: MIPI output port. DETAILED DESCRIPTION

[0042] The following is a further detailed description of a multi-handle matching endoscope host device proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the drawings are in a very simplified form and use non-precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, please refer to the drawings. It should be noted that the structure, proportion, size, etc. illustrated in the drawings of this specification are only used to match the content disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the implementation conditions of the present invention, so they have no technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention.

[0043] This embodiment provides an endoscope host device compatible with multiple handles, including an interface module 10 and a signal processing system 20. The interface module 10 is configured as an MXM interface. By adopting a standardized card slot designed like the MXM interface, it can support the rapid replacement of hardware modules with different interfaces, facilitate the expansion or replacement of interface types according to needs, and achieve compatibility with handles with different types of physical interfaces.

[0044] The interface module 10 is used to receive image data collected by the handle image sensor. The interface protocol is compatible with the MIPI standard protocol, so that it can receive data collected by the image sensor. Since the handle image sensor is divided into a digital image sensor and an analog image sensor, the digital image sensor can directly output a digital signal in the MIPI format, while the analog image sensor outputs an analog signal. Therefore, the interface module 10 in this embodiment includes a digital interface 11 and an analog interface 12 (analog interface), which are respectively used to connect the digital signal line and the analog signal line, thereby respectively receiving the digital signal output by the digital image sensor and the analog signal output by the analog image sensor. The digital interface 11 is, for example, a 4-wire digital interface (4-wire interface).

[0045] In order to unify the link, it is necessary to convert the analog signal into a digital signal through a bridge processing circuit, that is, a signal processing system 20. Figure 1 As shown, the signal processing system 20 is connected to the interface module 10 and mainly includes an analog-to-digital converter 21, a synchronization FIFO (SYNC_FIFO) module 22, a line buffer module 23 and an output port.

[0046] Specifically, the analog-to-digital converter 21 is connected to the analog interface 12 and is used to receive analog signals and convert them into digital signals. Figure 1 As shown, in this embodiment, a 10-bit analog-to-digital converter 21 (10-bit A / D converter) can be used to convert the analog signal.

[0047] Furthermore, the synchronous FIFO module 22 is connected to the analog-to-digital converter 21 and the digital interface 11, and is used to receive the digital signal output from the digital interface 11 and the digital signal output from the analog-to-digital converter 21, and implement data buffering. Figure 1 As shown, a synchronization module 25 can also be provided between the analog-to-digital converter 21 and the synchronization FIFO module 22 to coordinate the synchronization operation between the analog-to-digital converter 21 and the synchronization FIFO module 22 to ensure that the sampling moments, data conversions or triggering actions of multiple analog-to-digital converters 21 are strictly aligned in time, thereby improving the overall system performance and data consistency.

[0048] Furthermore, the line buffer module 23 is connected to the synchronous FIFO module 22 and is used to rearrange the image data contained in the digital signal to form image data in RAWData format and cache the formed RAWData format image data. This allows the original electrical signal captured by the sensor to be directly recorded, preserving the maximum dynamic range and details.

[0049] Finally, the output port is connected to the line buffer module 23 for outputting digital signals. Figure 1 As shown, the output ports may include a DVP output port 31, an LVDS output port 32, and a MIPI output port 33, for outputting DVP signals, LVDS signals, and MIPI signals, respectively. A functional module may also be provided between the line buffer module 23 and the output ports. The functional module may, for example, have functions such as dark noise processing, bad pixel correction, white balance, lens correction, and digital noise reduction, thereby enabling further processing of the RAWData format image data according to actual needs.

[0050] In addition to the aforementioned structures, signal processing system 20 also includes a timing generator and system control logic module 24, which receives an external clock signal or an internal clock signal and generates and outputs corresponding synchronous timing signals and control signals based on the clock signals to ensure that the various components of signal processing system 20 operate in coordination according to the predetermined process. In this embodiment, the internal register set of signal processing system 20 can be written to via an I2C interface 26.

[0051] In summary, the signal processing system 20 constructed in this embodiment has powerful signal processing capabilities and is compatible with video signals of different formats, resolutions, and frame rates output by a variety of image sensors. It can process various controller control command signals, achieve precise responses to different controller functions, and ensure low latency and high fidelity in signal transmission.

[0052] On the other hand, to ensure signal uniformity and drive capability, the system needs to convert the MIPI signal into a CML signal after acquiring it to address its long-distance transmission limitations. Therefore, in this embodiment, the endoscope host device also includes a CML signal conversion system for converting the MIPI signal into a CML signal.

[0053] Specifically, the CML signal conversion system includes a single-channel LVDS chip and a dual-channel LVDS chip. The single-channel LVDS chip is exemplified by the THCV241A chip, and the dual-channel LVDS chip is exemplified by the THCV242A chip. An isolation circuit is provided between the single-channel LVDS chip and the dual-channel LVDS chip via a MIPI strobe switch. Specifically, the single-channel LVDS chip can input a clock signal to the internal clock module 26 via an external crystal oscillator and a clock input pin. Its built-in clock buffering function can enhance driving capability and compensate for signal loss. The single-channel LVDS chip can also output a clock signal via a clock output pin for use by the image sensor.

[0054] In order to complete signal transmission, the register properties of the single-channel LVDS chip and the dual-channel LVDS chip need to be configured through IIC. The specific configuration process is as follows Figure 2 As shown in the figure, the left link transmits digital image signals, while the right link transmits analog image signals. Specifically, initial configuration is required, including configuring the IIC and address of the single-channel LVDS chip and the IIC of the dual-channel LVDS chip, as well as configuring RegisterGPIO (General Purpose Input / Output), which is the configuration and control of general-purpose input / output pins through register operations.

[0055] After completing the initial configuration, it is necessary to further read the sensor's ID information and determine whether the sensor is transmitting a digital signal or an analog signal based on the ID information. If it is determined to be a digital signal, an additional step of configuring the GPIO is required. Then, the steps of configuring a single-channel LVDS chip, configuring the V-By-One interface, and configuring a dual-channel LVDS chip are performed in sequence. The V-By-One interface is a high-speed video interface that can be configured to ensure that it can stably transmit high-resolution video signals. If it is determined to be an analog signal, the steps of configuring a single-channel LVDS chip, configuring the V-By-One interface, and configuring the dual-channel LVDS chip are directly performed in sequence.

[0056] In addition, the endoscope host device in this embodiment also includes a power management system, which has a flexible power output interface and a stable power management module, which is used to provide a variety of voltage and current outputs for other systems and modules of the endoscope host device to meet the power consumption requirements of different handles and provide overvoltage, overcurrent, and overheating protection functions.

[0057] To ensure that different handle-host combinations do not pose safety risks to patients and medical staff, the endoscope host device provided in this embodiment complies with relevant medical safety standards and certifications, such as electrical safety and biocompatibility. It also has comprehensive fault diagnosis capabilities, capable of real-time monitoring of the connection status and operating status of the host and handle, thereby promptly alarming when a fault is detected and providing detailed fault information, allowing maintenance personnel to quickly locate and resolve the problem.

[0058] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0059] It should be noted that the devices and methods disclosed in the embodiments of this document may also be implemented in other ways. The device embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of the devices, methods, and computer program products according to the various embodiments of this document. In this regard, each box in the flowchart or block diagram may represent a module, program, or portion of code, wherein the module, program segment, or portion of code contains one or more executable instructions for implementing a specified logical function, and the module, program segment, or portion of code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the boxes may also occur in an order different from that marked in the accompanying drawings. For example, two consecutive boxes may actually be executed substantially in parallel, or they may sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart, may be implemented by a dedicated hardware-based system for performing the specified function or action, or may be implemented by a combination of dedicated hardware and computer instructions.

[0060] In addition, the functional modules in the various embodiments of this document may be integrated together to form an independent part, or each module may exist independently, or two or more modules may be integrated to form an independent part.

[0061] Although the present invention has been described in detail through the above preferred embodiments, it should be understood that the above description is not intended to limit the present invention. After reading the above description, various modifications and substitutions of the present invention will become apparent to those skilled in the art. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A multi-handle matching endoscope host device, characterized in that: include: An interface module, the interface module being constructed as an MXM interface for receiving image data collected by the handle image sensor, the interface module comprising a digital interface and an analog interface, respectively used to connect a digital signal line and an analog signal line; and A signal processing system, connected to the interface module, comprising: an analog-to-digital converter, connected to the analog interface, for receiving an analog signal and converting it into a digital signal; A synchronous FIFO module, connected to the analog-to-digital converter and the digital interface, for receiving digital signals and implementing data buffering; a line buffer module, connected to the synchronous FIFO module, for rearranging the image data to form image data in a RAWData format, and buffering the image data; and The output port is connected to the row buffer module and is used to output a digital signal.

2. The endoscope host device according to claim 1, characterized in that: The interface protocol of the interface module is compatible with the MIPI standard protocol.

3. The endoscope host device according to claim 1, wherein: A synchronization module is further provided between the analog-to-digital converter and the synchronization FIFO module, for coordinating synchronization operations between the analog-to-digital converter and the synchronization FIFO module.

4. The endoscope host device according to claim 1, characterized in that: A functional module is further provided between the line buffer module and the output port, and the functional module has at least dark noise processing, bad pixel correction, white balance, lens correction and digital noise reduction functions.

5. The endoscope host device according to claim 1, wherein: The output port includes at least one of a DVP port, a LVDS port and a MIPI port.

6. The endoscope host device according to claim 1, characterized in that: The signal processing system further includes a timing generator and a system control logic module, which are used to generate and output synchronous timing signals and control signals.

7. The endoscope host device according to claim 1, characterized in that: In the signal processing system, the internal register group is written through the IIC interface.

8. The endoscope host device according to claim 5, characterized in that: A CML signal conversion system is also included for converting MIPI signals into CML signals.

9. The endoscope host device according to claim 8, characterized in that: The CML signal conversion system includes a single-channel LVDS chip and a dual-channel LVDS chip, wherein an isolation circuit is provided between the single-channel LVDS chip and the dual-channel LVDS chip via a MIPI strobe switch; The register attributes of the single-channel LVDS chip and the dual-channel LVDS chip are configured through an IIC interface.

10. The endoscope host device according to claim 1, wherein: It also includes a power management system, which is used to provide multiple voltage and current outputs for other systems and modules of the endoscope host device, and provide overvoltage, overcurrent, and overheating protection functions.

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