Single-core cable communication circuits between logging instruments, logging instruments and logging systems

Abstract

The present invention discloses a single-core cable communication circuit between well logging instruments, a well logging instrument, and a well logging system. The single-core cable communication circuit between well logging instruments includes: a single-core cable interface, a sampling inductor, a DC blocking capacitor, a transmitting drive circuit, a receiving signal conditioning circuit, and a power supply module. The receiving signal conditioning circuit includes: a receiving end digital interface, and the transmitting drive circuit includes: a first transmitting end digital interface and a second transmitting end digital interface. The single-core cable interface is respectively connected to the first end of the DC blocking capacitor and the first end of the sampling inductor. The second end of the DC blocking capacitor is respectively connected to the receiving signal conditioning circuit and the transmitting drive circuit. The second end of the sampling inductor is connected to the power supply module. This circuit can supply DC power to the well logging instrument through the single-core cable while realizing half-duplex communication between the well logging instruments. It has the characteristics of simple circuit structure and easy implementation.

Description

Technical Field

[0001] The present invention relates to the field of exploration technology, and in particular to a single-core cable communication circuit between well logging instruments, a well logging instrument and a well logging system. Background Art

[0002] Currently, stable communication between different instruments in geophysical and oil and gas exploration and development processes is a critical technical specification. Conventional technology relies on hard-wiring between instruments. However, with the advancement of drilling technology and the prevalence of deep and ultra-deep wells, smaller wellbore sizes and higher temperatures are driving higher demands on communication technology between instruments. Therefore, a communication circuit is needed to enable communication between logging instruments. Summary of the Invention

[0003] In view of the above problems, the present invention is proposed to provide a single-core cable communication circuit between logging instruments, a logging instrument and a logging system that overcome the above problems or at least partially solve the above problems.

[0004] According to one aspect of the present invention, a single-core cable communication circuit between logging instruments is provided, which is applied to a first logging instrument. The single-core cable communication circuit between logging instruments includes: a single-core cable interface, a sampling inductor, a DC blocking capacitor, a transmitting drive circuit, a receiving signal conditioning circuit, and a power module. The receiving signal conditioning circuit includes: a receiving end digital interface, and the transmitting drive circuit includes: a first transmitting end digital interface and a second transmitting end digital interface. The single-core cable interface is respectively connected to a first end of the DC blocking capacitor and a first end of the sampling inductor, and the second end of the DC blocking capacitor is respectively connected to the receiving signal conditioning circuit and the transmitting drive circuit. The second end of the sampling inductor is connected to the power module.

[0005] a single-core cable interface, connecting the first well logging instrument with the single-core cable interface of the second well logging instrument via the single-core cable, and configured to receive a high-voltage direct current signal transmitted by the second well logging instrument via the single-core cable, and to receive a first digital signal transmitted by the second well logging instrument via the single-core cable or to send a second digital signal to the second well logging instrument via the single-core cable;

[0006] a sampling inductor, configured to filter the first digital signal, output a high-voltage direct current signal, and output the signal to the power module, so that the power module performs electrical signal conversion processing and outputs a low-voltage direct current signal;

[0007] a receiving signal conditioning circuit, configured to perform signal conditioning on the first digital signal transmitted by the DC blocking capacitor to obtain a single-ended digital signal, and transmit the single-ended digital signal to a digital processing chip in the first logging instrument through a receiving-end digital interface for decoding;

[0008] a transmitting driving circuit, configured to receive a second digital signal when transmitting data through the first transmitting end digital interface and the second transmitting end digital interface;

[0009] The DC blocking capacitor is used to block the high-voltage DC signal during data reception and output a first digital signal; and, during data transmission, couple the second digital signal transmitted by the transmission drive circuit to the single-core cable interface.

[0010] Furthermore, the single-core cable interface includes: a single-core cable uplink interface and a single-core cable downlink interface;

[0011] The single-core cable uplink interface is respectively connected to the first end of the DC blocking capacitor and the first end of the sampling inductor;

[0012] The single-core cable communication circuit between logging instruments further includes: a switch circuit, wherein the switch circuit includes a signal control interface;

[0013] The switch circuit is connected to the single-core cable uplink interface and the single-core cable downlink interface respectively;

[0014] The switch circuit is used to control the on / off between the single-core cable upstream interface and the single-core cable downstream interface by controlling the voltage value of the digital control signal applied to the signal control interface;

[0015] The DC blocking capacitor is further used to couple the second digital signal transmitted by the transmission driving circuit to the single-core cable uplink interface during data transmission.

[0016] Furthermore, the switch circuit further comprises: a PMOS transistor, an NMOS transistor;

[0017] The signal control interface is connected to the gate G of the NMOS transistor, and the source S of the NMOS transistor is grounded; the drain D of the NMOS transistor is connected to the gate G of the PMOS transistor via a resistor, the single-core cable upstream interface is connected to the source S of the PMOS transistor, and the drain D of the PMOS transistor is connected to the single-core cable downstream interface;

[0018] The switching circuit is used to: control the connection between the single-core cable upstream interface and the single-core cable downstream interface by pulling up the digital control signal applied to the signal control interface to a first voltage; and control the disconnection between the single-core cable upstream interface and the single-core cable downstream interface by pulling down the digital control signal applied to the signal control interface to a second voltage.

[0019] Furthermore, the receiving signal conditioning circuit further includes: a signal conditioning circuit connected to the DC blocking capacitor, configured to perform signal conditioning on the first digital signal output by the DC blocking capacitor to obtain a single-ended digital signal;

[0020] The signal conditioning circuit includes: a first operational amplifier, a second operational amplifier, and a resistor. The first operational amplifier and the second operational amplifier are connected in series. The positive input terminal of the first operational amplifier is connected to the second end of the DC blocking capacitor. The negative input terminal of the first operational amplifier is connected to GND through a resistor. The output terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier. The positive input terminal of the second operational amplifier is connected to GND through a resistor. The output terminal of the second operational amplifier is connected to the digital interface of the receiving end.

[0021] Furthermore, the transmitting drive circuit further includes: a PMOS transistor, an NMOS transistor, a capacitor, a resistor, and a diode, wherein the first transmitting-end digital interface is connected to the gate G of the PMOS transistor via the capacitor, the source S of the PMOS transistor is connected to the +12V voltage via the resistor, the drain D of the PMOS transistor is connected to the second end of the DC-blocking capacitor via the diode and the resistor, the second transmitting-end digital interface is connected to the gate G of the NMOS transistor via the capacitor, the drain D of the NMOS transistor is connected to the second end of the DC-blocking capacitor via the diode and the resistor, and the source S of the NMOS transistor is connected to the -12V voltage via the resistor;

[0022] The transmission drive circuit is further used to: receive a second digital signal when transmitting data through the first transmission end digital interface and the second transmission end digital interface, and the PMOS transistor and the NMOS transistor drive the second digital signal.

[0023] Furthermore, the waveform amplitude of the first digital signal is ±9 VDC or ±12 VDC; the waveform amplitude of the second digital signal is ±9 VDC or ±12 VDC.

[0024] Furthermore, the circuit is used to implement half-duplex communication between the first well logging tool and the second well logging tool.

[0025] According to another aspect of the present invention, a well logging instrument is provided. The well logging instrument includes the above-mentioned inter-logging instrument single-core cable communication circuit.

[0026] According to another aspect of the present invention, a well logging system is provided, comprising a transmission sub and a plurality of the above-mentioned well logging instruments cascaded via a single-core cable, wherein the transmission sub and the well logging instruments are connected via the single-core cable;

[0027] The transmission sub includes: a high-voltage DC power supply, a single-core cable interface, a sampling inductor, a DC blocking capacitor, a transmitting drive circuit, a receiving signal conditioning circuit, and a power supply module, wherein the high-voltage DC power supply is connected to the first end of the sampling inductor, the second end of the sampling inductor is respectively connected to the single-core cable interface and the first end of the DC blocking capacitor, the second end of the DC blocking capacitor is respectively connected to the receiving signal conditioning circuit and the transmitting drive circuit, and the high-voltage DC power supply is connected to the power supply module; the receiving signal conditioning circuit includes: a receiving end digital interface, and the transmitting drive circuit includes: a first transmitting end digital interface and a second transmitting end digital interface;

[0028] A single-core cable interface, connecting the transmission sub to the single-core cable interface of the logging instrument via the single-core cable, for transmitting a high-voltage direct current signal to the logging instrument via the single-core cable, and for sending a first digital signal to the logging instrument via the single-core cable, or for receiving a second digital signal transmitted by the logging instrument via the single-core cable;

[0029] a sampling inductor, used for filtering the first digital signal or the second digital signal;

[0030] a receiving signal conditioning circuit, configured to perform signal conditioning on the second digital signal transmitted by the DC blocking capacitor to obtain a single-ended digital signal, and transmit the single-ended digital signal to a digital processing chip in the transmission short section through a receiving end digital interface for decoding;

[0031] a transmitting driving circuit, configured to receive a first digital signal when transmitting data through the first transmitting end digital interface and the second transmitting end digital interface;

[0032] The DC blocking capacitor is used to block the high-voltage DC signal during data reception and output a second digital signal; and, during data transmission, couple the first digital signal transmitted by the transmission drive circuit to the single-core cable interface.

[0033] Furthermore, the transmission sub further comprises: a switch circuit, wherein the switch circuit comprises a signal control interface;

[0034] The switch circuit is connected to the second end of the sampling inductor and the single-core cable interface respectively;

[0035] The switch circuit is used to control the on / off connection between the high-voltage DC power supply and the single-core cable interface by controlling the voltage value of the digital control signal applied to the signal control interface.

[0036] This circuit can supply DC power to the logging instrument through a single-core cable and realize half-duplex communication between the logging instruments. It has the characteristics of simple circuit structure and easy implementation.

[0037] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0039] Figure 1 A circuit diagram of a single-core cable communication circuit between logging instruments according to an embodiment of the present invention is shown;

[0040] Figure 2 A schematic structural diagram of a well logging system according to an embodiment of the present invention is shown;

[0041] Figure 3 A circuit diagram of a transmission sub in a well logging system according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] Exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0043] Figure 1 FIG1 shows a circuit diagram of a single-core cable communication circuit between logging instruments according to an embodiment of the present invention. The single-core cable communication circuit between logging instruments is applied to a first logging instrument, such as Figure 1 As shown, the single-core cable communication circuit between the logging instruments includes: a single-core cable interface ( Figure 1 ), a sampling inductor 101, a DC blocking capacitor 102, a transmitting drive circuit 103, a receiving signal conditioning circuit 104, and a power supply module 105, wherein the receiving signal conditioning circuit includes: a receiving end digital interface, the transmitting drive circuit includes: a first transmitting end digital interface and a second transmitting end digital interface, the single-core cable interface is respectively connected to the first end of the DC blocking capacitor and the first end of the sampling inductor, the second end of the DC blocking capacitor is respectively connected to the receiving signal conditioning circuit and the transmitting drive circuit, and the second end of the sampling inductor is connected to the power supply module.

[0044] A single-core cable interface connects the first logging instrument to the single-core cable interface of the second logging instrument via a single-core cable, and is used to receive a high-voltage direct current signal transmitted by the second logging instrument via the single-core cable, and to receive a first digital signal transmitted by the second logging instrument via the single-core cable or to send a second digital signal to the second logging instrument via the single-core cable.

[0045] In this embodiment, a single-core cable communication cable between logging instruments is used for the first logging instrument, and the logging instrument connected to the first logging instrument via the single-core cable is referred to as the second logging instrument. It should be noted that the first logging instrument and the second logging instrument are identical logging instruments, and the first logging instrument and the second logging instrument are only relative. For example, there are three logging instruments, namely logging instrument 1, logging instrument 2, and logging instrument 3. Logging instrument 1, logging instrument 2, and logging instrument 3 are connected via a single-core cable. Logging instrument 2 is the first logging instrument, and logging instrument 1 is the second logging instrument; logging instrument 3 is the first logging instrument, and logging instrument 2 is the second logging instrument. The single-core cable interface is the signal transmission interface of the logging instrument. The single-core cable interface of the two logging instruments is connected via a single-core cable to achieve communication between the logging instruments.

[0046] A single-core cable interface connects a first logging instrument to a second logging instrument via a single-core cable, and is used to receive a high-voltage DC signal transmitted by the second logging instrument via the single-core cable, as well as to receive a first digital signal transmitted by the second logging instrument via the single-core cable or to send a second digital signal to the second logging instrument via the single-core cable. The signal received by the single-core cable interface consists of two superimposed parts, mainly including a high-voltage DC signal and a first digital signal. The high-voltage DC signal is generally above 100VDC, for example, 110VDC. The first digital signal and the second digital signal are AC signals.

[0047] The sampling inductor 101 is used to filter the first digital signal, output a high-voltage DC signal, and output it to the power module for the power module to convert the signal into a low-voltage DC signal.

[0048] In order to avoid the influence of the AC signal on the power module in the circuit, the first digital signal needs to be filtered out. The sampling inductor has the characteristic of passing DC and blocking AC. Therefore, a sampling inductor is set between the single-core cable interface and the power module. The first end of the sampling inductor is connected to the single-core cable interface. Due to the characteristic of the sampling inductor passing DC and blocking AC, the first digital signal input to the sampling inductor is blocked. The sampling inductor ultimately only transmits a high-voltage DC signal and transmits the high-voltage DC signal to the power module. The power module performs electrical signal conversion processing, converts the high-voltage DC signal into a low-voltage DC signal, and outputs the low-voltage DC signal to supply power to the power-consuming part in the circuit.

[0049] The receiving signal conditioning circuit 104 is used to condition the first digital signal transmitted by the DC blocking capacitor to obtain a single-ended digital signal, and transmit the single-ended digital signal to the digital processing chip in the first logging tool through the receiving end digital interface for decoding processing.

[0050] During the data reception process, the first digital signal transmitted by the DC blocking capacitor is a bipolar pulse signal. The receiving signal conditioning circuit performs signal conditioning on the first digital signal output by the DC blocking capacitor. Through signal conditioning, the bipolar pulse signal is converted into a single-ended digital signal, for example, into a positive pulse signal, and the single-ended digital signal is transmitted to the digital processing chip in the first logging instrument through the receiving end digital interface for decoding processing. For example, the receiving end digital interface is represented by RX. The single-ended digital signal is transmitted to the digital processing chip through RX for decoding information. Through the decoding processing, it can be identified what specific processing the logging instrument needs to do.

[0051] In an optional embodiment of the present invention, the receiving signal conditioning circuit further includes: a signal conditioning circuit connected to the DC blocking capacitor, configured to perform signal conditioning on the first digital signal output by the DC blocking capacitor to obtain a single-ended digital signal;

[0052] The signal conditioning circuit includes: a first operational amplifier, a second operational amplifier, and a resistor. The first operational amplifier and the second operational amplifier are connected in series. Figure 1 As shown, the first operational amplifier is represented by U1, and the second operational amplifier is represented by U2. The first operational amplifier and the second operational amplifier can be AD817AN model operational amplifiers. The positive input terminal of the first operational amplifier is connected to the second end of the DC blocking capacitor, the negative input terminal of the first operational amplifier is connected to GND through a resistor, the output terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier, the positive input terminal of the second operational amplifier is connected to GND through a resistor, and the output terminal of the second operational amplifier is connected to the receiving end digital interface.

[0053] In addition, the receiving signal conditioning circuit also includes: diodes and capacitors. Figure 1As shown, the receiving signal conditioning circuit includes: a first diode CR9, a second diode CR10, a third diode CR12, a fourth diode CR13, a fifth diode CR16, a sixth diode CR17, a seventh diode CR18, an eighth diode CR19, a ninth diode CR20, a tenth diode CR21, a first resistor R7, a second resistor R12, a third resistor R13, a fourth resistor R18, a fifth resistor R19, a sixth resistor R20, a seventh resistor R21, an eighth resistor R22, a ninth resistor R23, a first capacitor C 10. The second capacitor C11, the third capacitor C7, the diode can be BAS32L, the capacitance value of C10 is 0.1uF, the capacitance value of C11 is 100pF, the capacitance value of C7 is 10pF, the resistance value of resistor R7 is 10K, the resistance value of R12 is 2K15, the resistance value of R13 is 3K16, the resistance value of R18 is 2K15, the resistance value of R19 is 2K15, the resistance value of R20 is 2K15, the resistance value of R21 is 38K3, the resistance value of R22 is 14K7, and the resistance value of R23 is 464R. The circuit formed by diodes CR9 and CR10 is mainly to prevent reverse breakdown; the circuit formed by R18, C7, CR12, CR13, CR16, and CR17 is mainly to play the role of circuit protection; the circuit formed by CR18, CR19, CR20, and CR21 is mainly to prevent reverse breakdown; the circuit formed by R20, R21, R22, and R23 is mainly to play the role of voltage division.

[0054] Specifically, the first operational amplifier is represented by U1, the second operational amplifier is represented by U2, and the receiving end digital interface RX;

[0055] The first end of the first capacitor C10 is connected to the second end of the DC blocking capacitor C2, and the first capacitor C10 is connected in series with the first resistor R7, that is, the second end of the first capacitor C10 is connected to the first end of the first resistor R7, and the second end of the first resistor R7 is respectively connected to the anode of the first diode CR9, the cathode of the second diode CR10, and the positive input terminal of the first operational amplifier U1. The cathode of the first diode CR9 is connected to a +12V voltage, and the cathode of the second diode CR10 is connected to a -12V voltage. The positive input terminal of the first operational amplifier U1 is grounded through the second resistor R12. GND, the negative input terminal of the first operational amplifier U1 is connected to the ground GND through the third resistor R13, the output terminal of the first operational amplifier U1 is connected to the negative input terminal of the second operational amplifier U2 through the fifth resistor R19, the positive input terminal of the second operational amplifier U2 is grounded through the sixth resistor R20, the positive input terminal of the second operational amplifier U2 is connected to the -5V voltage through the seventh resistor R21, the output terminal of the second operational amplifier U2 is connected to the receiving end digital interface RX through the ninth resistor R23, and the eighth resistor R22 is connected between the positive input terminal and the output terminal of the second operational amplifier U2.

[0056] The second capacitor C11 is connected in parallel with the first resistor R7, the fourth resistor R18 is connected between the negative input terminal and the output terminal of the first operational amplifier U1, the third capacitor C7 is connected between the negative input terminal and the output terminal of the first operational amplifier U1, the third diode CR12 and the fifth diode CR16 are connected in series, the cathode of the third diode CR12 is connected to the negative input terminal of the first operational amplifier U1, the anode of the fifth diode CR16 is connected to the output terminal of the first operational amplifier U1, the fourth diode CR13 and the sixth diode CR17 are connected in series, the anode of the fourth diode CR13 is connected to the negative input terminal of the first operational amplifier U1, and the cathode of the sixth diode CR17 is connected to the output terminal of the first operational amplifier U1.

[0057] The seventh diode CR18 and the ninth diode CR20 are connected in series, the cathode of the seventh diode CR18 is grounded, the anode of the ninth diode CR20 is connected to the negative input terminal of the second operational amplifier U2, the eighth diode CR19 and the tenth diode CR21 are connected in series, the anode of the eighth diode CR19 is grounded, and the cathode of the tenth diode CR21 is connected to the negative input terminal of the second operational amplifier U2.

[0058] The transmission driving circuit 103 is configured to receive a second digital signal when transmitting data through the first transmitting end digital interface and the second transmitting end digital interface.

[0059] Specifically, the transmitting end digital interface includes a first transmitting end digital interface and a second transmitting end digital interface, such as Figure 1 As shown, the first transmitting end digital interface is represented as TX+, and the second transmitting end digital interface is represented as TX-;

[0060] The first transmitting end digital interface and the second transmitting end digital interface each transmit one digital signal, and the two digital signals together constitute a second digital signal, wherein the two digital signals have different normal levels. The second digital signal is a double-pulse digital signal.

[0061] When sending data, the first sending end digital interface and the second sending end digital interface are used to receive a second digital signal, and the second digital signal is transmitted to the DC blocking capacitor.

[0062] The transmitting drive circuit also includes: a PMOS transistor, an NMOS transistor, a capacitor, a resistor, and a diode. Figure 1As shown, Q4B is a PMOS transistor and Q3B is an NMOS transistor, wherein the first transmitting-end digital interface is connected to the gate G of the PMOS transistor Q4B through a capacitor, the source S of the PMOS transistor Q4B is connected to the +12V voltage through a resistor, and the drain D of the PMOS transistor Q4B is connected to the second end of the DC-blocking capacitor through a diode and a resistor. The second transmitting-end digital interface is connected to the gate G of the NMOS transistor Q3B through a capacitor, the drain D of the NMOS transistor Q3B is connected to the second end of the DC-blocking capacitor through a diode and a resistor, and the source S of the NMOS transistor Q3B is connected to the -12V voltage through a resistor.

[0063] The transmit driver circuit is further configured to receive a second digital signal when transmitting data via the first transmit digital interface TX+ and the second transmit digital interface TX-, and drive the second digital signal via a PMOS transistor Q4B and an NMOS transistor Q3B. The PMOS transistor Q4B drives one of the second digital signals received by the first transmit digital interface TX+, and the NMOS transistor Q3B drives the other of the second digital signals received by the first transmit digital interface TX+. The PMOS transistor can be an IRF9953 transistor, and the NMOS transistor can be an IRF9956 transistor.

[0064] Among them, the sending drive circuit includes: a tenth resistor R5, an eleventh resistor R8, a twelfth resistor R9, a thirteenth resistor R10, a fourteenth resistor R11, a fifteenth resistor R14, a sixteenth resistor R15, a seventeenth resistor R16, and an eighteenth resistor R17; a fourth capacitor C3, a fifth capacitor C4, a sixth capacitor C5, a seventh capacitor C6, an eighth capacitor C8, and a ninth capacitor C9; an eleventh diode CR5, a twelfth diode CR6, a thirteenth diode CR14, and a fourteenth diode CR15. The resistor R5 is 20R 1W; R8 is 10R1W; R9 is 10R1W, R10 is 46R4; R11 is 46R4; R14 is 4R7 1W; R15 is 10K; R16 is 10K; and R17 is 4R7. 1W; capacitor C3 is 0.1uF, C4 is 0.1uF, C5 is 47uF / 20V, C6 is 47uF / 20V, C8 is 0.1uF, C9 is 0.1uF; the diode can be BAS32L.

[0065] Specifically, if Figure 1As shown, the first transmitting end digital interface TX+ is connected to the first end of the eighth capacitor C8, the second end of the eighth capacitor C8 is respectively connected to the first end of the fourteenth resistor R11, the first end of the sixteenth resistor R15, and the anode of the thirteenth diode CR14, the second end of the sixteenth resistor R15, the cathode of the thirteenth diode CR14, and the source S of the PMOS transistor Q4B are connected to the first node, the first node is connected to the +12V voltage through the fifteenth resistor R14, the second end of the fourteenth resistor R11 is connected to the gate G of the PMOS transistor Q4B, the drain D of the PMOS transistor Q4B is connected to the first end of the eleventh resistor R8, the eleventh resistor R8 is connected in series with the eleventh diode CR5, and the cathode of the eleventh diode CR5 is connected to the first end of the tenth resistor R5.

[0066] The second transmitting end digital interface TX- is connected to the first end of the ninth capacitor C9. The second end of the ninth capacitor C9 is respectively connected to the first end of the seventeenth resistor R16, the first end of the thirteenth resistor R10, and the cathode of the fourteenth diode CR15. The second end of the seventeenth resistor R16, the positive and negative electrodes of the fourteenth diode CR15, and the source S of the NMOS transistor Q3B are connected to the second node. The second node is connected to a -12V voltage through the eighteenth resistor R17. The second end of the thirteenth resistor R10 is connected to the gate G of the NMOS transistor Q3B. The drain D of the NMOS transistor Q3B is connected to the first end of the twelfth resistor R9. The second end of the twelfth resistor R9 is connected to the cathode of the twelfth diode CR6. The anode of the twelfth diode CR6 is connected to the first end of the tenth resistor R5. The second end of the tenth resistor R5 is connected to the second end of the DC blocking capacitor.

[0067] A first end of the fourth capacitor C3 and a first end of the sixth capacitor C5 are respectively connected to the first node, a second end of the fourth capacitor C3 and a second end of the sixth capacitor C5 are respectively grounded, a first end of the fifth capacitor C4 and a first end of the seventh capacitor C6 are respectively grounded, and a second end of the fifth capacitor C4 and a second end of the seventh capacitor C6 are respectively connected to the second node.

[0068] The DC blocking capacitor 102 is used to block the high-voltage DC signal during data reception and output a first digital signal; and to couple the second digital signal transmitted by the sending drive circuit to the single-core cable interface during data transmission.

[0069] Capacitors have the characteristic of passing AC and blocking DC. To prevent the high-voltage DC signal from affecting the receiving signal conditioning circuit, the transmitting drive circuit, and the digital signal transmission, it is necessary to block the high-voltage DC signal. Therefore, a DC blocking capacitor is provided. The isolation capacitor is connected to the single-core cable interface, the receiving signal conditioning circuit, and the transmitting drive circuit via a wire. The DC blocking capacitor uses a 330nF, 200V capacitor. During the data reception process, the DC blocking capacitor blocks the transmitted high-voltage DC signal and allows the first digital signal to pass through. Therefore, the DC blocking capacitor outputs the first digital signal to the receiving signal conditioning circuit. During the data transmission process, the transmitting drive circuit transmits the second digital signal to the DC blocking capacitor. The DC blocking capacitor couples the second digital signal transmitted by the transmitting drive circuit to the single-core cable interface for transmission to the second logging instrument via the single-core cable interface.

[0070] In this embodiment, the first digital signal and the second digital signal are Manchester encoded, wherein the encoding clock frequency is 4 MHz, and the waveform amplitude is ±9 VDC or ±12 VDC.

[0071] The single-core cable communication circuit between logging instruments uses a single-core cable to simultaneously supply DC power to the logging instruments and enable half-duplex communication between the instruments. Specifically, this circuit enables half-duplex communication between a first logging instrument and a second logging instrument. This circuit has a simple structure, is easy to implement, and can be used in high-temperature environments. It can accommodate cables up to 15 meters long and operates in temperatures up to 175°C.

[0072] In an optional embodiment of the present invention, the single-core cable interface includes: a single-core cable uplink interface (such as Figure 1 Port in the upper part), single-core cable downstream interface (such as Figure 1 The single-core cable uplink interface is connected to the first end of the DC blocking capacitor and the first end of the sampling inductor respectively;

[0073] The circuit further includes: a switch circuit 106, wherein the switch circuit includes a signal control interface;

[0074] The switch circuit is connected to the single-core cable uplink interface and the single-core cable downlink interface respectively;

[0075] The switch circuit is used to control the on / off between the single-core cable upstream interface and the single-core cable downstream interface by controlling the voltage value of the digital control signal applied to the signal control interface;

[0076] The DC blocking capacitor is further used to couple the second digital signal transmitted by the transmission driving circuit to the single-core cable uplink interface during data transmission.

[0077] The logging instruments can be cascaded via a single-core cable. The single-core cable upstream interface in the first logging instrument is connected to the single-core cable downstream interface in the second logging instrument via a single-core cable. The single-core cable downstream interface in the first logging instrument is connected to the single-core cable upstream interface of other logging instruments. The on / off between the single-core cable upstream interface and the single-core cable downstream interface can be controlled by the signal control interface of the switching circuit in the first logging instrument, thereby realizing whether to power on other logging instruments cascaded with the first logging instrument.

[0078] By controlling the voltage value applied to the digital control signal ("Ctrl" signal), the connection and disconnection of the switch circuit can be achieved, thereby controlling the conduction and disconnection between the single-core cable upstream interface and the single-core cable downstream interface. Specifically, when the logging instrument is actually working, the current logging instrument can control whether to power the next-level logging instrument through the "Ctrl" signal. The purpose of this method is to achieve automatic allocation of the logging instrument address, especially when multiple cascaded logging instruments are of the same type (typically such as VSP). The instrument itself does not have an address and needs to be automatically allocated by the transmission short section connected to the logging instrument after power is turned on. If this power supply method is not adopted, all the instruments on the ground will be powered on. When the transmission short section sends a command to the instrument below, all the logging instruments will respond, which will inevitably lead to communication confusion.

[0079] When there is a single-core cable uplink interface and a single-core cable downlink interface, the DC blocking capacitor is further used to couple the second digital signal transmitted by the transmission drive circuit to the single-core cable uplink interface during data transmission.

[0080] In an optional embodiment of the present invention, the switch circuit further comprises: a PMOS transistor, an NMOS transistor;

[0081] The signal control interface is connected to the gate G of the NMOS transistor, and the source S of the NMOS transistor is grounded; the drain D of the NMOS transistor is connected to the gate G of the PMOS transistor via a resistor, the single-core cable upstream interface is connected to the source S of the PMOS transistor, and the drain D of the PMOS transistor is connected to the single-core cable downstream interface;

[0082] The switching circuit is used to: control the connection between the single-core cable upstream interface and the single-core cable downstream interface by pulling up the digital control signal applied to the signal control interface to a first voltage; and control the disconnection between the single-core cable upstream interface and the single-core cable downstream interface by pulling down the digital control signal applied to the signal control interface to a second voltage.

[0083] The voltage at the single-core cable upstream interface is 110V. Under normal circumstances, the digital control signal Ctrl is pulled down to 0V, the NMOS tube Q1 is not conducting, and the G pole and S pole voltages of the PMOS tube Q2 are basically equal, that is, Q2 is also not conducting. At this time, the single-core cable upstream interface and the single-core cable downstream interface are disconnected, that is, no power is supplied to the next-level logging instrument; when the Ctrl signal is pulled up to a first voltage, where the first voltage is greater than the turn-on voltage of the NMOS tube Q1, the NMOS tube Q1 is turned on, and the G pole of the PMOS tube Q2 is greater than the S pole voltage, Q2 is turned on, and the single-core cable upstream interface and the single-core cable downstream interface are connected.

[0084] It should be noted that with the development of technology, logging instruments may have their own unique instrument addresses. In this case, there is no need to transmit the short-section allocation address, and the logging instruments can be powered on at the same time without switching circuits.

[0085] This circuit supplies DC power to logging instruments through a single-core cable while also enabling half-duplex communication between logging instruments. It has a simple circuit structure and is easy to implement. Furthermore, the longest cable length between instruments can be 15 meters, and it can be used in high-temperature environments, for example, at 200°C.

[0086] One embodiment of the present invention provides a well logging instrument, which includes Figure 1 The single-core cable communication circuit between logging instruments shown in the figure. The logging instruments here can be Figure 1 The first logging tool in the illustrated embodiment, Figure 1 The first logging tool and the second logging tool are the same tool.

[0087] Figure 2 A schematic structural diagram of a well logging system according to an embodiment of the present invention is shown. Figure 3 FIG. 1 shows a circuit diagram of a transmission sub in a well logging system according to an embodiment of the present invention. Figure 2 and Figure 3 As shown, the logging system includes a transmission sub 201 and a plurality of logging instruments (eg, Figure 2 Logging instrument 1, logging instrument 2, logging instrument 3), wherein the transmission sub and the logging instrument are connected via a single-core cable;

[0088] The transmission short section 201 includes: a high voltage DC power supply 301, a single core cable interface ( Figure 3port) 302 in, sampling inductor 303, blocking capacitor 304, sending drive circuit 305, receiving signal conditioning circuit 306, power supply module 307, wherein the high-voltage DC power supply is connected to the first end of the sampling inductor, the second end of the sampling inductor is respectively connected to the single-core cable interface and the first end of the blocking capacitor, the second end of the blocking capacitor is respectively connected to the receiving signal conditioning circuit and the sending drive circuit, and the high-voltage DC power supply is connected to the power supply module; the receiving signal conditioning circuit includes: a receiving end digital interface, and the sending drive circuit includes: a first sending end digital interface and a second sending end digital interface;

[0089] A single-core cable interface, connecting the transmission sub to the single-core cable interface of the logging instrument via the single-core cable, for transmitting a high-voltage direct current signal to the logging instrument via the single-core cable, and for sending a first digital signal to the logging instrument via the single-core cable, or for receiving a second digital signal transmitted by the logging instrument via the single-core cable;

[0090] a sampling inductor, used for filtering the first digital signal or the second digital signal;

[0091] a receiving signal conditioning circuit, configured to perform signal conditioning on the second digital signal transmitted by the DC blocking capacitor to obtain a single-ended digital signal, and transmit the single-ended digital signal to a digital processing chip in the transmission short section through a receiving end digital interface for decoding;

[0092] a transmitting driving circuit, configured to receive a first digital signal when transmitting data through the first transmitting end digital interface and the second transmitting end digital interface;

[0093] The DC blocking capacitor is used to block the high-voltage DC signal during data reception and output a second digital signal; and, during data transmission, couple the first digital signal transmitted by the transmission drive circuit to the single-core cable interface.

[0094] The ground system supplies high voltage DC power to the transmission short section through cables and bridles. For the convenience of description, this high voltage DC power supply is defined as POWER, which is usually as high as 110V. Figure 3 The power module converts the power into the low-voltage DC power required by the internal circuits.

[0095] Figure 3 The port in the figure is the single-core cable interface at the bottom of the transmission short section. The outer shell of the transmission short section and the outer sheath of the cable are the ground wires.

[0096] Optionally, the transmission sub further includes: a switch circuit 308, wherein the switch circuit includes a signal control interface;

[0097] The switch circuit is connected to the second end of the sampling inductor and the single-core cable interface respectively;

[0098] The switch circuit is used to control the on / off connection between the high-voltage DC power supply and the single-core cable interface by controlling the voltage value of the digital control signal applied to the signal control interface.

[0099] Optionally, the switch circuit further includes: a PMOS transistor and an NMOS transistor;

[0100] The signal control interface is connected to the gate G of the NMOS transistor, and the source S of the NMOS transistor is grounded; the drain D of the NMOS transistor is connected to the gate G of the PMOS transistor via a resistor, the single-core cable upstream interface is connected to the source S of the PMOS transistor, and the drain D of the PMOS transistor is connected to the single-core cable downstream interface;

[0101] The switching circuit is used to: control the connection between the high-voltage DC power supply and the single-core cable downstream interface by pulling up the digital control signal applied to the signal control interface to a first voltage; and control the disconnection between the high-voltage DC power supply and the single-core cable downstream interface by pulling down the digital control signal applied to the signal control interface to a second voltage.

[0102] Optionally, the receiving signal conditioning circuit further includes: a signal conditioning circuit connected to the DC blocking capacitor, configured to perform signal conditioning on the first digital signal output by the DC blocking capacitor to obtain a single-ended digital signal;

[0103] The signal conditioning circuit includes: a first operational amplifier, a second operational amplifier, and a resistor. The first operational amplifier and the second operational amplifier are connected in series. The positive input terminal of the first operational amplifier is connected to the second end of the DC blocking capacitor. The negative input terminal of the first operational amplifier is connected to GND through a resistor. The output terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier. The positive input terminal of the second operational amplifier is connected to GND through a resistor. The output terminal of the second operational amplifier is connected to the digital interface of the receiving end.

[0104] Optionally, the transmitting drive circuit further includes: a PMOS transistor, an NMOS transistor, a capacitor, a resistor, and a diode, wherein the first transmitting-end digital interface is connected to the gate G of the PMOS transistor via the capacitor, the source S of the PMOS transistor is connected to a +12V voltage via a resistor, the drain D of the PMOS transistor is connected to the second end of the DC-blocking capacitor via a diode and a resistor, the second transmitting-end digital interface is connected to the gate G of the NMOS transistor via the capacitor, the drain D of the NMOS transistor is connected to the second end of the DC-blocking capacitor via a diode and a resistor, and the source S of the NMOS transistor is connected to a -12V voltage via a resistor;

[0105] The transmission drive circuit is further used to: receive a second digital signal when transmitting data through the first transmission end digital interface and the second transmission end digital interface, and the PMOS transistor and the NMOS transistor drive the second digital signal.

[0106] Optionally, the first digital signal adopts Manchester encoding, wherein the encoding clock frequency is 4 MHz;

[0107] The second digital signal adopts Manchester encoding, wherein the encoding clock frequency is 4 MHz.

[0108] Optionally, the waveform amplitude of the first digital signal is ±9 VDC or ±12 VDC; the waveform amplitude of the second digital signal is ±9 VDC or ±12 VDC.

[0109] Each circuit or module in the transmission short section realizes Figure 1 The specific implementation of the single-core cable communication circuit between the logging instruments in the illustrated embodiment is similar and will not be repeated here.

[0110] This system can realize half-duplex communication between logging instruments. It has the characteristics of simple circuit structure and easy implementation. The longest cable between instruments can be 15 meters long and can be used in high temperature environments. For example, it can work in a high temperature environment of 200℃.

[0111] The algorithm or demonstration provided herein are not inherently relevant to any particular computer, virtual system or other equipment. Various general-purpose systems may also be used together with the teachings based on this. According to the above description, it is apparent that the structure required for constructing this type of system. In addition, the embodiment of the present invention is not directed to any specific programming language yet. It should be understood that various programming languages ​​can be utilized to realize the content of the present invention described herein, and the above description of specific languages ​​is for the purpose of disclosing the best mode of the present invention.

[0112] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0113] Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the embodiments of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims that follow the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0114] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition may be divided into multiple submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed herein may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0115] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0116] The various component embodiments of the present invention can be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components according to an embodiment of the present invention. The present invention can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for executing a part or all of the methods described herein. Such a program implementing the present invention can be stored on a computer-readable medium, or can have the form of one or more signals. Such a signal can be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

[0117] It should be noted that the above embodiments illustrate rather than limit the invention, and that alternative embodiments may be devised by a person skilled in the art without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising several different elements and by means of appropriately programmed computers. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names. The steps in the above embodiments should not be understood as limiting the order of execution unless otherwise specified.

Claims

1. A single-core cable communication circuit between logging instruments, applied to a first logging instrument, the single-core cable communication circuit between logging instruments comprising: A single-core cable interface, a sampling inductor, a DC blocking capacitor, a transmitting drive circuit, a receiving signal conditioning circuit, and a power module, wherein the receiving signal conditioning circuit includes: a receiving end digital interface, and the transmitting drive circuit includes: a first transmitting end digital interface and a second transmitting end digital interface. The single-core cable interface is respectively connected to the first end of the DC blocking capacitor and the first end of the sampling inductor, the second end of the DC blocking capacitor is respectively connected to the receiving signal conditioning circuit and the transmitting drive circuit, and the second end of the sampling inductor is connected to the power module; a single-core cable interface, connecting the first well logging instrument with the single-core cable interface of the second well logging instrument via the single-core cable, and configured to receive a high-voltage direct current signal transmitted by the second well logging instrument via the single-core cable, and to receive a first digital signal transmitted by the second well logging instrument via the single-core cable or to send a second digital signal to the second well logging instrument via the single-core cable; a sampling inductor, configured to filter the first digital signal, output a high-voltage direct current signal, and output the signal to the power module, so that the power module performs electrical signal conversion processing and outputs a low-voltage direct current signal; a receiving signal conditioning circuit, configured to perform signal conditioning on the first digital signal transmitted by the DC blocking capacitor to obtain a single-ended digital signal, and transmit the single-ended digital signal to a digital processing chip in the first logging instrument through the receiving-end digital interface for decoding; a transmitting driving circuit, configured to receive a second digital signal when transmitting data through the first transmitting end digital interface and the second transmitting end digital interface; a DC blocking capacitor, configured to block the high-voltage DC signal during data reception and output a first digital signal; and, during data transmission, couple the second digital signal transmitted by the transmission drive circuit to the single-core cable interface; Wherein, the single-core cable interface includes: a single-core cable uplink interface and a single-core cable downlink interface; The single-core cable uplink interface is connected to the first end of the DC blocking capacitor and the first end of the sampling inductor respectively; The single-core cable communication circuit between the logging instruments further includes: a switch circuit, wherein the switch circuit includes a signal control interface; The switch circuit is connected to the single-core cable uplink interface and the single-core cable downlink interface respectively; The switch circuit is used to control the connection and disconnection between the single-core cable upstream interface and the single-core cable downstream interface by controlling the voltage value of the digital control signal applied to the signal control interface, wherein the connection between the single-core cable upstream interface and the single-core cable downstream interface is controlled by pulling the digital control signal applied to the signal control interface up to a first voltage; and the disconnection between the single-core cable upstream interface and the single-core cable downstream interface is controlled by pulling the digital control signal applied to the signal control interface down to a second voltage; The DC blocking capacitor is further used to couple the second digital signal transmitted by the transmission driving circuit to the single-core cable uplink interface during data transmission.

2. The single-core cable communication circuit between logging instruments according to claim 1, wherein: The switch circuit further comprises: a PMOS transistor and an NMOS transistor; The signal control interface is connected to the gate G of the NMOS transistor, and the source S of the NMOS transistor is grounded; the drain D of the NMOS transistor is connected to the gate G of the PMOS transistor via a resistor, the single-core cable upstream interface is connected to the source S of the PMOS transistor, and the drain D of the PMOS transistor is connected to the single-core cable downstream interface.

3. The single-core cable communication circuit between logging instruments according to claim 1 or 2, wherein: The receiving signal conditioning circuit further includes: a signal conditioning circuit connected to the DC blocking capacitor, configured to perform signal conditioning on the first digital signal output by the DC blocking capacitor to obtain a single-ended digital signal; The signal conditioning circuit includes: a first operational amplifier, a second operational amplifier, and a resistor. The first operational amplifier and the second operational amplifier are connected in series. The positive input terminal of the first operational amplifier is connected to the second end of the DC blocking capacitor. The negative input terminal of the first operational amplifier is connected to GND through a resistor. The output terminal of the first operational amplifier is connected to the negative input terminal of the second operational amplifier. The positive input terminal of the second operational amplifier is connected to GND through a resistor. The output terminal of the second operational amplifier is connected to the digital interface of the receiving end.

4. The single-core cable communication circuit between logging instruments according to claim 1 or 2, wherein: The transmitting drive circuit further includes: a PMOS transistor, an NMOS transistor, a capacitor, a resistor, and a diode, wherein the first transmitting-end digital interface is connected to the gate G of the PMOS transistor of the transmitting drive circuit via the capacitor, the source S of the PMOS transistor of the transmitting drive circuit is connected to a +12V voltage via a resistor, the drain D of the PMOS transistor of the transmitting drive circuit is connected to the second end of the DC blocking capacitor via a diode and a resistor, the second transmitting-end digital interface is connected to the gate G of the NMOS transistor of the transmitting drive circuit via the capacitor, the drain D of the NMOS transistor of the transmitting drive circuit is connected to the second end of the DC blocking capacitor via a diode and a resistor, and the source S of the NMOS transistor of the transmitting drive circuit is connected to a -12V voltage via a resistor; The transmitting drive circuit is further used to: receive a second digital signal when transmitting data through the first transmitting end digital interface and the second transmitting end digital interface, and the PMOS transistor and the NMOS transistor of the transmitting drive circuit drive the second digital signal.

5. The single-core cable communication circuit between logging instruments according to claim 1 or 2, wherein: The waveform amplitude of the first digital signal is ±9 VDC or ±12 VDC; the waveform amplitude of the second digital signal is ±9 VDC or ±12 VDC.

6. The single-core cable communication circuit between logging instruments according to claim 1 or 2, wherein: The circuit is used to implement half-duplex communication between the first well logging tool and the second well logging tool.

7. A well logging instrument, comprising the inter-logging instrument single-core cable communication circuit according to any one of claims 1 to 6.

8. A well logging system comprising a transmission sub and a plurality of well logging instruments according to claim 7 cascaded via a single-core cable, wherein: The transmission sub is connected to the logging instrument via a single-core cable; The transmission short section includes: a high-voltage DC power supply, a single-core cable interface, a sampling inductor, a DC blocking capacitor, a transmitting drive circuit, a receiving signal conditioning circuit, and a power supply module, wherein the high-voltage DC power supply is connected to the first end of the sampling inductor of the transmission short section, the second end of the sampling inductor of the transmission short section is respectively connected to the single-core cable interface of the transmission short section and the first end of the DC blocking capacitor of the transmission short section, the second end of the DC blocking capacitor of the transmission short section is respectively connected to the receiving signal conditioning circuit of the transmission short section and the transmitting drive circuit of the transmission short section, and the high-voltage DC power supply is connected to the power supply module of the transmission short section; the receiving signal conditioning circuit of the transmission short section includes: a receiving end digital interface, and the transmitting drive circuit of the transmission short section includes: a first transmitting end digital interface and a second transmitting end digital interface; A single-core cable interface of the transmission sub, which connects the transmission sub to the single-core cable interface of the logging instrument via the single-core cable, and is used to transmit a high-voltage direct current signal to the logging instrument via the single-core cable, and to send a first digital signal to the logging instrument via the single-core cable, or to receive a second digital signal transmitted by the logging instrument via the single-core cable; a sampling inductor of the transmission short section, used for filtering the first digital signal or the second digital signal; The receiving signal conditioning circuit of the transmission short section is used to perform signal conditioning on the second digital signal transmitted by the DC blocking capacitor of the transmission short section to obtain a single-ended digital signal, and transmit the single-ended digital signal to the digital processing chip in the transmission short section through the receiving end digital interface of the transmission short section for decoding processing; a transmission drive circuit of the transmission subsection, configured to receive a first digital signal when transmitting data through the first transmitting end digital interface of the transmission subsection and the second transmitting end digital interface of the transmission subsection; The DC blocking capacitor of the transmission short section is used to block the high-voltage DC signal during the data reception process and output a second digital signal; and, during the data transmission process, couple the first digital signal transmitted by the transmission drive circuit of the transmission short section to the single-core cable interface of the transmission short section.

9. The system according to claim 8, wherein: The transmission sub also includes: a switch circuit, wherein the switch circuit of the transmission sub includes a signal control interface; The switch circuit of the transmission short section is respectively connected to the second end of the sampling inductor of the transmission short section and the single-core cable interface of the transmission short section; The switching circuit of the transmission short section is used to control the on / off connection between the high-voltage DC power supply and the single-core cable interface of the transmission short section by controlling the voltage value of the digital control signal applied to the signal control interface of the transmission short section.

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