Multi-precision floating point fusion multiply-add structure and microprocessor architecture

Abstract

The invention provides a multi-precision floating point fusion multiply-add structure and a microprocessor architecture, and the structure is characterized in that in a first-stage assembly line, an input preprocessing module decomposes an input operand to obtain a sign bit, an index bit and a mantissa bit; the Booth encoder generates partial products through a radix-4 Booth encoding algorithm, and the tree array multiplier compresses the partial products into three groups; in the second-stage assembly line, the CSA4-2 compression adder compresses the mantissa bits after the three groups of partial products and shift alignment into two groups; the summator module sums the two groups of partial products to obtain a mantissa summation result; in the third-stage assembly line package, a leading zero detection module performs leading zero detection on the mantissa summation result, and performs index adjustment and mantissa adjustment to obtain a normalized result; and in the fourth-stage assembly line, rounding of floating point data is carried out. According to the application, the operation performance, the energy efficiency ratio and the adaptability of the floating point fusion multiply-add structure are improved, so that the high performance and the high energy efficiency of the microprocessor are balanced.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a multi-precision floating-point fused multiplication-addition structure and a microprocessor architecture. Background Art

[0002] Emerging applications such as the Internet of Things, artificial intelligence, and edge computing are placing higher demands on embedded processors for floating-point computing capabilities. In particular, the fused multiply-add (FMA) operation has become a core computational unit in compute-intensive tasks such as image processing, signal processing, and machine learning inference. FMA combines multiplication and addition into a single operation, effectively reducing the number of instructions and intermediate rounding errors, thereby significantly improving computational throughput. The IEEE 754 standard specifies the mathematical behavior and rounding rules for floating-point multiply-add operations. The RISC-V instruction set builds on this by extending instructions such as FMUL and FMADD to support efficient hardware implementation.

[0003] Single-precision formats (such as FP32) struggle to achieve an ideal balance between performance and power consumption. Floating-point units supporting multiple precision formats (such as FP32, FP16, and BF16) have become a key trend in modern processor design. Low-precision arithmetic not only helps reduce hardware complexity and power consumption but is also particularly well-suited for energy-sensitive edge devices. RISC-V, as an open and modular instruction set architecture, features a flexible ISA extension mechanism, facilitating customized instruction extensions tailored to specific application requirements. Although research and application of low-precision floating-point arithmetic have achieved significant results in academia and industry, processor implementations within the RISC-V architecture still primarily support FP32 basic precision, with limited native support for lower-precision formats such as FP16 and BF16. This is particularly true in resource-constrained and power-sensitive edge computing scenarios, where optimized designs that balance flexibility, energy efficiency, and resource utilization are still lacking.

[0004] Therefore, a solution is urgently needed to address the problems of insufficient support for multi-precision floating-point multiplication and addition operations, low instruction scheduling efficiency, and low resource utilization. Summary of the Invention

[0005] The present application discloses a multi-precision floating-point fused multiply-add structure and a microprocessor architecture, which can improve the computing performance, energy efficiency and adaptability of the floating-point fused multiply-add structure, while balancing the high performance and high energy efficiency of the floating-point fused multiply-add structure in the microprocessor.

[0006] Other purposes and advantages of this application can be further understood from the technical features disclosed in this application.

[0007] To achieve one, part, or all of the above objectives or other objectives, in a first aspect, the present application provides a multi-precision floating-point fused multiply-add structure, including: The first-stage pipeline includes an input preprocessing module, a Booth encoder, a tree array multiplier, an exponential order difference module, and a symbolic logic module. The input preprocessing module is used to decompose the input operand to obtain a sign bit, an exponent bit, and a mantissa bit; the symbolic logic module is used to determine the sign bit of the operand; the exponential order difference module is used to perform order difference calculation on the exponent bit in combination with the sign bit to determine the exponent difference; the Booth encoder encodes the mantissa bit using a radix-4 Booth encoding algorithm to generate partial products, and the tree array multiplier is used to compress the partial products into three groups of partial products. The second-stage pipeline includes a CSA 4-2 compression adder, an alignment shift module, and an adder module, wherein the alignment shift module is used to calculate the size of the alignment shift according to the exponent difference and shift-align the mantissa bits; the CSA4-2 compression adder is used to compress the three groups of partial products and the mantissa bits after the shift alignment into two groups of partial products; the adder module is used to sum the two groups of partial products to obtain a mantissa sum result; The third-stage pipeline includes a leading zero detection module, an exponent logic module, and a shift logic module. The leading zero detection module is used to perform leading zero detection on the mantissa summation result and output the number of leading zeros. The exponent logic module is used to perform exponent adjustment on the number of leading zeros. The shift logic module performs mantissa adjustment on the number of leading zeros to obtain a normalized result. The fourth stage pipeline includes a rounding module, which rounds the floating point data according to the normalization result and the rounding mode instruction.

[0008] Furthermore, in the first-stage pipeline, the input preprocessing module performs an abnormality judgment on the input operand based on the decomposed sign bit, exponent bit and mantissa bit. If the operand is a NAN value or an infinite value, the operation is stopped and the result and status are directly output.

[0009] Furthermore, in the first-stage pipeline, the first-stage pipeline includes a buffer for caching floating-point instructions and operands contained in the floating-point instructions, and transmitting them to the second-stage pipeline.

[0010] Furthermore, in the low-precision floating-point multiplication-addition operation, an 11×11 bit multiplier is used; in the floating-point mantissa multiplication, two low-precision mantissa multiplication results are generated in parallel and implemented using single-precision floating-point mantissa multiplication, and the 11×11 bit multiplier uses a Booth encoder.

[0011] Further, the expression for the tree array multiplier to compress the partial products into three groups of partial products is: ; Among them, the partial products compressed by the tree array multiplier are determined by the maximum height sequence d j , and j is the initial value that satisfies the maximum value of d j < min(n1, n2), where n1 and n2 are the number of bits of the input multiplicand and multiplier respectively.

[0012] Further, in single-precision floating-point multiply-add operations, 4 11×11 bit multipliers, 4 2×11 bit multipliers, and 1 2×2 bit multiplier are used to implement single-precision floating-point mantissa multiplication.

[0013] Further, the 2×11 bit multiplier includes two 13-bit data selectors and one adder. The input multipliers of the data selectors are all 11 bits, and the control signals of the data selectors are all 2 bits.

[0014] Further, in the second-level pipeline, the floating-point instructions include at least one of floating-point multiplication instructions, floating-point addition instructions, and floating-point multiply-add instructions; If there are two consecutive related floating-point instructions and there is a register conflict, when the first instruction contains a floating-point multiplication instruction and the second instruction is a floating-point addition instruction, the floating-point multiplication is executed first, and the floating-point addition is executed in the next clock cycle; If there are two consecutive related floating-point instructions and there is a register conflict, when the first instruction is a floating-point addition instruction and the second instruction contains a floating-point multiplication instruction, the floating-point addition is executed first, paused in the next clock cycle, and after forwarding the result of the floating-point addition to the first-level pipeline, the floating-point multiplication is executed; If the two floating-point instructions are not related, they are executed according to the original order.

[0015] Further, in the second-level pipeline, the execution of floating-point multiplication and floating-point addition is controlled by a state machine.

[0016] Further, if there are two consecutive related floating-point instructions, and the first instruction is a floating-point multiplication instruction and the second floating-point instruction is a floating-point addition instruction, in the first clock cycle, the floating-point multiplication is executed; < In a second clock cycle, the CSA 4-2 compression adder performs floating-point addition based on a first addition operand shift result of the first-stage pipeline, a floating-point mantissa multiplication result generated by the second-stage pipeline in the first clock cycle, and a second addition operand shift result; wherein the first addition operand shift result represents an exponential difference between exponents of the maximum operands in two related consecutive floating-point instructions in the first-stage pipeline in the second clock cycle, the second addition operand shift result represents an exponential difference between exponents of the maximum operands in two related consecutive floating-point instructions in the second-stage pipeline in the first clock cycle, and three of the four input ports of the CSA 4-2 compression adder are used.

[0017] Further, if the first floating-point instruction is a floating-point multiplication instruction, the second floating-point instruction is a floating-point multiply-add instruction, and the result of the floating-point multiplication instruction is an addition operand of the second floating-point instruction, then the floating-point multiplication of the first floating-point instruction is calculated in the second clock cycle to obtain a floating-point mantissa multiplication result; Using the floating-point mantissa multiplication result of the first floating-point instruction as the addition operand of the second floating-point instruction, and performing a shift operation based on the exponent difference between the maximum exponents of the two instructions; During a third clock cycle, the CSA 4-2 compression adder performs floating-point addition based on the three floating-point mantissa multiplication partial products of the second floating-point instruction and the floating-point mantissa multiplication result of the first floating-point instruction, and four of the four input ports of the CSA 4-2 compression adder are used.

[0018] Furthermore, if the first floating-point instruction of the two floating-point instructions is a floating-point addition instruction, and the second floating-point instruction is a floating-point multiplication instruction or a floating-point multiply-add instruction, and the multiplication operand used by the second floating-point instruction is generated by the first floating-point instruction, the pipeline is paused for one cycle when executing the second floating-point instruction.

[0019] Furthermore, the rounding includes at least one of rounding to the nearest, rounding towards zero, rounding down, rounding up and rounding to the nearest.

[0020] In a second aspect, the present application provides a microprocessor architecture, which includes a multi-precision floating-point fused multiply-add structure as described in any one of the first aspects.

[0021] Furthermore, the microprocessor architecture includes: An instruction fetch module, configured to fetch a floating-point instruction, the instruction fetch module comprising a pre-decoding unit configured to decode a source register address; wherein the floating-point instruction comprises at least one of a floating-point multiply-add instruction, a floating-point multiplication instruction, and a floating-point addition instruction; A decoding module, comprising a buffer unit for caching a destination register address of a floating-point instruction; the decoding module is used to determine whether the destination register address is the same as the source register address, and whether there is a register conflict between the current floating-point instruction and the next floating-point instruction, so as to determine whether to pause the pipeline; An execution module, configured to send the current floating-point instruction into the floating-point fused multiply-add structure and obtain an execution result; The memory access module is used to write the execution result back to the register file to complete the instruction execution.

[0022] Furthermore, the decoding module is used to determine whether there is a register conflict between the current floating-point instruction and the next floating-point instruction. If there is a register conflict and the next instruction includes a floating-point multiplication instruction, the pipeline is paused for one cycle.

[0023] The multi-precision floating-point fused multiply-add structure and microprocessor architecture utilizes a four-stage pipeline, employing multi-cycle implementations in the floating-point multiplication partial product summation stage and the floating-point addition stage. By using tree-array multipliers to rapidly compress partial products in the multiplication stage, this improves computational speed while reducing the number of required full and half adders, thereby lowering hardware area and power consumption. Furthermore, the hierarchical tree-array multipliers effectively alleviate the latency bottleneck of the first-stage pipeline, rationally allocating partial multiplication latency to the addition stage of the second-stage pipeline. The second-stage pipeline utilizes multi-cycle multiplexing to reduce hardware resources and achieve balanced optimization of overall latency. This improves the computational performance, energy efficiency, and adaptability of the floating-point fused multiply-add structure, balancing the high performance and energy efficiency of the floating-point fused multiply-add structure in the microprocessor.

[0024] In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present application, the following is a brief introduction to the drawings required for the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] Figure 1 This is the structural block diagram of the multi-precision floating-point fusion multiplication and addition structure of this application.

[0027] Figure 2 This is the calculation result diagram of the single-precision multiplier for this application.

[0028] Figure 3 This is the framework diagram of the 2×11 bit multiplier implementation for this application.

[0029] Figure 4 This is a structural block diagram of the microprocessor architecture of this application.

[0030] Figure 5 Execution graph of floating-point multiply-add and floating-point add instructions when register conflict occurs for this application.

[0031] Figure 6 Execution graph of floating-point addition and floating-point multiplication instructions when register conflicts occur for this application.

[0032] Figure 7 The floating-point multiply-add or add, floating-point multiply-add instruction execution graph when register conflict occurs for this application. DETAILED DESCRIPTION

[0033] The aforementioned and other technical contents, features, and functions of the present application will be clearly presented in the following detailed description of a preferred embodiment with reference to the drawings. The terms "first," "second," and the like in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, and this is merely a way of distinguishing objects of the same attributes when describing them in the embodiments of the present application.

[0034] The embodiment of the present application provides a multi-precision floating-point fused multiplication-addition structure comprising a four-stage pipeline. The first stage of the pipeline comprises an input preprocessing module, a Booth encoder, a tree array multiplier, an exponential order difference module, and a symbolic logic module. The input preprocessing module is used to decompose the input operand into a sign bit, an exponent bit, and a mantissa bit; the symbolic logic module is used to determine the sign bit of the operand; the exponential order difference module is used to calculate the order difference of the exponent bit in combination with the sign bit to determine the exponent difference; the Booth encoder encodes the mantissa bits using a radix-4 Booth encoding algorithm to generate partial products; and the tree array multiplier is used to compress the partial products into three groups of partial products.

[0035] The second-stage pipeline includes a CSA 4-2 compression adder, an alignment shift module, and an adder module. The alignment shift module is used to calculate the size of the alignment shift based on the exponent difference and shift-align the mantissa bits. The CSA 4-2 compression adder is used to compress the mantissa bits of three groups of partial products after compression and shift alignment into two groups of partial products. The adder module is used to sum the shift-aligned data to obtain the mantissa sum result.

[0036] The third-level pipeline includes a leading zero detection module, an exponential logic module, and a shift logic module. The leading zero detection module is used to perform leading zero detection on the sum of the mantissas and output the number of leading zeros. The exponential logic module is used to adjust the exponent of the number of leading zeros. The shift logic module adjusts the mantissa of the number of leading zeros to obtain a normalized result.

[0037] The fourth-stage pipeline includes a rounding module, which rounds the floating-point data according to the normalization result and the rounding mode instruction.

[0038] The multi-precision floating-point fused multiplication-addition structure of the present invention is implemented in a multi-cycle form in the floating-point multiplication partial product summation stage and the floating-point addition stage through a four-stage pipeline. By using a tree array multiplier to quickly compress the partial products in the multiplication stage, the number of required full adders and half adders is reduced while improving the computing speed, thereby reducing the hardware area and power consumption. At the same time, the hierarchical tree array multiplier effectively alleviates the delay bottleneck of the first-stage pipeline and reasonably distributes the partial multiplication delay to the addition stage of the second-stage pipeline. The second-stage pipeline reduces hardware resources through multi-cycle multiplexing, achieving balanced optimization of the overall delay. This improves the computing performance, energy efficiency, and adaptability of the floating-point fused multiplication-addition structure, thereby balancing the high performance and high energy efficiency of the floating-point fused multiplication-addition structure in the microprocessor.

[0039] Specifically, refer to Figure 1 , which is a block diagram of the multi-precision floating-point fused multiply-add structure of the present application. The first-stage pipeline is used to decompose the three floating-point operands (op-a / op-b / op-c) input. The input preprocessing module decomposes each floating-point operand into the sign bit Sign, exponent bit Exp, and mantissa bit Man3. It also performs an exception check based on the decomposition results. If the input data is NAN or infinity, the calculation path operation is stopped and the result and status exception are directly output. The buffer is used to cache operands and other input information when the instruction contains multiplication; the exponential order difference module performs exponential order difference calculations to determine the shift distance; the symbolic logic module determines the sign bit based on the three input operand signals; the Booth encoder uses radix-4 Booth encoding to generate partial products, and a tree array multiplier is used to compress the partial products into three groups. In this embodiment, the tree array multiplier is preferably a DaddaTree compressor.

[0040] In the second-stage pipeline, the CSA 4-2 compression adder receives three sets of partial products from the first-stage pipeline and compresses them into two sets. The alignment shift module calculates the size of the alignment shift based on the exponent difference transmitted from the first stage, simultaneously shifts and aligns the mantissa bits of the operand op-c, and transmits the result to the CSA 4-2 compression adder. The CSA 4-2 compression adder compresses the received three sets of partial products and the shifted and aligned mantissa bits into two sets. The adder module receives the two sets of partial products and sums them to obtain the mantissa summation result. In the second-stage pipeline, a state machine can be used to control whether a floating-point multiplication instruction or a floating-point addition instruction is executed. The judgment condition is differentiated based on the execution order of two related floating-point instructions or individual instructions. The floating-point instructions include at least one of a floating-point fused multiply-and-add instruction, a floating-point multiplication instruction, and a floating-point addition instruction.

[0041] Furthermore, if there are two consecutive floating-point instructions and a register conflict, the floating-point multiplication state is entered first, and the floating-point addition state is entered in the next clock cycle. If the instructions are unrelated, they are executed according to the original order, and the pipeline is paused as needed. When executing a single-instruction floating-point multiplication and addition operation, in the next clock cycle, the CSA 4-2 compressed adder receives the shifted result of the third addition operand and the floating-point mantissa multiplication result generated by the second stage pipeline in the previous clock cycle. The exponent corresponding to this mantissa multiplication is subtracted from the exponent of the third addition operand to generate an exponent difference. The third mantissa addition operand is shifted according to the exponent difference. At this time, two of the four input ports of the CSA 4-2 compressed adder are used, and the other two ports are set to zero.

[0042] When executing two consecutive floating-point fused multiply-add instructions, if the first instruction contains a floating-point multiplication instruction (either a floating-point multiplication instruction or a floating-point multiply-add instruction) and the second instruction is a floating-point addition instruction, the operation remains unchanged in the first clock cycle, i.e., floating-point multiplication is performed. In the second clock cycle, the CSA 4-2 compressed adder receives the shifted result of the third addition operand from the first pipeline stage (the shift length is the exponent difference formed by the first pipeline stage in the second clock cycle, using the exponent of the largest operand between the two instructions as the standard), the floating-point mantissa multiplication result generated by the second pipeline stage in the first clock cycle, and the shifted result of the third addition operand (the shift length is the exponent difference formed by the second pipeline stage in the first clock cycle, using the exponent of the largest operand between the two instructions as the standard). At this time, three of the four input ports of the CSA 4-2 compressed adder are used, and the other port is set to zero.

[0043] If the first instruction is a floating-point multiplication instruction and the second instruction is a floating-point multiply-add instruction, and the result of the floating-point multiplication is the addition operand of the second instruction, the first clock cycle remains unchanged, that is, the floating-point multiplication is executed. The second instruction cycle calculates the floating-point mantissa multiplication of the first instruction, and the second instruction enters the pipeline. The addition operand of the second instruction is replaced by the floating-point mantissa multiplication result of the first instruction. The exponent difference is shifted based on the maximum exponent of the two instructions. In the third cycle, the CSA 4-2 compressed adder receives the three floating-point mantissa multiplication partial products of the second instruction and the mantissa multiplication result of the first instruction. At this time, four of the four input ports of the CSA 4-2 compressed adder are used. Then, another mantissa addition operation is performed in the adder module, resulting in the unnormalized and unrounded results of the two instructions.

[0044] When the first of two instructions is a floating-point addition instruction and the second instruction contains a floating-point multiplication instruction (floating-point multiplication instruction or floating-point multiply-add instruction), and one operand of the multiplication operation is generated by the result of the previous instruction, the floating-point addition is performed first. It is necessary to pause the pipeline for one cycle when executing the second instruction so that the result of the first instruction is passed to the a operand port of the first-level pipeline, and the b operand port is another unrelated multiplication operand to perform floating-point multiplication.

[0045] In the third-stage pipeline, the leading zero detection module receives the result of the mantissa calculation of the previous stage and performs leading zero detection. The exponent logic module and the shift logic module adjust the exponent or mantissa according to the number of leading zeros output by the leading zero detection module to obtain a normalized result.

[0046] In the fourth-level pipeline, the rounding module rounds the floating-point data in the normalized result according to the normalized result and rounding mode instruction transmitted by the previous-level pipeline. The rounding includes five states: rounding to the nearest (associated with an even number), rounding toward zero, rounding down, rounding up, and rounding to the nearest (associated with the maximum amplitude).

[0047] In some embodiments, as shown in Table 1, the partial products generated by the radix-4 Booth encoding algorithm of the Booth encoder of the present application are shown. Here, X represents the number of bits of the current data, and Z represents the operation to be performed on this set of data. 0 indicates that the result of this data is 0, +A indicates that the data remains unchanged, -A indicates that the data is inverted and then added by one, 2A indicates that the data is shifted left by one bit, and -2A indicates that the data is shifted left by one bit, inverted, and added by one. When performing an operation on the first set of data, 0 must be padded to the end (X-1; when X is 1, the 0th bit of data must be padded).

[0048] Table 1 In this embodiment, the partial products are compressed into 3 groups using a tree array multiplier. The tree array multiplier is preferably a Dadda Tree compressor, and the reduced partial products are determined by the maximum height sequence and will generate sequences such as d1 = 2, d2 = 3, d3 = 4, d4 = 6, d5 = 9. The expression (1) for the tree array multiplier to compress the partial products into three groups of partial products is: Expression (1); where the partial products compressed by the tree array multiplier are determined by the maximum height sequence d [ j , and j is the initial value satisfying the maximum value of d [ j < min(n1, n2), where n1 and n2 are the number of bits of the input multiplicand and multiplier respectively.

[0049] In this embodiment, the Booth encoder includes an 11×11 bit multiplier. Using the radix-4 Booth algorithm will generate 6 groups of partial products, and the partial products P0, P1, P2, P3, P4, P5 are arranged. As shown in Table 2, where S represents the sign bit of the current partial product, 1 represents a negative number, and 0 represents a positive number. The tree array multiplier compresses the 6 groups of partial products. For the first compression, it is necessary to satisfy d3 = 4, so the 6 groups of partial products need to be compressed into 4 groups; for the second time, the 4 groups of partial products need to be compressed into 3 groups; in the architecture of this embodiment, it is sufficient to compress the partial products into 3 groups.

[0050] Table 2 More specifically, during the first compression, a half adder is used to sum the 6-9 columns in partial products P0 and P1, a half adder is used to sum the 15th column in partial products P4 and P5, a half adder is used to sum the 17th column in partial products P2 and P3, a full adder is used to sum the 10-14 columns in partial products P0, P1 and P2, a full adder is used to sum the 8-9 columns in partial products P2, P3 and P4, a full adder is used to sum the 10-14 columns in partial products P3, P4 and P5, a full adder is used to sum the 15th column in partial products P1, P2 and P3, a full adder is used to sum the 16th column in partial products P2, P3 and P4. The results and carry obtained after summing using the full adder and half adder are given to the next column respectively, generating a 4-level partial product compression sequence as shown in Table 3. Among them, the full adder generates the sum result by 2 exclusive-OR gates, and two AND gates and one OR gate generate the carry result. The half adder generates the sum result by one exclusive-OR gate and the carry result by one AND gate.

[0051] Table 3 During the second compression, the partial product sequences in Table 3 are compressed. Columns 4-5, and 19 of the partial products L0 and L1 are summed using half adders. Columns 6-18 of the partial products L0, L1, and L2 are summed using full adders. The summation results and carry bits of the full and half adders are added to the next column, respectively. This produces the three sets of partial product compressed sequences shown in Table 4. In Tables 2, 3, and 4, all · denote partial product data, S denotes an operator, and blank spaces are filled with 0s.

[0052] Table 4 When performing single-precision floating-point multiplication and addition operations, floating-point mantissa multiplication requires four 11×11-bit multipliers, four 2×11-bit multipliers, and one 2×2-bit multiplier to implement. Figure 2 The figure shows the mantissa product generation diagram for single-precision floating-point multiplication. P0, P1, P3, and P4 are the results of 11×11-bit multipliers, P2, P5, P6, and P7 are the results of 2×11-bit multipliers, and P8 is the result of a 2×2-bit multiplier. Of these multipliers, only the 11-bit multiplier is implemented using the radix-4 Booth algorithm and the DaddaTree compressor. The other multipliers are implemented using 13-bit or 4-bit input adders and data selectors.

[0053] like Figure 3 As shown in Figure 1, the 2×11-bit multiplier of this embodiment is implemented using two 13-bit data selectors and an adder. The 2-bit multiplication inputs serve as control signals for the data selectors. The two inputs to the first data selector are {2'b0, A} and 13'b0, respectively. The two inputs to the second data selector are {1'b0, A, 1'b0} and 13'b0, respectively. A represents the 11-bit input multiplier. The 2×2-bit multiplier is implemented using shifting and summing, and its basic implementation is similar to that of the 2×11-bit multiplier.

[0054] When performing other low-precision floating-point multiplication and addition operations, since the mantissa bit width of the low-precision format is less than or equal to 10 bits, an 11*11 bit multiplier can be directly used. At the same time, in the floating-point mantissa multiplication, two low-precision mantissa multiplication results can be generated in parallel, and the results of P0 and P4 in the single-precision floating-point mantissa multiplication calculation can be directly used. For example, when a superscalar processor executes two consecutive single-precision floating-point multiplication instructions without data conflicts, it can simultaneously generate the results of these two instructions and write the data results through a multi-port register. The floating-point multiplication and addition structure designed in this application can also be integrated into a superscalar processor for high-speed data processing.

[0055] In this embodiment, floating-point mantissa multiplication is implemented using an 11×11-bit multiplier, which is applicable to multiple precisions, such as FP32 / TF32 / Bfloat16 / DLFloat / FP16. In particular, full utilization is achieved in mantissa multiplication calculations of TF32 and FP16 precisions. In calculations with other precisions, at least 2 bits of circuit resources can be saved in each calculation cycle while maintaining computational efficiency. For single-precision calculations, mantissa multiplication is implemented using four 11×11-bit multipliers, four 2×11-bit multipliers, and one 2×2-bit multiplier. The 2×11-bit multiplier is implemented using two selectors and one adder, ensuring that resource consumption is minimized as much as possible while fully utilizing the multiplier bit width.

[0056] Based on the same inventive concept, an embodiment of the present application also provides a microprocessor architecture, which includes any of the above-mentioned multi-precision floating-point fused multiply-add structures.

[0057] In one embodiment, Figure 4 As shown, the microprocessor architecture includes an instruction fetch module, a decode module, an execution module, and a memory access module. The instruction fetch module is used to fetch floating-point instructions and includes a pre-decode unit for decoding a source register address. Floating-point instructions include at least one of floating-point multiply-add instructions, floating-point multiplication instructions, and floating-point addition instructions. The decode module includes a buffer unit for caching the destination register address of the floating-point instruction. The decode module is used to determine whether the destination register address is the same as the source register address and whether there is a register conflict between the current floating-point instruction and the next floating-point instruction, thereby determining whether to stall the pipeline. The execution module is used to send the current floating-point instruction to the floating-point fused multiply-add structure to obtain the execution result. The memory access module is used to write the execution result back to the register stack to complete instruction execution.

[0058] In one embodiment, if the decoding module determines that there is a register conflict between the current floating-point instruction and the next floating-point instruction, and the current floating-point instruction is a floating-point multiplication-addition instruction, and the next instruction is a floating-point addition instruction or a floating-point multiplication instruction, the pipeline is not paused. If the decoding module fails to determine that the error occurs, the pipeline is paused, and the execution of the next floating-point instruction is continued after the current floating-point instruction is completed. This microprocessor architecture precisely controls the execution of the floating-point multiplication and addition stages through control instructions, utilizing the same hardware architecture to complete different computational tasks, effectively alleviating the problem of processor resource overflow. This allows floating-point multiplication instructions to continue executing even when they are issued continuously and generate register conflicts, thereby improving processor execution efficiency.

[0059] Specifically, the instruction fetch module is used to execute the instruction fetch phase and reduce the pressure of the decoding phase through the pre-decoding unit. At the same time, the pre-decoding unit decodes the source register address, and the signal names are rs1, rs2, and rs3 respectively. The decoding module is used to execute the decoding phase and cache the destination register address of the current instruction and the floating-point fusion multiplication and addition, floating-point multiplication, and floating-point addition instruction enable through the buffer unit. The signal names are rd-buf, fmadd-buf, fmul-buf, and fadd-buf. In the decoding phase, it is determined whether rd-buf is the same as the address of one of rs1, rs2, and rs3 to determine whether there is a register conflict problem. At the same time, the decoding phase will generate a specific floating-point instruction type. If the previous floating-point fusion multiplication and addition instruction enable signal fmadd-buf and the current floating-point multiplication or addition enable signal are both high, the execution phase of the floating-point multiplication unit structure of the present application is entered. If there is a register conflict between the current instruction and the next instruction, and the next instruction includes a floating-point multiplication instruction (a floating-point multiplication instruction or a floating-point multiply-add instruction), the pipeline will be paused for one cycle in the next clock cycle, allowing the addition result to be passed to the first-stage pipeline before continuing execution. If the current instruction includes a floating-point multiplication instruction (a floating-point multiply-add instruction or a floating-point multiplication instruction) and the next instruction is a floating-point addition instruction, the pipeline will not be paused, and the floating-point multiplication will be executed first, followed by the floating-point addition in the next clock cycle. The floating-point fused multiplication-add structure of this application can be used to calculate the final result of the two instructions and write the final result to the destination register of the next instruction. If the judgment fails, the current pipeline will be paused and the next instruction will continue after the current instruction is completed.

[0060] In this embodiment, the pre-decoding unit is preferably suitable for processor cores that do not include an instruction cache and branch predictor. If these components are included, adding pre-decoding during the instruction fetch phase will increase the instruction fetch latency and reduce processor performance. In this case, pre-decoding is not performed, and the source operand, destination operand, and three floating-point instruction enables are generated during the decoding phase. These are simultaneously input to the buffer unit and then compared with the decoded signal of the next cycle to generate control logic. These two implementation methods are respectively targeted at devices with different processor cores, expanding the scope and application scenarios of this application.

[0061] More specifically, if Figure 5 As shown, the status of two related instructions when they are executed in the processor architecture of this application. The first instruction A is shown in expression (2), where R0 is the destination register number, R1, R2, and R3 are the source register numbers, and FMADD indicates that this instruction is a floating-point fused multiply-add instruction. The second instruction B is shown in expression (3), where R5 is the destination register number, R0 and R2 are the source register numbers, and FADD indicates that this instruction is a floating-point addition instruction.

[0062] Expression (2); Expression (3); During execution, instruction A enters the processor of this application first, and instruction B is fetched one clock cycle later. The two instructions pass through the decoding stage in sequence, with instruction A reaching the execution stage first and being sent to the floating-point multiplication-add fusion structure of this application. It undergoes data preprocessing and partial multiplication pre-operation in the first-stage pipeline. In the next clock cycle (cycle 2), it is sent to the second-stage pipeline for multiplication. At this time, instruction B enters the first-stage pipeline of this application, and instruction A completes the floating-point mantissa multiplication and related shift operations. In the next clock cycle (cycle 3), instruction A begins performing floating-point addition, and instruction B also begins performing floating-point addition. The calculation is now a+b+c, where a is the operand required for instruction A's floating-point multiplication and addition, and b is the multiplication result of instruction A's floating-point multiplication and addition. Instruction B needs to calculate (a+b)+c. The CSA 4-2 compression adder of this application compresses the input values ​​of a, b, and c together to avoid wasting time executing instruction B after instruction A has completed. The output result then enters the cycle 2 input adder for calculation, obtaining the final calculation result of floating-point instructions A and B. Then, in the fourth clock cycle, the normalization phase begins, performing floating-point normalization processing. The fifth cycle enters the rounding phase, rounding the calculation result according to the requirements of instruction B decoding. Other instructions, such as FMUL followed by FADD, are similar in calculation to the aforementioned FMADD followed by FADD. The differences lie in the different inputs to the CSA 4-2 compression adder and the choice of which to use for the result of the previous DaddaTree compressor. These are all described above and will not be repeated here. This application completes this type of instruction in just five cycles, without concern for register conflicts.

[0063] like Figure 6 As shown, a floating-point addition is followed by a floating-point multiplication instruction, and a register conflict occurs. Since the second-stage pipeline of this application performs partial mantissa multiplication and addition operations, it is necessary to pause the pipeline in the third cycle to pass the result of the addition operation to the first stage so that the partial product operation of the first stage can obtain the correct result. Other operations and the above Figure 5 This type of instruction requires 6 cycles to implement in this application, without considering register conflicts.

[0064] like Figure 7As shown, a floating-point multiplication or floating-point addition is followed by a floating-point multiplication-add instruction, and a register conflict occurs. Since the second-stage pipeline of the present application performs partial mantissa multiplication and addition operations, it is necessary to pause the pipeline in the third clock cycle and pass the result of the addition operation to the first-stage pipeline so that the partial product operation of the first-stage pipeline obtains the correct result. At the same time, due to the design characteristics of the present application, partial multiplication summation and addition operations need to be performed in the second-stage pipeline, so the subsequent two instructions need to perform multiplication and addition together. It takes another two cycles, a total of 7 cycles to complete the two instructions, and not considering register conflicts. The present application greatly improves the efficiency of the processor when executing floating-point multiplication and addition related instructions, greatly reducing the execution cycle.

[0065] To summarize, the microprocessor architecture of the present application, through the pre-decoding unit in the instruction fetch stage and the buffer module in the decoding stage, enables the floating-point fused multiplication and addition, floating-point multiplication and floating-point addition instructions to maintain uninterrupted pipeline operation when a register conflict occurs, thereby significantly improving the execution efficiency of the processor; under the same pipeline stage, the number of cycles required to execute two related instructions is a minimum of 5 cycles and a maximum of 7 cycles, avoiding the problem in the prior art that floating-point multiplication and addition operation instructions with similar pipeline stages require at least 9 cycles when a register conflict occurs, thereby shortening the execution cycle, improving instruction operation efficiency, and balancing the high performance and high energy efficiency of the microprocessor.

[0066] It should be noted that, for those skilled in the art, various improvements and modifications may be made to the present invention without departing from the principles of the present invention, and such improvements and modifications also fall within the scope of protection of the claims of the present invention. It should be understood that certain features of the present invention described in the context of separate embodiments for the sake of clarity may also be provided in combination in a single embodiment. Conversely, various features of the present invention described in the context of a single embodiment for the sake of clarity may also be provided individually or in any suitable combination or as any other described embodiment of the present invention.

Claims

1. A multi-precision floating-point fusion multiplication and addition structure, characterized in that: include: The first-stage pipeline includes an input preprocessing module, a Booth encoder, a tree array multiplier, an exponential order difference module, and a symbolic logic module. The input preprocessing module is used to decompose the input operand to obtain a sign bit, an exponent bit, and a mantissa bit; the symbolic logic module is used to determine the sign bit of the operand; the exponential order difference module is used to perform order difference calculation on the exponent bit in combination with the sign bit to determine the exponent difference; the Booth encoder encodes the mantissa bit using a radix-4 Booth encoding algorithm to generate partial products, and the tree array multiplier is used to compress the partial products into three groups of partial products. The second-stage pipeline includes a CSA 4-2 compression adder, an alignment shift module, and an adder module, wherein the alignment shift module is used to calculate the size of the alignment shift according to the exponent difference and perform shift alignment on the mantissa bits; the CSA 4-2 compression adder is used to compress the three groups of partial products and the mantissa bits after the shift alignment into two groups of partial products; the adder module is used to sum the two groups of partial products to obtain a mantissa sum result; The third-stage pipeline includes a leading zero detection module, an exponent logic module, and a shift logic module. The leading zero detection module is used to perform leading zero detection on the mantissa summation result and output the number of leading zeros. The exponent logic module is used to perform exponent adjustment on the number of leading zeros. The shift logic module performs mantissa adjustment on the number of leading zeros to obtain a normalized result. The fourth stage pipeline includes a rounding module, which rounds the floating point data according to the normalization result and the rounding mode instruction.

2. The multi-precision floating-point fusion multiplication-addition structure according to claim 1, characterized in that: In the first-stage pipeline, the input preprocessing module performs an abnormality judgment on the input operand based on the decomposed sign bit, exponent bit and mantissa bit. If the operand is a NAN value or an infinite value, the operation is stopped and the result and status are directly output.

3. The multi-precision floating-point fusion multiplication-addition structure according to claim 1, characterized in that: In the first-stage pipeline, the first-stage pipeline includes a buffer for caching floating-point instructions and operands contained in the floating-point instructions, and transmitting them to the second-stage pipeline.

4. The multi-precision floating-point fusion multiplication-addition structure according to claim 1, characterized in that: In the low-precision floating-point multiplication and addition operation, an 11×11 bit multiplier is used; in the floating-point mantissa multiplication, two low-precision mantissa multiplication results are generated in parallel and implemented using single-precision floating-point mantissa multiplication. The 11×11 bit multiplier uses a Booth encoder.

5. The multi-precision floating-point fusion multiplication-addition structure according to claim 4, characterized in that: The expression for compressing the partial products into three groups of partial products by the tree array multiplier is: ； Among them, the partial products compressed by the tree array multiplier are determined by the maximum height sequence d j where j is the initial value satisfying d j which is the maximum value less than min(n1, n2), where n1 and n2 are the number of bits of the input multiplicand and multiplier respectively.

6. The multi-precision floating-point fusion multiplication-addition structure according to claim 1, characterized in that: In the single-precision floating-point multiplication-addition operation, four 11×11-bit multipliers, four 2×11-bit multipliers, and one 2×2-bit multiplier are used to implement single-precision floating-point mantissa multiplication.

7. The multi-precision floating-point fusion multiplication-addition structure according to claim 6, characterized in that: The 2×11 bit multiplier includes two 13-bit data selectors and an adder. The input multipliers of the data selectors are all 11 bits, and the control signals of the data selectors are all 2 bits.

8. The multi-precision floating-point fusion multiplication-addition structure according to claim 1, characterized in that: In the second-stage pipeline, the floating-point instruction includes at least one of a floating-point multiplication instruction, a floating-point addition instruction, and a floating-point multiply-add instruction; If there are two related consecutive floating-point instructions and there is a register conflict, when the first instruction contains a floating-point multiplication instruction and the second instruction is a floating-point addition instruction, the floating-point multiplication is executed first and the floating-point addition is executed in the next clock cycle; If there are two related consecutive floating-point instructions and there is a register conflict, when the first instruction is a floating-point addition instruction and the second instruction contains a floating-point multiplication instruction, the floating-point addition is executed first, and then paused in the next clock cycle. After the result of the floating-point addition is forwarded to the first stage of the pipeline, the floating-point multiplication is executed; If two floating-point instructions are unrelated, they are executed in the original order.

9. The multi-precision floating-point fusion multiplication-addition structure according to claim 8, characterized in that: In the second stage pipeline, the execution of floating-point multiplication and floating-point addition is controlled by a state machine.

10. The multi-precision floating-point fusion multiplication-addition structure according to claim 8, characterized in that: If there are two related consecutive floating-point instructions, and the first instruction is a floating-point multiplication instruction and the second floating-point instruction is a floating-point addition instruction, the floating-point multiplication is executed in the first clock cycle; In a second clock cycle, the CSA 4-2 compression adder performs floating-point addition based on a first addition operand shift result of the first-stage pipeline, a floating-point mantissa multiplication result generated by the second-stage pipeline in the first clock cycle, and a second addition operand shift result; wherein the first addition operand shift result represents an exponential difference between exponents of the maximum operands in two related consecutive floating-point instructions in the first-stage pipeline in the second clock cycle, the second addition operand shift result represents an exponential difference between exponents of the maximum operands in two related consecutive floating-point instructions in the second-stage pipeline in the first clock cycle, and three of the four input ports of the CSA 4-2 compression adder are used.

11. The multi-precision floating-point fusion multiplication-addition structure according to claim 10, characterized in that: If the first floating-point instruction is a floating-point multiplication instruction, the second floating-point instruction is a floating-point multiply-add instruction, and the result of the floating-point multiplication instruction is the addition operand of the second floating-point instruction, then the floating-point multiplication of the first floating-point instruction is calculated in the second clock cycle to obtain a floating-point mantissa multiplication result; Using the floating-point mantissa multiplication result of the first floating-point instruction as the addition operand of the second floating-point instruction, and performing a shift operation based on the exponent difference between the maximum exponents of the two instructions; During a third clock cycle, the CSA 4-2 compression adder performs floating-point addition based on the three floating-point mantissa multiplication partial products of the second floating-point instruction and the floating-point mantissa multiplication result of the first floating-point instruction, and four of the four input ports of the CSA 4-2 compression adder are used.

12. The multi-precision floating-point fusion multiplication-addition structure according to claim 10, characterized in that: If the first of two floating-point instructions is a floating-point addition instruction, and the second floating-point instruction is a floating-point multiplication instruction or a floating-point multiply-add instruction, and the multiplication operand used by the second floating-point instruction is generated by the first floating-point instruction, the pipeline will be paused for one cycle when executing the second floating-point instruction.

13. The multi-precision floating-point fusion multiplication-addition structure according to claim 1, characterized in that: The rounding includes at least one of rounding to the nearest, rounding towards zero, rounding down, rounding up and rounding to the nearest.

14. A microprocessor architecture, characterized in that The microprocessor architecture includes a multi-precision floating-point fused multiply-add structure as described in any one of claims 1-13.

15. The microprocessor architecture according to claim 14, wherein: The microprocessor architecture includes: An instruction fetch module, configured to fetch a floating-point instruction, the instruction fetch module comprising a pre-decoding unit configured to decode a source register address; wherein the floating-point instruction comprises at least one of a floating-point multiply-add instruction, a floating-point multiplication instruction, and a floating-point addition instruction; A decoding module, comprising a buffer unit for caching a destination register address of a floating-point instruction; the decoding module is used to determine whether the destination register address is the same as the source register address, and whether there is a register conflict between the current floating-point instruction and the next floating-point instruction, so as to determine whether to pause the pipeline; An execution module, configured to send the current floating-point instruction into the floating-point fused multiply-add structure and obtain an execution result; The memory access module is used to write the execution result back to the register file to complete the instruction execution.

16. The microprocessor architecture according to claim 15, characterized in that: The decoding module is used to determine whether there is a register conflict between the current floating-point instruction and the next floating-point instruction. If there is a register conflict and the next instruction includes a floating-point multiplication instruction, the pipeline is paused for one cycle.

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