Layout and wiring planning design method based on 2.5 D core particle interconnection passive interposer

Abstract

The invention relates to a layout wiring planning design method based on a 2.5 D core particle interconnection interposer, which is characterized by comprising the following steps of: defining signal logic interfaces for automatic wiring in a passive interposer according to signal transmission requirements among core particles and a communication relationship between the core particles and a packaging substrate, and creating a mapping relationship list among the logic interfaces; according to the method, layout planning is carried out on physical interface endpoints of a passive intermediate layer, the physical interface endpoints are matched with signal logic interfaces, and an optimal layout allocation scheme is quickly determined through a signal allocation algorithm based on a flow network in combination with a window matching method, so that the wiring resource loss of a 2.5 D integrated circuit is effectively reduced, and the wiring efficiency is improved. The system overall performance is improved. According to the invention, the method can cope with a complex interconnection wiring condition generated by a plurality of independently designed core particles in a 2.5 D integration process, and achieves the efficient interconnection design of the passive interposer.

Description

Technical Field

[0001] The present invention belongs to the technical field of core particle interconnection, and in particular relates to a layout and routing planning design method based on a 2.5D core particle interconnection passive interposer. Background Art

[0002] With advances in semiconductor process technology, the effects of Moore's Law are gradually diminishing, and the cost and complexity of chip manufacturing are continuously increasing. Amidst challenges in chip heat dissipation, transmission bandwidth, and manufacturing yield, improving the performance of individual chips has encountered bottlenecks in power consumption, storage, and area. The emergence of chiplet technology offers a new solution to this problem. This technology allows bare dies from different manufacturers and processes to be fabricated into chiplets using internal interconnect technology. These chiplets are then integrated into a system-on-chip (SoC) using advanced packaging technology, enabling a new form of IP reuse. To efficiently integrate multiple chiplets, 2.5D and 3D packaging technologies are crucial. Among them, TSMC's CoWoS packaging technology, based on a passive interposer, has become one of the best solutions for improving system performance, reducing power consumption, and supporting heterogeneous integration. Compared to traditional 2D packaging, 2.5D packaging inserts a silicon interposer between the substrate and the chip, connecting the upper and lower metal layers with through-silicon vias (TSVs). This overcomes the difficulty of high-density wiring on the package substrate, which limits packaging density.

[0003] In the traditional design process, chiplets are typically designed independently, then placed on a passive interposer to complete the 2.5D package. Finally, internal interconnection between chiplets is completed on the passive interposer's RDL. This design process results in an illogical layout of the passive interposer's physical interfaces, requiring significant effort to resolve routing issues within the passive interposer. Furthermore, the passive interposer's physical interface layout and signal distribution significantly impact the wire length and number of metal layers used for 2.5D chiplet interconnects. Long interconnects degrade the performance of 2.5D integrated circuits and increase the manufacturing cost of the passive interposer. Therefore, minimizing the passive interposer's routing length and reducing routing resource consumption has become a key issue in 2.5D chiplet interconnect design. Summary of the Invention

[0004] The purpose of the present invention is to provide a layout and routing planning and design method based on a 2.5D chip interconnect passive interposer. By using a flow network-based signal allocation algorithm, the optimal layout allocation is obtained, thereby effectively reducing the wiring resource loss of the 2.5D integrated circuit and improving the performance of the 2.5D integrated circuit.

[0005] The above-mentioned purpose of the present invention is mainly achieved through the following technical solutions:

[0006] A layout and routing planning design method based on a 2.5D chip interconnection passive interposer includes the following steps:

[0007] (1) Based on the signal transmission requirements between the core particles and the communication relationship between the core particles and the package substrate, define the signal logic interface for automatic wiring inside the passive interposer and create a mapping relationship list between the logic interfaces;

[0008] (2) Plan the layout of the physical interface endpoints of the passive interposer, which include ubump and C4bump;

[0009] (3) matching the physical interface endpoints with the signal logic interface, performing signal allocation on the physical interface endpoints, and obtaining a signal matching result;

[0010] (4) Based on the signal matching result obtained in step (3), automatic wiring is performed between the physical interface endpoints to complete the layout and wiring planning design;

[0011] In step (3), the signal allocation method is a signal allocation algorithm based on a flow network, specifically as follows: i Establish flow network G for externally connected logical signals i , G i =(V i ,E i );

[0012] Among them, V i is the set of all nodes in the flow network, E i is the set of all paths in the flow network, V i ={s,t}∪U i ∪B i , where s is the flow network G i The source point, t is the flow network G i The meeting point, U i Core D i The ubump set of connected passive interposers, B i Core D i The collection of C4bumps in the passive interposer within the window;

[0013] In the flow network G i In the example, the capacity of each path is 1, the cost of each path leaving s or entering t is 0, and u i,x ∈U i , b i,y ∈B i , from u i,x to b i,y The fees are:

[0014] C(u i,x ,bi,y )=α i ×WC(u i,x ,b i,y )

[0015] WC(u i,x ,b i,y ) indicates the physical interface endpoint u i,x To physical interface endpoint b i,y The wiring length, α i Indicates the physical interface endpoint u i,x Weight parameter of the matched logic signal.

[0016] In the step (1), the signal logic interface and mapping relationship include signals that need to be interconnected between core particles through the passive interposer RDL and signals that need to be led out to the packaging substrate through the passive interposer RDL and TSV.

[0017] The ubump is used for data transmission between the passive interposer and the chip, and the C4 bump is used for data transmission between the passive interposer and the package substrate. The layout planning of the ubump is determined according to the arrangement layout of the chip and the position coordinates of the physical interface endpoints of the chip itself; the layout planning of the physical interface endpoint C4 bump is based on the spacing requirements of the C4 bump to build a C4bump network array for G i Execute the MCMF algorithm and obtain the signal matching result of the C4 bump of the physical interface endpoint based on the algorithm result.

[0018] The MCMF algorithm speed is improved by using a window matching method, which is as follows:

[0019] (1) Create a center u for each ubump i,x Window w i,x , window w i,x Length and width are both 2×m pitch , where m pitch is the spacing of C4 bumps;

[0020] (2) The number of ubumps is less than the number of C4 bumps of the assigned candidates, that is, B(w i,x )-U(w i,x )≥λ, where, U(w i,x ) and B(w i,x ) represent window w i,x The number of ubump and C4 bump contained in it, if B(w i,x )-U(w i,x )<λ, then m pitch Iterate the expansion window w i,x The size of B(wi,x )-U(w i,x )≥λ, get the window w i,x ;

[0021] Stream Network G i During the execution of the algorithm, it is only necessary to construct the window w i,x The path from each ubump to C4bump in the range.

[0022] In step (3), if the ubump and C4 bump cannot be vertically interconnected, a signal allocation algorithm based on a flow network is used. If the ubump and C4 bump can be vertically aligned, a C4 bump with a logical interconnection relationship is directly created based on the ubump coordinates.

[0023] In the step (4), the automatic wiring between the physical interface endpoints adopts the NDR wiring rule, and utilizes the shield metal wire to shield the crosstalk effect.

[0024] Divide the signal matching priority according to the signal rate, and set a larger weight parameter α for signals with high signal rates i .

[0025] A method for preparing a 2.5D core interconnect system based on a passive interposer comprises the following steps:

[0026] (1) According to the layout and routing planning and design method according to any one of claims 1 to 7, a redistribution layer, TSV and C4 bump layout are performed on a bare wafer to obtain a passive interposer;

[0027] (2) Flip and align the core with micro-bumps on the front side and bond it face-to-face with the ubump of the passive interposer;

[0028] (3) The passive interposer obtained in step (2) is electrically connected to the package substrate through C4 bump to obtain a core particle interconnection system.

[0029] Compared with the prior art, the present invention has at least the following beneficial effects:

[0030] (1) The present invention provides a layout and routing planning method for a passive interposer in 2.5D chip interconnect technology. This method uses a flow network-based signal allocation algorithm to obtain the optimal layout allocation of physical interface endpoints and signal allocation, thereby effectively reducing the wiring resource loss of the 2.5D integrated circuit and improving the performance of the 2.5D integrated circuit.

[0031] (2) The embodiment of the present invention preferably adopts a weight allocation mechanism to divide the signal matching priority according to the signal rate, give priority to solving the transmission path problem of high-speed signals, and avoid signal attenuation caused by high-speed transmission.

[0032] (3) The embodiment of the present invention preferably adopts a window matching method to effectively reduce the number of paths in the flow network and improve the algorithm speed. Window matching is performed on the signal allocation algorithm to accelerate the MST topology range of each physical interface endpoint ubump through the window matching method, effectively reducing the number of paths in the flow network and improving the speed of the MCMF algorithm. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a structural diagram of the 2.5D chip interconnection system based on the passive interposer of the present invention;

[0034] Figure 2 This is an overall flow chart of the layout and routing planning design method based on the 2.5D chip interconnection passive interposer of the present invention;

[0035] Figure 3 This is a schematic diagram of the signal logic interface mapping relationship of the present invention;

[0036] Figure 4 Schematic diagram of the flow network in the signal layout allocation algorithm of the present invention. DETAILED DESCRIPTION

[0037] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments:

[0038] like Figure 1 The structure of the 2.5D chip interconnect system based on a passive interposer, described in this invention, includes interconnected chips, a passive interposer, and a packaging substrate, packaged using CoWoS technology. The process involves laying out the redistribution layer, TSVs, and C4 bumps on a bare wafer to create the passive interposer. The chip, with microbumps on the front, is then flipped, aligned, and bonded face-to-face to the bumps on the passive interposer. Finally, the entire system is electrically connected to the packaging substrate via the C4 bumps, enabling data transmission between multiple chips and interconnection between the chips and the packaging substrate. This technology can package components manufactured using different processes, with different functions, and by different manufacturers, creating a 2.5D heterogeneous integrated system to enhance functionality and improve performance.

[0039] The layout of the die on the passive interposer, as well as the layout and signal distribution of the ubump and C4 bump, will greatly affect the length of the interconnect wires in the 2.5D integrated system. Since long interconnects can degrade the performance of the 2.5D interconnect system, layout and routing planning in the passive interposer design process is crucial.

[0040] like Figure 2 As shown, the layout and routing planning design method based on the 2.5D core particle interconnection passive interposer of the present invention includes the following steps:

[0041] (1) Based on the signal transmission relationship between each chiplet and between the chiplet and the package substrate, define the signal logic interface for automatic wiring inside the passive interposer and create a mapping relationship list between the logic interfaces;

[0042] (2) Layout planning of the physical interface endpoints of the passive intermediary layer;

[0043] (3) Matching the physical interface endpoints and the signal logic interface, converting the wiring length minimization problem of the passive interposer into a signal allocation problem of the physical interface endpoints; obtaining the optimal layout allocation through a signal allocation algorithm based on a flow network;

[0044] (4) Based on the signal logic mapping relationship, use the tool to automatically wire the physical interface endpoints.

[0045] Specifically, the layout and routing planning and design method based on the 2.5D chip interconnection passive interposer according to an embodiment of the present invention is described in detail below with reference to the accompanying drawings.

[0046] In the step (4), for the automatic wiring between the physical interface endpoints, the NDR wiring rule is adopted to increase the width and spacing of the wiring to ensure signal integrity; at the same time, the shield metal wire is used to shield the crosstalk effect to ensure the stability of signal transmission.

[0047] like Figure 3 As shown, the passive interposer contains signals that need to be interconnected between die through the passive interposer RDL, as well as signals that need to be routed to the package substrate through the passive interposer RDL and TSV. By defining the signal logic interface and establishing the mapping relationship between signals, it provides a key basis for subsequent automatic routing tools.

[0048] The ubump is used for data transmission between the passive interposer and the chip, and the C4 bump is used for data transmission between the passive interposer and the package substrate. The layout planning of the ubump is determined according to the arrangement layout of the chip and the position coordinates of the physical interface endpoints of the chip itself; the layout planning of the physical interface endpoint C4 bump is based on the spacing requirements of the C4 bump to build a C4bump network array for G i Execute the MCMF algorithm and obtain the signal matching result of the C4 bump of the physical interface endpoint based on the algorithm result.

[0049] like Figure 4 As shown in the figure, it is specifically explained how to solve the problem of minimizing the wiring length of the passive interposer by using the signal distribution algorithm based on the flow network. i All logic signals that need to be connected to the outside world establish a flow network G i =(Vi ,E i ); where V i Represents the set of all nodes in the flow network, E i Represents the set of all paths in the flow network. V i ={s,t}∪U i ∪B i , where s and t represent the source and sink of the flow network respectively, U i Indicates core particle D i The ubump collection of the connected passive interposer (u i,x ∈U i ), B i Indicates core particle D i The set of C4 bumps in the passive interposer within the window (b i,x ∈B i ). In the flow network G i In the example, the capacity of each path is 1, the cost of each path leaving s or entering t is 0, and the cost of each path from a certain ubump u is 1. i,x To a certain C4 bump b i,y The fees are:

[0050] C(u i,x ,b i,y )=α i ×WC(u i,x ,b i,y )

[0051] WC(u i,x ,b i,y ) indicates the physical interface endpoint u i,x To physical interface endpoint b i,y The wiring length, α i Indicates the physical interface endpoint u i,x The weight parameters of the matched logic signals are divided into signal matching priorities according to the signal rate, and a larger weight value is set for high-speed signals to shorten the routing distance of high-speed signals as much as possible to avoid signal attenuation caused by data transmission. i After calculating the capacity and cost of each path, i Execute the MCMF algorithm and obtain the signal matching result of the C4 bump of the physical interface endpoint based on the algorithm result.

[0052] The above flow network G iThe number of paths from all ubumps in the passive interposer to all C4 bumps is huge, which makes the execution speed of the MCMF algorithm slow. The embodiment of the present invention uses a window matching method to narrow the MST topology range of each physical interface endpoint ubump while ensuring that a feasible result is found, effectively reducing the number of paths in the flow network and improving the speed of the MCMF algorithm. First, for each ubump, create a center u i,x Window w i,x , its length and width are both 2×m pitch , where m pitch Indicates the spacing of C4 bump. U(w i,x ) and B(w i,x ) represent window w i,x The number of ubumps and C4 bumps contained in B(w) is less than the number of C4 bumps in the candidate assignments to ensure that the method can find a feasible signal assignment result. i,x )-U(w i,x )≥λ. If B(w i,x )-U(w i,x )<λ, then m pitch Iterate the expansion window w i,x Until the conditions are met. Finally, for the flow network G i , during the execution of the algorithm, it is only necessary to build the window w i,x By finding the path from each ubump to C4 bump within the range, the number of paths in the flow network can be effectively reduced, thus improving the execution speed of the algorithm.

[0053] The above description is only the best specific implementation method of the present invention, but the scope of protection of the present invention is not limited thereto. Any changes or replacements that can be easily thought of by any technician familiar with this technical field within the technical scope disclosed by the present invention should be covered by the scope of protection of the present invention.

[0054] The contents not described in detail in the specification of the present invention belong to the common knowledge of professionals in this field.

Claims

1. A layout and routing planning and design method based on a 2.5D chip interconnection passive interposer, characterized by: The following steps are involved: (1) Based on the signal transmission requirements between the chiplets and the communication relationship between the chiplets and the package substrate, define the signal logic interface for automatic wiring inside the passive interposer and create a mapping relationship list between the logic interfaces; (2) Plan the layout of the physical interface endpoints of the passive interposer, which include ubump and C4bump; (3) matching the physical interface endpoints with the signal logic interface, performing signal allocation on the physical interface endpoints, and obtaining a signal matching result; (4) Based on the signal matching result obtained in step (3), automatic wiring is performed between the physical interface endpoints to complete the layout and wiring planning design; In step (3), the signal allocation method is a signal allocation algorithm based on a flow network, specifically as follows: i Establish flow network G for externally connected logical signals i , G i =(V i ,E i ); Among them, V i is the set of all nodes in the flow network, E i is the set of all paths in the flow network, V i ={s,t}∪U i ∪B i , where s is the flow network G i The source point, t is the flow network G i The meeting point, U i Core D i The ubump set of connected passive interposers, B i Core D i The collection of C4bumps in the passive interposer within the window; In the flow network G i In the example, the capacity of each path is 1, the cost of each path leaving s or entering t is 0, and u i,x ∈U i , b i,y ∈B i , from u i,x to b i,y The fees are: C(u i,x ,b i,y )=α i ×WC(u i,x ,b i,y ) WC(u i,x ,b i,y ) indicates the physical interface endpoint u i,x To physical interface endpoint b i,y The wiring length, α i Indicates the physical interface endpoint u i,x Weight parameter of the matched logic signal.

2. The layout and routing planning and design method based on a 2.5D chip interconnect passive interposer according to claim 1, characterized in that: In the step (1), the signal logic interface and mapping relationship include signals that need to be interconnected between core particles through the passive interposer RDL and signals that need to be led out to the packaging substrate through the passive interposer RDL and TSV.

3. The layout and routing planning and design method based on a 2.5D chip interconnect passive interposer according to claim 1, characterized in that: The ubump is used for data transmission between the passive interposer and the chip, and the C4 bump is used for data transmission between the passive interposer and the package substrate. The layout planning of the ubump is determined according to the arrangement layout of the chip and the position coordinates of the physical interface endpoints of the chip itself; the layout planning of the physical interface endpoint C4 bump is based on the spacing requirements of the C4 bump to build a C4 bump network array. i Execute the MCMF algorithm and obtain the signal matching result of the C4 bump of the physical interface endpoint based on the algorithm result.

4. The layout and routing planning and design method based on a 2.5D chip interconnect passive interposer according to claim 3, characterized in that: The MCMF algorithm speed is improved by using a window matching method, which is as follows: (1) Create a center u for each ubump i,x Window w i,x , window w i,x Length and width are both 2×m pitch , where m pitch is the spacing of C4bump; (2) The number of ubumps is less than the number of C4 bumps of the assigned candidates, that is, B(w i,x )-U(w i,x )≥λ, where, U(w i,x ) and B(w i,x ) represent window w i,x The number of ubump and C4 bump contained in it, if B(w i,x )-U(w i,x )<λ, then m pitch Iterate the expansion window w i,x The size of B(w i,x )-U(w i,x )≥λ, get the window w i,x ; Stream Network G i During the execution of the algorithm, it is only necessary to construct the window w i,x The path from each ubump to C4bump in the range.

5. The layout and routing planning and design method based on a 2.5D chip interconnect passive interposer according to claim 1, characterized in that: In step (3), if the ubump and C4 bump cannot be vertically interconnected, a signal allocation algorithm based on a flow network is used. If the ubump and C4 bump can be vertically aligned, a C4 bump with a logical interconnection relationship is directly created based on the ubump coordinates.

6. The layout and routing planning and design method based on a 2.5D chip interconnection passive interposer according to claim 1, characterized in that: In the step (4), the automatic wiring between the physical interface endpoints adopts the NDR wiring rule, and utilizes the shield metal wire to shield the crosstalk effect.

7. The layout and routing planning and design method based on a 2.5D chip interconnection passive interposer according to claim 1, characterized in that: Divide the signal matching priority according to the signal rate, and set a larger weight parameter α for signals with high signal rates i .

8. A method for fabricating a 2.5D chip interconnect system based on a passive interposer, characterized by: The following steps are involved: (1) According to the layout and routing planning and design method according to any one of claims 1 to 7, a redistribution layer, TSV and C4 bump layout are performed on a bare wafer to obtain a passive interposer; (2) Flip and align the core with micro-bumps on the front side and bond it face-to-face with the ubump of the passive interposer; (3) The passive interposer obtained in step (2) is electrically connected to the package substrate through C4 bump to obtain a core particle interconnection system.

9. A 2.5D chip interconnect system based on a passive interposer, characterized by: Prepared according to the preparation method according to claim 8.

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