Multi-level PDN modeling optimization method and system based on advanced packaging

Abstract

The invention provides a multi-level PDN modeling optimization method and system based on advanced packaging, and belongs to the technical field of electrical packaging design, and the method comprises the steps: in multi-level packaging including a chip level, a packaging substrate level and a PCB level, under the condition that actual electromagnetic parameters, power supply layout, wiring topology and the actual length of a power supply loop of materials are considered, the actual length of the power supply loop is calculated; obtaining a PDN model for completing voltage stability and power supply capability under each level; through a three-dimensional loop path mapping algorithm and a target impedance rule, obtaining a PDN model of stable power supply of a power supply network in a full frequency band under different levels; obtaining a plurality of PDN optimization models under each level; and inputting one model under each level into the simulation tool at the same time to obtain an optimal PDN model under each level. The invention aims to solve the problem that only the mutual influence between electronic devices in the PDN model of each layer is considered when the PDN model is carried out on a PCB (Printed Circuit Board), a semiconductor and a chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of electrical packaging design, and specifically relates to a multi-level PDN modeling optimization method and system based on advanced packaging. Background Art

[0002] With the continuous advancement of semiconductor manufacturing and system integration technologies, System-in-Package (SiP) has become a key development direction for modern high-performance electronic systems. By integrating multiple chips, passive components, and other functional modules into a single package, SiP achieves system miniaturization, high speed, and low power consumption. However, this high level of integration also brings significant design challenges, particularly in the coordination between signal integrity (SI) and power integrity (PI). The transmission quality of high-speed links depends not only on the signal path itself but also on the design of the hierarchical power distribution network (PDN). Power supply noise, inductor resonance, and ground bounce within the PDN can cause signal jitter, eye diagram shrinkage, transmission delay, and in severe cases, system malfunction.

[0003] Traditional PDN modeling methods often use equivalent circuit models (such as RLC networks), which are suitable for low-frequency or single-layer analysis, such as modeling the power grid within a chip or the power supply layer network on a PCB. However, with increasing operating frequencies and structural complexity, this local modeling approach struggles to accurately reflect the global response characteristics of the PDN within the SiP structure. In particular, within the PDN path spanning the chip, package, and PCB layers, impedance jumps between layers, parasitic effects, and inductive coupling caused by vertical interconnects pose a serious threat to system stability. Previous studies have shown that PDNs are prone to generating multiple resonance points in the GHz frequency band. If these resonate at frequencies that overlap with signal paths, signal quality will be significantly degraded.

[0004] Furthermore, existing PDN modeling often simplifies package capacitor layout and packaging material parameters, making it difficult to simulate the resonant behavior of real devices with multiple capacitance values ​​and packaging combinations. For high-speed systems, decoupling capacitors not only provide filtering, but their layout, capacitance selection, and electrical parameter matching with the package substrate directly impact whether target impedance is achieved. In practical engineering, the target impedance method is widely used to evaluate PDN performance. However, if the model cannot accurately reproduce the impedance distribution in the frequency domain, the optimization results will lack a physical basis. Summary of the Invention

[0005] In order to solve the problem that in the current electrical component manufacturing process, the PDN model of the three-layer structure of chip, packaging substrate and PCB is modeled separately without considering the mutual influence between different layers, resulting in unsatisfactory modeling results, the present invention proposes a multi-level PDN modeling optimization method and system based on advanced packaging.

[0006] In order to achieve the above object, the present invention provides the following technical solutions: A multi-level PDN modeling and optimization method based on advanced packaging, comprising: Based on the actual electromagnetic parameters of the material, power supply layout, routing topology, and the actual length of the power loop, a PDN model is constructed to ensure voltage stability and power supply capability at each layer. A three-dimensional loop path mapping algorithm is used to determine the potential fluctuation and power jitter within the PDN model that ensures voltage stability and power supply capability at each level. Taking into account the potential fluctuation and power jitter within the PDN model that ensures voltage stability and power supply capability at each level, the target impedance rule is used to adjust the placement of decoupling capacitors within the PDN model that ensures voltage stability and power supply capability at different levels, thereby obtaining PDN models that ensure stable power supply across the entire frequency band for the power network at different levels. A variety of capacitor configuration combinations within the PDN model that ensures voltage stability and power supply capability can all yield PDN models that ensure stable power supply across the entire frequency band. Obtain the optimal configuration combination of multiple capacitor configurations for the PDN model at each level, ensuring stable power supply across the entire frequency band from the power network. Optimize the PDN model for stable power supply across the entire frequency band based on the optimal configuration combination of each capacitor configuration at each level, obtaining multiple PDN optimization models at each level. Select one PDN optimization model at each of the three levels, input all three models into the simulation tool simultaneously, and obtain the optimization results of the PDN design for high-speed link performance in each simulation. The PDN optimization model at each level that achieves the best optimization effect is recorded as the optimal PDN model at that level.

[0007] Furthermore, the specific steps of constructing a PDN model that completes voltage stability and power supply capability at each level are as follows: Use grid layout to build power or ground plane structure models at chip level, package substrate level and PCB level respectively; Taking into account the actual electromagnetic parameters of different materials, power supply layout, routing topology, and actual length of the power loop, electromagnetic simulation tools are used to model the PDN model at each level based on the power or ground plane structure models at the chip level, package substrate level, and PCB level. Multiple power ports are set up in each level of the PDN model, and decoupling capacitors are periodically arranged inside the chip-level PDN model. DC step-down simulation analysis is performed on each level of the PDN model to ensure the voltage stability and power supply capability of each level of the PDN model. It is ensured that the values ​​of each parameter at each level are within the allowable error range, and the PDN model with complete voltage stability and power supply capability at different levels is obtained.

[0008] Furthermore, the specific steps of obtaining the PDN model for stable power supply of the power network in the full frequency band at different levels are as follows: In the PDN model that completes voltage stability and power supply capability, set the power supply voltage, voltage tolerance, and maximum load current parameters within each PDN model layer. Use the target impedance rule to calculate the target impedance upper limit of each PDN model layer. Taking into account the potential fluctuations and power supply jitter within the PDN model that achieves voltage stability and power supply capability at each level, different types of bulk capacitors, on-chip capacitors, and decoupling capacitors with different frequency response characteristics are configured within each PDN model that achieves voltage stability and power supply capability. This ensures that the impedance of each PDN model in all frequency bands after capacitor configuration and voltage stability and power supply capability are all lower than the target impedance upper limit of the PDN model at that level. The model after capacitor configuration is recorded as a PDN model with stable power supply network across the entire frequency band.

[0009] Furthermore, the specific steps of obtaining the optimal configuration combination of multiple capacitor configurations of the PDN model at each level are as follows: Taking into account the target impedance upper limit of each PDN model, various capacitor configuration combinations are established for each PDN model layer by considering the capacitance, package type, quantity, and layout position of the capacitors within the PDN model to ensure stable power supply across the full frequency band. Each capacitor configuration combination of each level of the PDN model is mapped in the simulation platform. Taking the flatness of the target impedance, the frequency distribution of the resonance point, and the impedance peak suppression capability as the optimization goals, the optimal configuration combination of each capacitor configuration combination is obtained, which is recorded as the optimal configuration combination of the capacitor configuration.

[0010] Furthermore, the specific steps for obtaining the optimization effect of the PDN design on the high-speed link performance during each simulation are as follows: Based on the PDN optimization model at each level, the frequency domain characteristics of the PDN optimization models at different levels are converted into standard files that can be used for system simulation; A standard file of a PDN optimization model is selected at each of the three levels, and the three selected PDN optimization models are simultaneously input into the high-speed link signal path simulation to obtain the optimization effect of the PDN design on the high-speed link performance.

[0011] The present invention also provides a multi-level PDN modeling and optimization system based on advanced packaging, comprising: Initial PDN model construction module: This module takes into account the actual electromagnetic parameters of the materials, power supply layout, routing topology, and the actual length of the power loop to obtain a PDN model that completes voltage stability and power supply capabilities at each layer. The initial PDN model improvement module uses a three-dimensional loop path mapping algorithm to determine the potential fluctuation and power jitter within the PDN model that ensures voltage stability and power supply capability at each layer. Taking these fluctuations and jitter into account, the target impedance principle is used to improve the PDN models at different layers, resulting in PDN models that ensure stable power supply across the full frequency band for the power network at each layer. Acquisition module for optimized PDN models at each level: Acquire multiple capacitor configuration combinations for the PDN model at each level, map one capacitor configuration combination for each PDN model at three different levels to the same simulation platform, and obtain the overall optimization effect of the capacitor combination within the simulation platform during each simulation; record the capacitor configuration combination of the PDN model at each level corresponding to the simulation platform with the best overall optimization effect as the optimal capacitor configuration combination at that level; optimize the PDN model for stable power supply of the power network at that level within the full frequency band based on the optimal capacitor configuration combination at that level to obtain the optimized PDN model at each level.

[0012] The present invention provides a multi-level PDN modeling optimization method based on advanced packaging, which has the following beneficial effects: When constructing the PDN model of each level, the present invention takes into account the packaging material parameters, avoiding the problem that the current PDN modeling process simplifies the packaging material parameters, making it difficult for the PDN model constructed by the current method to simulate the resonant behavior of real devices under multiple capacitance values ​​and multiple packaging combinations; and when constructing the PDN model, the present invention uses a grid layout to optimize the return path when constructing the PDN model, and takes into account the length of the power supply loop in the modeling process, avoiding the current problem of ignoring the path length of the power supply loop in the PDN modeling process, resulting in insufficient evaluation of effects such as ground bounce and return inductance. When reducing the impedance response of the PDN model in the frequency domain, the present invention uses a three-dimensional loop path mapping algorithm to obtain the potential fluctuation and power supply jitter within the PDN model that completes voltage stability and power supply capability at each level, thereby enhancing the anti-interference capability of the constructed PDN model; when modeling the PDN model, the present invention considers the mutual influence of models between different levels, and when selecting the best PDN model for each level, the models of the three levels are simultaneously mapped to the simulation platform, and the three-level models with the best effect are selected as the best PDN models for each level, which solves the problem that when modeling the PDN model, the mutual influence between different levels is not considered, so that after the modeling is completed, each layer model may reach the local optimum, while the three-layer model does not reach the overall optimum. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] To more clearly illustrate the embodiments of the present invention and its design, the following briefly introduces the drawings required for this embodiment. The drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0014] Figure 1 This is a flowchart of a multi-level PDN modeling optimization method based on advanced packaging according to Example 1 of the present invention; Figure 2 A schematic diagram of the collaborative analysis process of the present invention; Figure 3 The location distribution map of the chip, package substrate, and PCB of the package; Figure 4 A flowchart to obtain the optimization effect of PDN design on high-speed link performance; Figure 5 Flowchart to obtain the optimization effect of PDN design on high-speed link performance. DETAILED DESCRIPTION

[0015] In order to enable those skilled in the art to better understand the technical solution of the present invention and to be able to implement it, the present invention is described in detail below with reference to the accompanying drawings and specific embodiments. The following embodiments are only used to more clearly illustrate the technical solution of the present invention and are not intended to limit the scope of protection of the present invention.

[0016] Example 1 The present invention provides a method for modeling and optimizing a cross-level power distribution network for advanced packaging, specifically Figure 1 As shown, including: Step S001: Based on the actual electromagnetic parameters of the material, power supply layout, routing topology, and the actual length of the power loop, a PDN model is constructed to complete voltage stability and power supply capability at each level.

[0017] It should be noted that current PDN modeling methods are limited to the electrical uniformity of a single layer, namely, the chip, package substrate, or PCB, making it difficult to truly reflect the coupling effects between multiple layers. Therefore, this paper constructs a PDN structure model across the chip, package substrate, and PCB layers.

[0018] It's important to note that when constructing a cross-layer PDN structure model encompassing chips, package substrates, and PCBs, we first analyze each layer individually using existing methods to determine the optimal structure for each layer. Within each layer's optimal structure, we then consider the interplay between different layers and modify the PDN model for each layer to achieve an overall optimal solution.

[0019] It should be further explained that, since the current PDN structure model for each level is often simplified in terms of package capacitance and package material parameters, making it difficult to simulate the resonant behavior of real devices with multiple capacitance values ​​and multiple package combinations, the present invention considers the electromagnetic parameters of the material, power supply layout, and routing topology when constructing the PDN model.

[0020] It should be further explained that the current PDN model often ignores the path length of the power loop, resulting in insufficient evaluation of effects such as ground bounce and return inductance. Therefore, in the process of constructing the PDN model, the present invention adopts a grid layout that can optimize the inductance characteristics of the return path. Figure 2 Schematic diagram of the process of this method.

[0021] Specifically, based on the actual structure, a grid-based layout was used on the simulation platform to construct power or ground plane structural models at the chip level, package substrate level, and PCB level. Taking into account the actual electromagnetic parameters of different materials, power supply layout, routing topology, and the actual length of the power loop, electromagnetic simulation tools were used to model the power or ground plane structural models at each level, resulting in a PDN model for each level. Figure 3 The location distribution diagram of the chip, package substrate and PCB board of the package is shown. Figure 3 The innermost red arrow in the diagram points to the chip, the middle red arrow points to the package substrate, and the outermost red arrow points to the PCB, which contains the package substrate, which in turn contains the chip. Constructing a PDN model at each level and building a power or ground plane structure model using a grid layout are both well-known techniques and are not detailed in this embodiment.

[0022] Furthermore, multiple power ports are set within the PDN model at each level, and decoupling capacitors are periodically arranged within the PDN model at the chip level. DC buck simulation analysis is performed on each PDN model to ensure the voltage stability and power supply capability of each PDN model, and to ensure that the values ​​of each parameter at each level are within the allowable error range, thereby obtaining a PDN model that achieves voltage stability and power supply capability at different levels. The setting of power ports within the PDN model at each level, the periodic arrangement of decoupling capacitors within the chip PDN model, and the performance of DC buck simulation analysis are all known technologies and are not described in detail in this embodiment.

[0023] At this point, a PDN model that achieves voltage stability and power supply capability at different levels is obtained.

[0024] Step S002: Using a three-dimensional loop path mapping algorithm, the potential fluctuation and power supply jitter status within the PDN model that achieves voltage stability and power supply capability at each level are obtained; considering the potential fluctuation and power supply jitter status within the PDN model that achieves voltage stability and power supply capability at each level, the layout of the decoupling capacitors within the PDN model that achieves voltage stability and power supply capability at different levels is adjusted using the target impedance rule to obtain PDN models that achieve stable power supply across the full frequency band for the power network at different levels.

[0025] It should be noted that when constructing a PDN model at each level, components such as power ports are first arranged within the PDN model. DC voltage drop simulation analysis is then used to ensure voltage stability and power supply capability for each level. The target impedance rule is then used to reduce the impedance response of the PDN model in the frequency domain. Therefore, the present invention optimizes the PDN model after achieving voltage stability and power supply capability, resulting in a PDN model with stable power supply across the entire frequency band.

[0026] It should be further explained that the current approach of reducing the PDN model's impedance response in the frequency domain through the target impedance rule ignores the issue of return path reconstruction, resulting in insufficient assessment of effects such as ground bounce linearity and return inductance. Therefore, when reducing the PDN model's impedance response in the frequency domain, the present invention uses a three-dimensional loop path mapping algorithm to analyze breakpoints and common-mode path migration in the signal or power return path. This captures ground potential fluctuations and power supply jitter caused by loop discontinuities, thereby enhancing the modeling capabilities of signal integrity (SI) and power integrity (PI) coupled interference.

[0027] Specifically, in the PDN model that completes voltage stability and power supply capability, parameters such as the power supply voltage, voltage tolerance, and maximum load current are set within each PDN model layer. The target impedance rule is used to calculate the target impedance upper limit for each PDN model layer. Calculating the target impedance upper limit for each layer is a well-known technique and is not detailed in this embodiment.

[0028] Furthermore, a three-dimensional loop path mapping algorithm is used to analyze signal / power return path breakpoints, common-mode path migration, and other behaviors within each layer of the PDN model, ensuring voltage stability and power supply capability. This analysis determines the potential fluctuation and power jitter within each layer of the PDN model, ensuring voltage stability and power supply capability. Calculating potential fluctuation and power jitter within each layer of the PDN model using the three-dimensional loop path mapping algorithm is well-known technology and will not be detailed in this implementation.

[0029] Furthermore, taking into account the potential fluctuation and power jitter factors within the PDN model that completes voltage stability and power supply capability at each level, decoupling capacitors such as body capacitors and on-chip capacitors of different types and frequency response characteristics are configured in each level of the PDN model that completes voltage stability and power supply capability, so that the impedance of each level of the PDN model that has configured capacitors and completed voltage stability and power supply capability in all frequency bands is lower than the target impedance upper limit of the PDN model at that level. The model after the capacitors are configured is recorded as a PDN model in which the power supply network provides stable power supply in the entire frequency band. Among them, configuring decoupling capacitors in the PDN model so that the impedance in the PDN model after the decoupling capacitors are configured is lower than the target impedance upper limit of the PDN model is an existing well-known technology and will not be elaborated in this embodiment.

[0030] At this point, a PDN model is obtained in which the power network at different levels provides stable power supply across the entire frequency band.

[0031] Step S003: Obtain the optimal configuration combination of multiple capacitor configurations of the PDN model with stable power supply of the power network in the full frequency band at each level; optimize the PDN model with stable power supply of the power network in the full frequency band according to the optimal configuration combination of each capacitor configuration of the PDN model with stable power supply of the power network in the full frequency band at each level, and obtain multiple PDN optimization models at each level; select a PDN optimization model at each of the three levels, input these three models into the simulation tool at the same time, and obtain the optimization result of the PDN design on the high-speed link performance in each simulation; record the PDN optimization model at each level corresponding to the best optimization effect as the best PDN model at that level.

[0032] It should be noted that, currently, under the premise of considering the target impedance upper limit of the PDN model at each level, multiple capacitor configuration combinations will be obtained. Therefore, the multiple capacitor configuration combinations are optimized to obtain the optimal combination of each capacitor configuration, and then multiple PDN optimization models at each level are obtained.

[0033] It should be further explained that in the PDN path across the three-layer structure of chip, package, and PCB, there will be inductive coupling caused by impedance jumps, parasitic effects, and vertical interconnections between the layers, that is, there will be mutual influence between different layers. Therefore, when selecting the optimal PDN model for each layer, the present invention simultaneously selects a PDN optimization model in each of the three layers, maps the three models into the simulation platform, and obtains the optimization effect of the PDN design on high-speed link performance during each mapping. The three PDN optimization models corresponding to the best optimization effect are recorded as the best models. This solves the problem of considering the mutual influence between different layers.

[0034] Specifically, considering the target impedance upper limit for each PDN model, various capacitor configuration combinations are established for each PDN model layer by determining the capacitance, package type, quantity, and layout position of capacitors within the PDN model for stable power supply across the full frequency band at each layer. Determining various capacitor configuration combinations for each PDN model based on the target impedance upper limit is a well-known technique and is not further described in this embodiment.

[0035] Furthermore, each capacitor configuration combination for each PDN model at each level was mapped within the simulation platform. Using the target impedance flatness, the frequency distribution of the resonant point, and the ability to suppress impedance spikes as optimization objectives, the optimal configuration combination for each capacitor configuration was obtained, denoted as the optimal capacitor configuration combination. Based on the optimal capacitor configuration combination for each PDN model at each level, the capacitor distribution within the PDN model at that level was modified to ensure stable power supply across the entire frequency band, resulting in multiple PDN optimization models at each level.

[0036] Furthermore, according to the PDN optimization model at each level, the frequency domain characteristics of the PDN optimization models at different levels are converted into standard files that can be used for system simulation. A standard file of a PDN optimization model is selected at each of the three levels, and the three selected PDN optimization models are simultaneously input into the high-speed link signal path simulation to obtain the optimization effect of the PDN design on the high-speed link performance. The flowchart of the method for obtaining the optimization effect of the PDN design on the high-speed link performance is shown in FIG. Figure 4 、 Figure 5 The method for obtaining the optimization effect of PDN design on high-speed link performance is a well-known technology and will not be described in detail in this embodiment.

[0037] Furthermore, the three PDN optimization models corresponding to the best PDN design optimization effect on high-speed link performance are recorded as the best PDN models at each level.

[0038] Another embodiment of the present invention further provides a multi-level PDN modeling optimization method based on advanced packaging, including: Initial PDN model construction module: This module takes into account the actual electromagnetic parameters of the materials, power supply layout, routing topology, and the actual length of the power loop to obtain a PDN model that completes voltage stability and power supply capabilities at each layer.

[0039] Improvement module for the initial PDN model: This module uses a three-dimensional loop path mapping algorithm to determine the potential fluctuation and power jitter within the PDN model that ensures voltage stability and power supply capability at each layer. Taking these fluctuations and jitter into account, the target impedance rule is used to improve the PDN models that ensure voltage stability and power supply capability at different layers, resulting in PDN models that ensure stable power supply across the full frequency band at each layer.

[0040] Acquisition module for optimized PDN models at each level: Acquire multiple capacitor configuration combinations for the PDN model at each level, map one capacitor configuration combination for each PDN model at three different levels to the same simulation platform, and obtain the overall optimization effect of the capacitor combination within the simulation platform during each simulation; record the capacitor configuration combination of the PDN model at each level corresponding to the simulation platform with the best overall optimization effect as the optimal capacitor configuration combination at that level; optimize the PDN model for stable power supply of the power network at that level within the full frequency band based on the optimal capacitor configuration combination at that level to obtain the optimized PDN model at each level.

[0041] Example 2: Step S1: Construct a cross-level PDN structure model of "chip-package-PCB" and a cross-level PDN impedance network to accurately capture physical phenomena such as capacitive coupling, ground bounce, and return path discontinuity in the vertical structure.

[0042] First, the ANSYS SIwave™ simulation platform was used to build a cross-level power distribution network model corresponding to the ceramic composite-based high-speed link structure, covering the three structural layers: PCB level, package level, and chip level.

[0043] Specifically, the power / ground plane design within the PDN structure utilizes a mesh approach to improve simulation accuracy and reduce errors caused by high-frequency parasitic effects. The PDN network is powered via four ports, located at the four corners of the chip structure, to simulate the power distribution behavior of a packaged system with multi-path power supply. Periodically spaced decoupling capacitors are introduced within the chip to suppress noise resonance in the mid- and high-frequency bands, improving the transient response capability of the local power network.

[0044] Next, DC IR Drop Analysis was performed to analyze the DC power supply capabilities of different PDN layers and assess the voltage drop distribution across the power plane under steady-state operating conditions. This ensured that, through the coordinated voltage allocation strategy and capacitor placement, all PDN layers met the design requirements for voltage stability and power noise suppression. This provided a solid power supply foundation and analytical basis for subsequent signal integrity simulation and system-level collaborative optimization.

[0045] Step S2: Use the target impedance rule to constrain the PDN impedance frequency domain characteristics, taking into account impedance jumps, parasitic inductance, and loop path discontinuity caused by interconnections.

[0046] In this step, the target impedance method is used as a guiding principle to constrain the impedance characteristics of the cross-layer PDN across the entire frequency range. This ensures that the power supply voltage fluctuation at the load end is within acceptable limits and meets the power integrity requirements of high-speed links. The target impedance is defined as the ratio of the power supply voltage fluctuation tolerance to the load current, describing the maximum impedance that the PDN can tolerate under dynamic operating conditions. In actual projects, to avoid overly conservative designs, a certain percentage of the maximum load current is often used as a reference for target impedance calculation.

[0047] During the modeling process, the PDN is considered a multi-stage resonant system. To achieve the target impedance constraint, "wideband low impedance" characteristics must be achieved in the frequency domain. The specific design strategy is as follows: First, bulk capacitors are used to provide energy support in the low-frequency band to ensure the system's low-frequency response capability. Second, multiple medium-capacity surface-mount capacitors (SMT capacitors) are introduced and placed on the package and PCB layers to control the mid-frequency impedance. Third, to address high-frequency current disturbances, planar capacitors, embedded capacitors, and on-chip package capacitors are rationally deployed to form a local high-frequency energy buffering mechanism, reducing resonant spikes and improving high-frequency impedance.

[0048] Furthermore, to address the inevitable impedance discontinuities, parasitic inductance effects, and loop path discontinuities caused by interconnections, the design employs multi-point decoupling, return path optimization, and a symmetrical topology layout to enhance the impedance stability of the overall PDN system across a wide frequency band. These multi-dimensional approaches collaboratively control the PDN impedance response, ensuring it remains below the target impedance threshold across the entire operating frequency range, effectively safeguarding load-side voltage stability and system signal integrity.

[0049] Step S3: Set up multiple groups of package capacitor configuration schemes, consider the capacitance value, package form and position layout, and further optimize the PDN structure with the target impedance flatness and resonance point shift as the optimization goals.

[0050] Based on the target impedance constraint that has been achieved, this step further optimizes the impedance characteristics of the multi-level PDN system. Specifically, by setting up multiple sets of package capacitor configuration schemes and adjusting their capacitance, package type, and layout position, the impedance flatness of the PDN within the target frequency range is improved and the system resonance point is effectively shifted.

[0051] First, for the PDN at the PCB, package, and chip levels, an initial PDN model is constructed based on the target impedance values ​​determined in the previous step. Subsequently, multiple capacitor configuration schemes are set for each PDN design level. The scheme parameters cover the following factors: 1) decoupling capacitor value distribution, including a mix of large, medium, and small capacitors; 2) capacitor packaging, including traditional surface-mount capacitors (such as MLCCs) and advanced packaged capacitors (such as embedded capacitors and package-embedded capacitors); and 3) capacitor physical layout, with a focus on strategies such as proximity to the load, proximity to the power inlet, and symmetrical placement.

[0052] Frequency-domain simulations were performed on multiple combinations of the aforementioned configurations to evaluate the impedance response curves of each solution within the operating frequency band. The optimization objectives were: 1) reducing the maximum impedance peak of the PDN within the critical signal frequency band, keeping it consistently below the target impedance threshold; 2) shifting or eliminating key resonant points to improve the flatness of the PDN frequency response; and 3) ensuring uniform distribution across resonant frequencies to avoid concentrated impedance spikes.

[0053] During the optimization process, non-ideal factors such as parasitic coupling between capacitors, return path delays caused by package traces, and electromagnetic interference must be considered. Ultimately, the package capacitor configuration that performs optimally across these multiple dimensions is selected as the final PDN design for this layer, achieving a low-impedance, low-noise power supply path in the high-frequency band and providing stable power support for high-speed signal links.

[0054] Step S4: Establish an SI / PI collaborative simulation model including the TX end, RX end, and cross-layer PDN structure to verify the impact of the PDN before and after optimization on the high-speed link performance.

[0055] First, the frequency-domain impedance characteristics of the PDNs at the PCB, package, and chip levels, obtained in the previous step, were converted into a standard modeling data format (such as Multi-Domain Format (MDF)) to ensure that these impedance characteristics could be recognized by the system-level simulation platform. Using the data access interface modules supported by the simulation tool (Keysight ADS), these PDN models were modularly embedded into the high-speed link simulation system.

[0056] Secondly, for the high-speed signal path, a three-dimensional full-wave simulation method (such as an electromagnetic field solver based on the finite element or finite difference method) is used to build a signal path model including the transmitter (TX), receiver (RX) and intermediate interconnection structure, and it is exported as a network parameter file (such as an SNP file in Touchstone format) for coupling and integration with the PDN model.

[0057] After the collaborative simulation model was established, a joint analysis was performed in both the frequency and time domains based on the simulation platform. In the frequency domain, S-parameters were used to analyze the insertion loss, return loss, and crosstalk characteristics of the link at each frequency point, quantifying the impact of PDN changes on the impedance matching of the signal transmission path. In the time domain, eye diagrams were used to analyze the signal waveform quality of the link under high-speed switching conditions, including indicators such as jitter, signal swing, eye height and eye width, and to evaluate the potential disturbance effect of PDN noise coupling on data integrity.

[0058] Furthermore, simulation comparisons will be conducted by modeling and simulating both unoptimized and optimized PDN configurations to quantify the specific effects of the optimization measures on link performance. This will focus on the impact of PDN parasitic resonances, decoupling failures, and power return paths on signal timing stability, as well as their impact on overall system SI / PI coordination performance.

[0059] It should be noted that the specific embodiments described above can enable those skilled in the art to more fully understand the present invention, but do not limit the present invention in any way. Therefore, although this specification and examples have described the present invention in detail, those skilled in the art should understand that the present invention can still be modified or replaced with equivalents; and all technical solutions and improvements that do not depart from the spirit and scope of the present invention are included in the scope of protection of the patent for the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A multi-level PDN modeling optimization method based on advanced packaging, characterized in that: include: Based on the actual electromagnetic parameters of the material, power supply layout, routing topology, and the actual length of the power loop, a PDN model is constructed to ensure voltage stability and power supply capability at each layer. A three-dimensional loop path mapping algorithm is used to determine the potential fluctuation and power jitter within the PDN model that ensures voltage stability and power supply capability at each level. Taking into account the potential fluctuation and power jitter within the PDN model that ensures voltage stability and power supply capability at each level, the target impedance rule is used to adjust the placement of decoupling capacitors within the PDN model that ensures voltage stability and power supply capability at different levels, thereby obtaining PDN models that ensure stable power supply across the entire frequency band for the power network at different levels. A variety of capacitor configuration combinations within the PDN model that ensures voltage stability and power supply capability can all yield PDN models that ensure stable power supply across the entire frequency band. Obtain the optimal configuration combination of multiple capacitor configurations for the PDN model at each level, ensuring stable power supply across the entire frequency band. Based on the optimal configuration combination of each capacitor configuration for the PDN model at each level, optimize the PDN model, ensuring stable power supply across the entire frequency band, and obtain multiple PDN optimization models at each level. Select a PDN optimization model at each of the three levels and input all three models into the simulation tool simultaneously to obtain the PDN design optimization results for high-speed link performance in each simulation. The PDN optimization model at each level corresponding to the best optimization effect is recorded as the best PDN model at that level.

2. A multi-level PDN modeling optimization method based on advanced packaging according to claim 1, characterized in that: The specific steps for constructing a PDN model that implements voltage stability and power supply capability at each level are as follows: Use grid layout to build power or ground plane structure models at chip level, package substrate level and PCB level respectively; Taking into account the actual electromagnetic parameters of different materials, power supply layout, routing topology, and actual length of the power loop, electromagnetic simulation tools are used to model the PDN model at each level based on the power or ground plane structure models at the chip level, package substrate level, and PCB level. Multiple power ports are set up in each level of the PDN model, and decoupling capacitors are periodically arranged inside the chip-level PDN model. DC step-down simulation analysis is performed on each level of the PDN model to ensure the voltage stability and power supply capability of each level of the PDN model. It is ensured that the values ​​of each parameter at each level are within the allowable error range, and the PDN model with complete voltage stability and power supply capability at different levels is obtained.

3. The multi-level PDN modeling optimization method based on advanced packaging according to claim 1 is characterized in that: The specific steps of obtaining a PDN model for stable power supply of the power network in the full frequency band at different levels are as follows: In the PDN model that completes voltage stability and power supply capability, set the power supply voltage, voltage tolerance, and maximum load current parameters within each PDN model layer. Use the target impedance rule to calculate the target impedance upper limit of each PDN model layer. Taking into account the potential fluctuations and power supply jitter within the PDN model that achieves voltage stability and power supply capability at each level, different types of bulk capacitors, on-chip capacitors, and decoupling capacitors with different frequency response characteristics are configured within each PDN model that achieves voltage stability and power supply capability. This ensures that the impedance of each PDN model in all frequency bands after capacitor configuration and voltage stability and power supply capability are all lower than the target impedance upper limit of the PDN model at that level. The model after capacitor configuration is recorded as a PDN model with stable power supply network across the entire frequency band.

4. The multi-level PDN modeling optimization method based on advanced packaging according to claim 1, characterized in that: The specific steps of obtaining the optimal configuration combination of multiple capacitor configurations of the PDN model at each level are as follows: Taking into account the target impedance upper limit of each PDN model, various capacitor configuration combinations are established for each PDN model layer by considering the capacitance, package type, quantity, and layout position of the capacitors within the PDN model to ensure stable power supply across the full frequency band. Each capacitor configuration combination of each level of the PDN model is mapped in the simulation platform. Taking the flatness of the target impedance, the frequency distribution of the resonance point, and the impedance peak suppression capability as the optimization goals, the optimal configuration combination of each capacitor configuration combination is obtained, which is recorded as the optimal configuration combination of the capacitor configuration.

5. The multi-level PDN modeling optimization method based on advanced packaging according to claim 1 is characterized in that: The specific steps for obtaining the optimization effect of the PDN design on the high-speed link performance during each simulation are as follows: Based on the PDN optimization model at each level, the frequency domain characteristics of the PDN optimization models at different levels are converted into standard files that can be used for system simulation; A standard file of a PDN optimization model is selected at each of the three levels, and the three selected PDN optimization models are simultaneously input into the high-speed link signal path simulation to obtain the optimization effect of the PDN design on the high-speed link performance.

6. A multi-level PDN modeling and optimization system based on advanced packaging, characterized in that: include: Initial PDN model construction module: This module takes into account the actual electromagnetic parameters of the materials, power supply layout, routing topology, and the actual length of the power loop to obtain a PDN model that completes voltage stability and power supply capabilities at each layer. The initial PDN model improvement module uses a three-dimensional loop path mapping algorithm to determine the potential fluctuation and power jitter within the PDN model that ensures voltage stability and power supply capability at each layer. Taking these fluctuations and jitter into account, the target impedance principle is used to improve the PDN models at different layers, resulting in PDN models that ensure stable power supply across the full frequency band for the power network at each layer. Acquisition module for optimized PDN models at each level: Acquire multiple capacitor configuration combinations for the PDN model at each level, map one capacitor configuration combination for each PDN model at three different levels to the same simulation platform, and obtain the overall optimization effect of the capacitor combination within the simulation platform during each simulation; record the capacitor configuration combination of the PDN model at each level corresponding to the simulation platform with the best overall optimization effect as the optimal capacitor configuration combination at that level; optimize the PDN model for stable power supply of the power network at that level within the full frequency band based on the optimal capacitor configuration combination at that level to obtain the optimized PDN model at each level.

7. A computer device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the method steps according to any one of claims 1 to 5 when executing the computer program.

8. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method steps according to any one of claims 1 to 5 are implemented.

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