Four-level discontinuous pulse width modulation method based on variable reference carrier

Abstract

The invention discloses a four-level discontinuous pulse width modulation method based on a variable reference carrier wave, which comprises the following steps: respectively injecting different zero sequence voltages into three-phase sinusoidal modulation waves to obtain a modulation signal 1, a modulation signal 2 and a modulation signal 3, the modulation signal 1 and the modulation signal 3 are obtained by injecting the same zero sequence voltage, and the modulation signal 1 and the modulation signal 3 are obtained by injecting the same zero sequence voltage; the values of different zero-sequence voltage coefficients are determined by the injected zero-sequence voltage signals; when the modulation signal 1 is larger than the carrier signal, the output state is the level P, otherwise, the output state is transited to the level O; when the modulation signal 3 is larger than the carrier signal, the output state is the level O, otherwise, the output state is transited to the level N; and when the modulation signal 2 is greater than the carrier signal, the output state is O2 level, otherwise, the output state is switched to O1 level. The neutral-point voltage balance control and switching loss optimization of the four-level NPC inverter are realized by injecting the optimized zero-sequence voltage component.

Description

Technical Field

[0001] The present invention relates to the technical field of four-level converter modulation, and in particular to a four-level discontinuous pulse width modulation method based on a variable reference carrier. Background Art

[0002] Multilevel inverters are widely used in medium-, high-voltage, and high-power applications due to their advantages, such as low output voltage harmonics and reduced switching device stress. Three-phase, four-level NPC inverters, in particular, further improve waveform quality by increasing the number of output levels. Existing four-level NPC topologies often use 18 or more switches, resulting in high conduction losses and complex modulation strategies. Furthermore, controlling the midpoint voltage balance of multilevel inverters is a major challenge. Traditional methods require complex algorithms or additional hardware circuitry, increasing system cost and reliability risks. Therefore, how to reduce the number of switches and simplify voltage balance control while maintaining performance through topology optimization and modulation strategy innovation has become a key research issue. Summary of the Invention

[0003] To overcome the above-mentioned deficiencies of the prior art, the present invention provides a four-level discontinuous pulse width modulation method based on a variable reference carrier, which realizes the midpoint voltage balance control and switching loss optimization of the four-level NPC inverter by injecting an optimized zero-sequence voltage component.

[0004] According to one aspect of the present invention, a four-level discontinuous pulse width modulation method based on a variable reference carrier is provided, comprising:

[0005] Different zero-sequence voltages are injected into the three-phase sinusoidal modulation wave to obtain modulation signal 1, modulation signal 2 and modulation signal 3, wherein modulation signal 1 and modulation signal 3 are obtained by injecting the same zero-sequence voltage, and the values ​​of different zero-sequence voltage coefficients are determined by the injected zero-sequence voltage signal;

[0006] When the modulation signal 1 is greater than the carrier signal, the output state is level P, otherwise, it transitions to level O;

[0007] When the modulation signal 3 is greater than the carrier signal, the output state is level O, otherwise, it transitions to level N;

[0008] When the modulation signal 2 is greater than the carrier signal, the output state is O2 level, otherwise, it switches to O1 level.

[0009] As a further technical solution, different zero-sequence voltage coefficients k1 and k2 are adjusted to generate different zero-sequence voltage components, thereby forming different modulation schemes.

[0010] As a further technical solution, the method further includes:

[0011] When the zero-sequence voltage coefficient (k1, k2) takes the value of (1, 1) and (0, 0), it corresponds to modulation scheme 1;

[0012] When the zero-sequence voltage coefficient (k1, k2) is (0.5, 1) or (0.5, 0), it corresponds to modulation scheme 2.

[0013] As a further technical solution, within one carrier cycle, the change in the voltage difference between the upper and lower capacitors is independent of the modulation signal after the zero-sequence voltage is injected.

[0014] As a further technical solution, a redundant clamping mechanism is adopted to achieve balanced control of the voltage between the upper and lower capacitors.

[0015] As a further technical solution, the zero-sequence voltage under the redundant clamping mechanism is expressed as:

[0016]

[0017] where u band is the voltage clamping boundary, u refx1.max 、u refx1.min u refa1 、u refb1 and u refc1 The maximum and minimum values ​​in u refx2.max 、u refx2.min for u refa2 、u refb2 and u refc2 The maximum and minimum values ​​in .

[0018] As a further technical solution, the method further includes:

[0019] When the zero-sequence voltage coefficient (k1, k2) takes the values ​​of (1, 1), (0, 0), (0.5, 1) and (0.5, 0), the voltage difference of the intermediate capacitor is not affected by the zero-sequence voltage coefficient.

[0020] As a further technical solution, the method further includes:

[0021] The voltage of the intermediate capacitor is dynamically adjusted using a proportional-integral controller.

[0022] According to one aspect of the present invention, a four-level discontinuous pulse width modulation device based on a variable reference carrier is provided, which is used to implement the four-level discontinuous pulse width modulation method based on a variable reference carrier.

[0023] According to one aspect of the present invention, a four-level inverter is provided, comprising an inverter body and the four-level discontinuous pulse width modulation device based on a variable reference carrier, wherein the four-level discontinuous pulse width modulation device based on a variable reference carrier is used to modulate the discontinuous pulse width of the inverter body.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] (1) Reduced switching losses: Dynamic switching is achieved by adjusting the dominant zero-sequence voltage coefficient. Compared with the traditional continuous pulse width modulation method, a unified discontinuous pulse width modulation method is proposed to achieve two types of variable reference carrier based discontinuous pulse width modulation (VRCB-DPWM). By utilizing the discontinuous modulation characteristics, redundant switching states are effectively reduced, thereby minimizing switching losses.

[0026] (2) Voltage balancing control: This paper investigates the influence of midpoint current distribution and its regulation mechanism by combining a zero-sequence voltage component injection mechanism. By injecting an optimized zero-sequence voltage component, the proposed control method balances the voltages of the upper and lower capacitors and dynamically adjusts the voltage of the middle capacitor using a proportional-integral controller, thereby ensuring stable operation of a four-level neutral point clamped (NPC) inverter. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, a brief introduction will be given below to the drawings used in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0028] Figure 1 A schematic diagram of a switching state sequence within a carrier cycle provided by an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of the flow path of the midpoint current provided in an embodiment of the present invention;

[0030] Figure 3 A schematic diagram showing the relationship between midpoint current, modulation coefficient, and power factor provided in an embodiment of the present invention;

[0031] Figure 4 The overall block diagram of the proposed method provided in an embodiment of the present invention.

[0032] Figure 5 Schematic diagram of experimental results of different modulation methods provided by embodiments of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention are arbitrarily combined with each other to form a new technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that this combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0034] The embodiment of the present invention proposes a variable-reference carrier based discontinuous pulse width modulation (VRCB-DPWM) method for neutral point voltage balance control and switching loss optimization of a four-level NPC inverter.

[0035] The modulation wave expression obtained by injecting zero-sequence voltage into the three-phase sinusoidal modulation wave is as follows:

[0036]

[0037] Taking sector 1 as an example, Figure 1 Shows u refx1z 、u refx2z and u refx3z The switching state sequence within one carrier cycle, where x = a, b or c. Figure 4 As shown, when u refx1z >V carr When u refx3z >V carr When u refx2z >V carr When , the output state corresponds to O2 level; otherwise, it switches to O1 level. Figure 1 In the equation, the values ​​of the zero-sequence voltage coefficients k1 and k2 are determined by the injected zero-sequence voltage (ZSV) signal. Applying the triangle similarity theorem, the following mathematical formula can be obtained:

[0038]

[0039] T z1 is the action time of zero sequence component 1, T z2 is the action time of zero sequence component 2, T s is the fundamental wave cycle time.

[0040] In sector 1, the maximum and minimum phases of the three reference signals are phases A and C, respectively. Similarly, injecting zero-sequence voltage into other sectors will produce similar results. Therefore, combining equations (1) and (2), the unified expression for zero-sequence voltage can be summarized as:

[0041]

[0042] Among them, u refx1.max and u refx1.min u refa1 、u refb1 and u refc1 The maximum and minimum values ​​in ;

[0043] Different zero-sequence voltage components can be generated by adjusting k1 and k2, which are summarized in Table 1.

[0044] Table 1 Zero-sequence voltage parameters of different modulation modes

[0045]

[0046] Assuming the output sinusoidal current i x for Among them, ω, and I m are the angular frequency, hysteresis angle, and current amplitude, respectively. φx (x = a, b, c) is equal to 0 for phase A, -2π / 3 for phase B, and 2π / 3 for phase C. Figure 2 The average pulse current i flowing from nodes N1 and N2 in one carrier cycle is shown in Figure 2. N1 and i N2 Respectively expressed as:

[0047]

[0048] Where: d x1 and d x2 (x=a、b、c) are the output level 2U dc / 3 and U dc In general, the switching frequency is much higher than the base frequency, so the reference signal can be regarded as a constant signal within one switching cycle. x1 and dx2 It can be expressed as:

[0049]

[0050] Then, the mathematical expressions of the voltages of the three capacitors during the carrier period are as follows:

[0051]

[0052] C represents the DC bus capacitance.

[0053] From formula (6), we can see that the capacitor voltage is determined by the midpoint current i during a switching process. N1 and i N2 The voltage difference between the upper and lower capacitors (expressed as Δu 13 ) is represented as follows:

[0054]

[0055] Formula (7) shows that the change in the voltage difference between the upper and lower capacitors depends on the node current i N and i N2 The sum of the reference signal u refx2z It doesn't matter, zero sequence voltage u zsv2 The injection does not affect the voltage difference between the upper and lower capacitors.

[0056] Figure 3 Shows different zsv1 The relationship between midpoint current, modulation coefficient and power factor during injection. Figure 3 (c) is shown. Figure 3 (c) It can be seen that and m∈[0,1.15], the charge Q np_sum This indicates that when k1=1, the discharge amount of the upper capacitor C1 is greater than the accumulation amount, while the accumulation amount of the lower capacitor C3 is greater than the discharge amount. Figure 3 (d) to (f) show the midpoint current and charge Q when k1 = 0 np_sum The corresponding result is exactly the opposite of k1=1. Specifically, when the phase voltage is clamped to level N, the charge of the upper capacitor C1 is greater than the discharge, while the discharge of the lower capacitor C3 is greater than the charge. 13 Based on the above analysis, the embodiment of the present invention proposes a redundant clamping mechanism to achieve balanced control of the upper and lower capacitor voltages. The zero-sequence voltage in this mode is expressed as:

[0057]

[0058] where u bandis the voltage clamping boundary. Although it was mentioned earlier that the zero sequence voltage u zsv2 Will not affect the upper and lower capacitor voltage Δu 13 , but when |Δu 13 |>u band When , k1 becomes the main zero-sequence voltage coefficient, and k2 is set equal to k1.

[0059] The voltage difference Δu2 of the intermediate capacitor can be expressed as:

[0060]

[0061] When the zero-sequence voltage coefficient (k1, k2) takes the values ​​of (1, 1), (0, 0), (0.5, 1) and (0.5, 0), the analytical expressions of the intermediate capacitor voltage difference Δu2 are shown in Equations (11)-(14).

[0062]

[0063] The analysis of the present invention is carried out under the assumption of a three-phase symmetrical system, that is, the algebraic sum of the three-phase current and voltage is zero. Under this assumption, the simplified results of formulas (11)-(14) are consistent with formula (10). Similarly, the same conclusion can be extended to other sectors. This shows that the values ​​of the zero-sequence voltage coefficients k1 and k2 do not affect the intermediate capacitor voltage difference, but are determined by the parameter s. Therefore, similar to the method of adjusting the intermediate capacitor voltage in the VRCB-CPWM method, the VRCB-DPWM method uses a proportional-integral controller to adjust the parameter s to ensure that the intermediate capacitor voltage U C2 Keep at 1 / 3U dc In summary, the overall framework of the proposed method is as follows Figure 4 shown.

[0064] Preferably, the present invention verifies the proposed method through experiments, and the suppression effect of different modulation methods on current ripple is as follows: Figure 5 The experimental results are summarized in Table 2.

[0065] Table 2 Efficiency and THD of different methods

[0066]

[0067]

[0068] In summary, although the DPWM-I method has a significant improvement in efficiency, its disadvantages are relatively high output current harmonic distortion and low-frequency voltage ripple (Δu 13 On the other hand, although the DPWM-II method is not the most efficient, it excels in reducing low-frequency voltage ripple and improving output current quality.

[0069] Based on the same inventive concept as the above embodiment, the embodiment of the present invention further provides a four-level discontinuous pulse width modulation device based on a variable reference carrier, which is used to implement the four-level discontinuous pulse width modulation method based on a variable reference carrier.

[0070] Specifically, the four-level discontinuous pulse width modulation device of the present invention includes:

[0071] A zero-sequence voltage injection module is used to inject different zero-sequence voltages into the three-phase sinusoidal modulation wave to obtain modulation signal 1, modulation signal 2, and modulation signal 3. Modulation signal 1 and modulation signal 3 are obtained by injecting the same zero-sequence voltage, and the values ​​of different zero-sequence voltage coefficients are determined by the injected zero-sequence voltage signal.

[0072] The dynamic switching module is used to output the state to level P when the modulation signal 1 is greater than the carrier signal, otherwise, it transitions to level O; when the modulation signal 3 is greater than the carrier signal, the output state is level O, otherwise, it transitions to level N; when the modulation signal 2 is greater than the carrier signal, the output state is level O2, otherwise, it switches to level O1.

[0073] Preferably, by adjusting different zero-sequence voltage coefficients k1 and k2, different zero-sequence voltage components are generated, thereby forming different modulation schemes.

[0074] Preferably, when the zero-sequence voltage coefficient (k1, k2) takes the value of (1, 1) or (0, 0), it corresponds to modulation scheme 1; when the zero-sequence voltage coefficient (k1, k2) takes the value of (0.5, 1) or (0.5, 0), it corresponds to modulation scheme 2.

[0075] Preferably, the four-level discontinuous pulse width modulation device further includes a upper and lower capacitor voltage difference balance control module, which adopts a redundant clamping mechanism to achieve balanced control of the voltage between the upper and lower capacitors. The zero-sequence voltage under the redundant clamping mechanism is expressed as:

[0076]

[0077] where u band is the voltage clamping boundary, u refx1.mx 、u refx1.min u refa1 、u refb1 and u refc1 The maximum and minimum values ​​in u refx2.mx 、u refx2.min for u refa2 、u refb2 and u refc2 The maximum and minimum values ​​in .

[0078] Preferably, the four-level discontinuous pulse width modulation device further comprises an intermediate capacitor voltage difference control module, which dynamically adjusts the voltage of the intermediate capacitor using a proportional-integral controller.

[0079] Based on the same inventive concept as the aforementioned embodiment, an embodiment of the present invention further provides a four-level inverter, comprising an inverter body and the four-level discontinuous pulse width modulation device based on a variable reference carrier, wherein the four-level discontinuous pulse width modulation device based on a variable reference carrier is used to modulate the discontinuous pulse width of the inverter body.

[0080] The embodiment of the present invention realizes dynamic switching of different discontinuous pulse width modulation technologies according to the dominant zero-sequence voltage coefficient, so as to ensure that the converter operates smoothly and safely at high efficiency.

[0081] The terms "including" and "having" and any variations thereof in the description and claims of the present invention and the above-mentioned drawings are intended to cover non-exclusive inclusions, for example, a process, method, system, product or apparatus that includes a series of steps or units is not necessarily limited to the steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products or apparatuses.

[0082] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically separate entities. That is, these functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily need to be executed in the order described. For example, some operations / steps may be further decomposed, while others may be combined or partially combined, so the actual execution order may vary depending on the actual situation.

[0083] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A four-level discontinuous pulse width modulation method based on a variable reference carrier, characterized in that: include: Different zero-sequence voltages are injected into the three-phase sinusoidal modulation wave to obtain modulation signal 1, modulation signal 2 and modulation signal 3, wherein modulation signal 1 and modulation signal 3 are obtained by injecting the same zero-sequence voltage, and the values ​​of different zero-sequence voltage coefficients are determined by the injected zero-sequence voltage signal; When the modulation signal 1 is greater than the carrier signal, the output state is level P, otherwise, it transitions to level O; When the modulation signal 3 is greater than the carrier signal, the output state is level O, otherwise, it transitions to level N; When the modulation signal 2 is greater than the carrier signal, the output state is O2 level, otherwise, it switches to O1 level.

2. A four-level discontinuous pulse width modulation method based on a variable reference carrier according to claim 1, characterized in that: By adjusting different zero-sequence voltage coefficients k1 and k2, different zero-sequence voltage components are generated, thereby forming different modulation schemes.

3. A four-level discontinuous pulse width modulation method based on a variable reference carrier according to claim 2, characterized in that: The method further comprises: When the zero-sequence voltage coefficient (k1, k2) takes the value of (1, 1) and (0, 0), it corresponds to modulation scheme 1; When the zero-sequence voltage coefficient (k1, k2) is (0.5, 1) or (0.5, 0), it corresponds to modulation scheme 2.

4. The four-level discontinuous pulse width modulation method based on a variable reference carrier according to claim 1, characterized in that: In one carrier cycle, the change of the voltage difference between the upper and lower capacitors has nothing to do with the modulation signal after the zero-sequence voltage is injected.

5. A four-level discontinuous pulse width modulation method based on a variable reference carrier according to claim 4, characterized in that: A redundant clamping mechanism is used to achieve balanced control of the voltage between the upper and lower capacitors.

6. A four-level discontinuous pulse width modulation method based on a variable reference carrier according to claim 5, characterized in that: The zero-sequence voltage under the redundant clamping mechanism is expressed as: where u band is the voltage clamping boundary, u refx1.max 、u refx1.mn u refa1 、u refb1 and u refc1 The maximum and minimum values ​​in u refx2.max 、u refx2.min for u refa2 、u refb2 and u refc2 The maximum and minimum values ​​in .

7. The four-level discontinuous pulse width modulation method based on a variable reference carrier according to claim 1, characterized in that: The method further comprises: When the zero-sequence voltage coefficient (k1, k2) takes the values ​​of (1, 1), (0, 0), (0.5, 1) and (0.5, 0), the voltage difference of the intermediate capacitor is not affected by the zero-sequence voltage coefficient.

8. A four-level discontinuous pulse width modulation method based on a variable reference carrier according to claim 7, characterized in that: The method further comprises: The voltage of the intermediate capacitor is dynamically adjusted using a proportional-integral controller.

9. A four-level discontinuous pulse width modulation device based on a variable reference carrier, characterized in that: Used to implement the four-level discontinuous pulse width modulation method based on a variable reference carrier as described in any one of claims 1 to 8.

10. A four-level inverter, comprising an inverter body, characterized in that: It also includes the four-level discontinuous pulse width modulation device based on a variable reference carrier as claimed in claim 9, wherein the four-level discontinuous pulse width modulation device based on a variable reference carrier is used to modulate the discontinuous pulse width of the inverter body.

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