Phase code digital low-pass filter circuit and PI-based retimer architecture

Abstract

This invention provides a phase code digital low-pass filter circuit and a re-timer based on a PI-based architecture. The phase code digital low-pass filter circuit includes a first accumulation unit and a downsampling decimation module. The first accumulation unit accumulates the initial frequency control information generated by the clock data recovery module of the re-timer to generate a phase signal. The downsampling decimation module downsamples the phase signal to generate a filtered phase code. The filtered phase code is used to generate the transmit channel clock. This invention effectively solves the problems of high implementation cost, large footprint, and easy introduction of additional analog non-ideal factors in existing digital filtering solutions.

Description

Technical Field

[0001] This invention relates to the field of high-speed signal transmission technology, and more specifically, to a phase code digital low-pass filter circuit and a re-timer based on a PI-based architecture. Background Technology

[0002] With the increasing demand for transmission bandwidth in applications such as large-scale data centers and high-performance computing, signal attenuation has become a more serious problem. The integrity and stability of signal transmission have become limiting factors for further increases in transmission speed and the continued expansion of transmission distance. Retimers offer a cost-effective solution to signal attenuation. Retimer chips have strong signal recovery capabilities and long data transmission distances, enabling large-scale data transmission in fields such as AI servers.

[0003] The primary function of a retimer is to recover the received signal and retransmit it, ensuring signal integrity and stability during long-distance transmission or in complex topologies. The retimer recovers the clock and retransmits the received data using a CDR (Clock Data Recovery). However, the clock recovered by the CDR often contains significant jitter, which affects the quality of the transmitted signal. During retransmission, noticeable jitter transfer occurs, further impacting signal quality and leading to performance degradation at the target node or the inability to fully recover the original data.

[0004] Figure 1 This is a simplified block diagram of a Retimer implemented based on a PI (Phase Interpolator)-based ADC (Analog to Digital Converter) + DSP (Digital Signal Processing) architecture, as shown below. Figure 1As shown, the data sampled by the ADC is processed in the DEMOD (demodulation) module, such as equalization and MLSD (Maximum Likeliness Sequence Detection) signal processing. On the one hand, it recovers the data sent by the TX (transmitter) end, outputs parallel symbol information (such as the initial transmitted data), and writes it into the FIFO (First In First Out) buffer using the RX (Receiver) clock. On the other hand, the DEMOD module contains TE (Timing Error) information generated by a TED (Timing Error Detector). For example, TED can obtain TE information through the BangBang-Phase Detector or the MM (Mueller-Muller Phase Detector).

[0005] Subsequently, the TE information is processed by a filter in the CDR Loop Filter to obtain the Phase Control signal (initial phase code). For example, the Loop Filter can be a second-order loop filter, a typical proportional-integral control system. The second-order loop filter controls the PI through two paths, where, for the first path, TE is multiplied by the Phase coefficient K. P For the second path, TE is multiplied by the integral coefficient K. I The signal is then accumulated to obtain the frequency offset signal, which is then accumulated onto the first path to obtain the initial frequency control information. The signal is then accumulated again to obtain the phase control signal, which is the PI Code (the initial phase code). The PI Code is used to control the RX PI (Receiver Phase Interpolator) to generate the RXClock (receive channel clock).

[0006] In practical use, the RX Clock recovered by the RX PI using the PI Code is directly used as the TXClock (transmit channel clock). However, due to factors such as input data and CDR implementation, there is also significant jitter in the RX Clock, so the TX Clock will also have significant jitter. That is, when the initial transmitted data is retransmitted based on the TX Clock, there is obvious jitter transfer, which causes the final target node to experience performance degradation or be unable to fully recover the initial transmitted data sent by the original node when receiving data, thus affecting the transmission performance of the Retimer.

[0007] To address the technical issues arising from the aforementioned Retimer architecture, existing solutions employ a filtered PLL (Phase Locked Loop) to track low-frequency jitter in the clock recovered by the CDR, while simultaneously filtering out high-frequency jitter; such as Figure 2 As shown, the clock recovered by CDR (essentially the RX Clock recovered by RX PI from the PI Code generated by CDR) is used to write the data output by DEMOD into the FIFO. At the same time, the clock recovered by CDR (essentially the RX Clock recovered by RX PI from the PI Code generated by CDR) is sent to a PLL for filtering to obtain the TX Clock for transmission. Subsequently, the TX Clock is used to read the data in the FIFO for transmission.

[0008] However, the existing solutions still suffer from high PLL implementation costs and large footprints; furthermore, the current solutions may introduce additional simulation non-ideal factors, leading to a decrease in the Jitter Tolerance performance of the target node.

[0009] Based on the aforementioned technical problems, there is an urgent need for a solution that is low-cost, occupies a small area, and does not introduce additional simulation non-ideal factors. Summary of the Invention

[0010] In view of the above problems, the purpose of this invention is to provide a phase code digital low-pass filter circuit and a retimer based on a PI-based architecture, so as to solve the problems of high implementation cost, large area occupation, and easy introduction of additional analog non-ideal factors in existing digital filtering solutions.

[0011] The phase code digital low-pass filter circuit provided by this invention is applied in a PI-based retimer and includes: a first accumulation unit and a downsampling decimation module; wherein,

[0012] The first accumulation unit is used to accumulate the initial frequency control information generated by the clock data recovery module of the retimer to generate a phase signal;

[0013] The downsampling extraction module is used to downsample and extract the phase signal to generate a filtered phase code;

[0014] The filtered phase code is used to generate the transmit channel clock.

[0015] Alternatively, the phase code digital low-pass filter circuit provided by the present invention further includes a dynamic range extension unit, which is used to extend the signal dynamic range of the phase signal so that the signal dynamic range of the phase signal is greater than the signal dynamic range of the initial phase code in the clock data recovery module.

[0016] Alternatively, the downsampling decimation module may include a decimation unit, a differential operation unit, a frequency correction unit, and a second accumulation unit; wherein,

[0017] The extraction unit is used to extract an accumulated value from the phase signal at each time interval;

[0018] The differential operation unit is used to perform differential operation on two consecutive accumulated values ​​extracted by the extraction unit to obtain the frequency offset information;

[0019] The frequency correction unit is used to multiply the frequency offset information by a scaling factor to obtain the frequency-corrected frequency offset information.

[0020] The second accumulation unit is used to accumulate the frequency offset information after frequency correction to obtain the filtered phase code.

[0021] Alternatively, the time control factor can be denoted as T, and the scaling factor as... ,but ; and / or,

[0022] The time control factor = , where n is an integer, n≥1.

[0023] Alternatively, the bandwidth of the phase code digital low-pass filter circuit can be adjusted based on the time control factor.

[0024] Alternatively, the initial frequency control information can be the sum of the output of the phase ratio channel and the output of the frequency offset channel in the clock data recovery module.

[0025] On the other hand, the present invention also provides a retimer based on a PI-based architecture, including an analog-to-digital conversion module, a demodulation module, a clock data recovery module, a transmitter phase interpolator, and the aforementioned phase code digital low-pass filter circuit; wherein,

[0026] The data sampled by the analog-to-digital conversion module is processed by the demodulation module to generate timing error information;

[0027] The clock data recovery module is used to generate initial frequency control information based on the timing error information;

[0028] The phase code digital low-pass filter circuit is used to perform digital low-pass filtering on the initial frequency control information to generate a filtered phase code.

[0029] The transmitting phase interpolator is used to generate the transmitting channel clock based on the filtered phase code.

[0030] Furthermore, an optional solution is that the PI-based retimer provided by this invention also includes a receiver phase interpolator; wherein,

[0031] The clock data recovery module is also used to generate an initial phase code, and the receiving phase interpolator is used to generate a receiving channel clock based on the initial phase code.

[0032] Furthermore, an optional solution is that the PI-based retimer provided by this invention also includes a first-in-first-out buffer; wherein,

[0033] The data sampled by the analog-to-digital conversion module is processed by the demodulation module to generate initial transmission data, which is written into the first-in-first-out buffer based on the clock of the receiving channel.

[0034] The initial transmission data stored in the first-in-first-out buffer is read out based on the transmission channel clock.

[0035] Furthermore, an alternative approach is that the PI-based retimer provided by this invention further includes a reference clock oscillator and a phase-locked loop (PLL), wherein the reference clock oscillator, in conjunction with the PLL, generates a reference clock; and,

[0036] Both the transmitting-end phase interpolator and the receiving-end phase interpolator are constructed based on the reference clock.

[0037] Compared with the prior art, the phase code digital low-pass filter circuit and the PI-based retimer provided by the present invention have the following advantages:

[0038] By setting up a phase code digital low-pass filter circuit that includes a first accumulation unit and a downsampling decimation module, it is possible to achieve digital low-pass filtering of the initial frequency control information to generate a filtered phase code, and generate a transmit channel clock that is different from the receive channel clock based on the filtered phase code. This ensures that there is no fixed frequency deviation between the receive channel clock and the transmit channel clock generated by the timer based on the PI-based architecture due to quantization error, and does not introduce additional analog non-ideal factors. Furthermore, the phase code digital low-pass filter circuit provided by this invention has low implementation cost and small footprint.

[0039] To achieve the foregoing and related objectives, one or more aspects of the invention include the features which will be described in detail below and specifically pointed out in the claims. The following description and accompanying drawings illustrate certain exemplary aspects of the invention. However, these aspects indicate only a few of the various ways in which the principles of the invention can be used. Furthermore, the invention is intended to include all such aspects and their equivalents. Attached Figure Description

[0040] Other objects and results of the invention will become more apparent and readily understood with reference to the following description taken in conjunction with the accompanying drawings and the contents of the claims, and with a more complete understanding of the invention. In the drawings:

[0041] Figure 1 For the existing retimer topology based on PI-based architecture;

[0042] Figure 2 A magnified view of a partial topology for filtering the clock recovered from a CDR using a filtering PLL;

[0043] Figure 3 A partially enlarged view of the topology of the phase code digital low-pass filter circuit provided in an embodiment of the present invention;

[0044] Figure 4 This is a topology for a retimer based on a PI-based architecture provided according to an embodiment of the present invention;

[0045] Figure 5 This is a diagram illustrating the phase accumulation result after extending the dynamic range of the phase signal according to an embodiment of the present invention. Detailed Implementation

[0046] In the following description, numerous specific details are set forth for illustrative purposes and to provide a thorough understanding of one or more embodiments. However, it will be apparent that these embodiments may also be implemented without these specific details. In other instances, well-known structures and devices are shown in block diagram form for ease of description of one or more embodiments.

[0047] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or server that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0048] In the several embodiments provided by this invention, it should be understood that the disclosed devices, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of modules is only a logical functional division, and other division methods may be used in actual implementation.

[0049] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0050] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0051] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be embraced within the present invention. No appended diagram markings in the claims should be construed as limiting the scope of the claims.

[0052] Figure 3 This diagram shows a partially enlarged topology of the phase code digital low-pass filter circuit provided in an embodiment of the present invention. Figure 4The topology of the retimer based on the PI-based architecture provided in the embodiment of the present invention is shown. Figure 5 A diagram illustrating the phase accumulation result after extending the dynamic range of the phase signal according to an embodiment of the present invention is shown.

[0053] Combination Figures 3 to 5 As can be seen, the phase code digital low-pass filter circuit provided by the present invention is applied in a PI-based retimer to generate a transmit channel clock. The phase code digital low-pass filter circuit includes: a first accumulation unit and a downsampling decimation module; wherein, the first accumulation unit is used to accumulate the initial frequency control information generated by the clock data recovery module of the retimer to generate a phase signal; the downsampling decimation module is used to downsample and decimate the phase signal obtained by accumulating the initial frequency control information to generate a filtered phase code; in the PI-based retimer, the filtered phase code generated by the phase code digital low-pass filter circuit is used to replace the initial phase code (generated by the clock data recovery module accumulating the initial frequency control information) to directly generate the transmit channel clock, and the transmit channel clock is subsequently used to retransmit the initial transmit data in the first-in-first-out buffer.

[0054] It should be noted that this invention is based on Figure 1 The existing PI-based retimer topology is shown. A phase code digital low-pass filter circuit is proposed to achieve the jitter reduction effect of the existing PI-based retimer architecture, such as... Figure 3 As shown, the solution provided by this invention sets up a phase code digital low-pass filter circuit on the CDR side of the existing PI-based retimer architecture. The PI Code (initial frequency control information) generated by the CDR is digitally low-pass filtered by the Digital Loop Filter (phase code digital low-pass filter circuit) provided by this invention. The filtered PI Code (filtered phase code) is used to control another TX PI (Transmitter Phase Interpolator, not the RX PI in the existing PI-based retimer architecture) to generate the TX Clock (transmit channel clock), thereby achieving the purpose of jitter elimination for the PI-based retimer architecture.

[0055] Compared with the traditional scheme of using PLL for digital low-pass filtering, the phase code digital low-pass filter circuit provided by this invention has low implementation cost, small footprint and low power consumption; at the same time, it can also solve the problem of fixed frequency deviation between RX Clock and TX Clock due to quantization error when using PLL to implement digital low-pass filtering; it can achieve low cost, high precision and high performance of timer jitter elimination based on PI-based architecture.

[0056] In one specific embodiment of the present invention, such as Figure 4 As shown, the PI-based retimer provided by this invention includes an analog-to-digital conversion module, a demodulation module, a clock data recovery module, a transmitting-end phase interpolator, a receiving-end phase interpolator, a first-in-first-out buffer, and the aforementioned phase code digital low-pass filter circuit. The analog-to-digital conversion module samples the required data, and the sampled data is sent to the demodulation module. The data is processed in the demodulation module, such as performing equalization and maximum likelihood sequence detection, to generate initial transmission data and timing error information. The clock data recovery module (corresponding to the clock data recovery loop filter) processes the timing error information and generates initial frequency control information based on the timing error information.

[0057] The phase code digital low-pass filter circuit provided by this invention is used to perform digital low-pass filtering on the initial control word to generate a filtered phase code. The subsequent transmitting end phase interpolator is used to generate the transmitting channel clock based on the filtered phase code. The clock data recovery module is also used to accumulate the initial frequency control information through its internal accumulation unit to generate the initial phase code. The receiving end phase interpolator is used to generate the receiving channel clock based on the initial phase code.

[0058] In practice, in the early stage, the data sampled by the analog-to-digital conversion module is processed by the demodulation module to generate the initial transmission data, which is written into the first-in-first-out (FIFO) buffer based on the receiving channel clock generated by the receiving end phase interpolator. In the later stage, the initial transmission data stored in the FIFO buffer (written based on the receiving channel clock) is read out based on the transmitting channel clock generated by the transmitting end phase interpolator to realize the retransmission of the initial transmission data.

[0059] It should be noted that the PI-based retimer provided by this invention typically also includes a reference clock oscillator and a phase-locked loop (PLL). The reference clock oscillator works in conjunction with the PLL to generate a reference clock. Furthermore, both the transmitting-end phase interpolator and the receiving-end phase interpolator are built based on the same reference clock.

[0060] The following is based on Figure 4 The structure shown illustrates the working principle of the PI-based retimer provided by this invention; for example... Figure 4 As shown, the ADC (Analog-to-Digital Converter) -> DEMOD (Demodulation Module) -> CDR (Clock Data Recovery Module) -> RX PI (Receiver Phase Interpolator) - ADC (Analog-to-Digital Converter) form the control loop of the receive channel clock, which is used to control the reception of data sent by the original node (mainly including the initial transmission data).

[0061] It should be noted that the PI-based retimer architecture provided in this invention includes two PIs: an RX PI (generated by the clock data recovery module to control the analog-to-digital conversion module, as used in existing solutions) and a TX PI (generated by the Retimer to retransmit data). To avoid clock errors between the two PIs, they are constructed using the same reference oscillator and a clock generated by the PLL. Furthermore, the phase signal controlling the TX PI subsequently undergoes digital low-pass filtering (i.e., downsampling) processing via the downsampling module in the phase code digital low-pass filter circuit provided in this invention. This filters out high-frequency jitter and a certain amount of low-frequency jitter in the phase signal, generating a filtered phase code to eliminate retimer jitter.

[0062] Furthermore, such as Figure 4 As shown, the phase code digital low-pass filter circuit provided by this invention needs to first receive the sum of the two channel signals in the CDR, one of which is the Phase Scaled channel (and K). P The corresponding channel), and another channel is the Frequency Offset Path (frequency offset channel, with K). I The outputs of the two channels are added together and the result is recorded as the aforementioned initial frequency control information. After obtaining the initial frequency control information, the phase code digital low-pass filter circuit provided by the present invention first accumulates the initial frequency control information through the first accumulation unit to generate a phase signal; then it performs downsampling and decimation on the phase signal through the downsampling and decimation module to obtain the filtered phase code.

[0063] In a specific embodiment of the present invention, to implement the downsampling decimation module for downsampling the phase signal to generate a filtered phase code, the downsampling decimation module may include a decimation unit, a differential operation unit, a frequency correction unit, and a second accumulation unit. The decimation unit is used to extract an accumulated value from the phase signal at each time interval using a control factor. The differential operation unit is used to perform a differential operation on two consecutive accumulated values ​​extracted by the decimation unit to obtain frequency offset information. The frequency correction unit is used to multiply the frequency offset information by a scaling factor to obtain frequency-corrected frequency offset information. The second accumulation unit is used to accumulate the frequency-corrected frequency offset information to obtain the filtered phase code. The phase code is subsequently used to control the phase interpolator at the transmitting end to generate the transmission channel clock. The T transmission channel clock is used to read the data written to the first-in-first-out buffer in the main path (such as the initial transmission data) and retransmit it.

[0064] It should be noted that, for the PI-based retimer provided by this invention, the initial transmission data output by DEMOD is written into the first-in-first-out buffer through the receiver channel clock generated by the receiver phase interpolator, and then read out through the transmitter channel clock generated by the transmitter phase interpolator, thereby achieving asynchronous processing and synchronization; and, the transmitter channel clock only contains a portion of low-frequency jitter, and high-frequency jitter has been filtered out, which can achieve the purpose of initial jitter removal.

[0065] Furthermore, it should be noted that the phase code digital low-pass filter circuit provided by the present invention, which includes a first accumulation unit, a decimation unit, a differential operation unit, a frequency trimming unit, and a second accumulation unit, has lower design cost and smaller footprint compared to existing filtering schemes that use PLLs. It also does not require a large number of shift registers as traditional schemes, while achieving high accuracy and avoiding the problem of fixed frequency deviation between the transmit channel clock and the receive channel clock due to quantization errors.

[0066] The time control factor can be denoted as T, and the scaling factor can be denoted as... At this time, Furthermore, the time control factor is preferably set to = (Number of Clocks), where n is an integer, n≥1.

[0067] In the phase code digital low-pass filter circuit provided by this invention, the length of the time control factor (T) determines the bandwidth of the digital low-pass filter circuit. A longer time control factor results in a smaller bandwidth, while a shorter time control factor results in a larger bandwidth. The bandwidth of the phase code digital low-pass filter circuit can be adjusted by regulating the time control factor. Furthermore, for simplicity, the time control factor is often preferably chosen to be a power of 2 clock cycles. This allows the division by the time control factor in the digital low-pass filter circuit to be implemented using a shift operation, further reducing implementation complexity and cost. Additionally, in the PI-based retimer architecture provided by this invention, there is no significant constraint on the timing margin between the clock used by the CDR and the clock used by the phase code digital low-pass filter circuit, meaning a large jitter range can be covered.

[0068] The phase signal dynamic range in the phase code digital low-pass filter circuit provided by this invention is larger than the dynamic range of the accumulated signal obtained by accumulating the initial frequency control information in CDR. That is, the number of times Phase Wrap Around or Phase Loop Around occurs within the time control factor range of the low-pass filter is less than or equal to 1.

[0069] Specifically, in the phase code digital low-pass filter circuit provided by the present invention, when the initial frequency control information is accumulated by the first accumulation unit in the first step, it is necessary to expand the signal dynamic range of the phase signal to ensure that the phase does not rotate multiple times within the time constant factor range under the maximum supported PPM (Parts Per Million, the difference in frequency between TX and RX), so that stable frequency offset information can be calculated. Figure 5 An extended dynamic range phase signal is shown, which ensures that at most one loop occurs between two phases of the time control factor, and is used to calculate frequency offset information.

[0070] As can be seen from the above specific embodiments, the phase code digital low-pass filter circuit and the PI-based retimer provided by the present invention have at least the following advantages:

[0071] 1. High-frequency jitter and some low-frequency jitter in the initial frequency control information are filtered out by a phase code digital low-pass filter circuit. The filtering is low in cost, occupies little area and consumes little power, and has a good jitter removal effect; and the implementation delay is small.

[0072] 2. The phase code digital low-pass filter circuit can ensure that there is no fixed frequency deviation caused by quantization error between the receiving channel clock and the transmitting channel clock, thus achieving high accuracy;

[0073] 3. Compared to existing digital low-pass filtering schemes that use phase-locked loops, this method does not introduce additional noise and offers relatively better performance.

[0074] 4. The phase code digital low-pass filter circuit has the advantages of simple implementation, low logic overhead, and stable performance;

[0075] 5. The bandwidth of the phase code digital low-pass filter circuit can be adjusted by adjusting the time control factor. A suitable balance point can be selected between jitter removal requirements and other performance requirements. For example, in scenarios that support SSC (Spread Spectrum Clocking), the bandwidth of the phase code digital low-pass filter circuit can be appropriately increased to track the frequency of SSC.

[0076] 6. Unaffected by PVT (Process Volage Temperature), its performance is consistent.

[0077] As per the above reference Figures 3 to 5 The phase code digital low-pass filter circuit and the PI-based retimer according to the present invention are described by way of example. However, those skilled in the art will understand that various modifications can be made to the phase code digital low-pass filter circuit and the PI-based retimer proposed in the present invention without departing from the scope of the invention. Therefore, the scope of protection of the present invention should be determined by the contents of the appended claims.

Claims

1. A phase code digital low-pass filter circuit; characterized in that, Applied to a PI-based retimer architecture, it includes: a first accumulation unit, a downsampling decimation module, and a dynamic range expansion unit; wherein, The first accumulation unit is used to accumulate the initial frequency control information generated by the clock data recovery module of the retimer to generate a phase signal; wherein, the initial frequency control information is the sum of the output of the phase ratio channel and the output of the frequency offset channel in the clock data recovery module; The dynamic range extension unit is used to extend the dynamic range of the phase signal so that the dynamic range of the phase signal is greater than the dynamic range of the initial phase code in the clock data recovery module. The downsampling decimation module is used to downsample and decimate the phase signal to generate a filtered phase code. The downsampling decimation module includes a decimation unit, a differential operation unit, a frequency correction unit, and a second accumulation unit. The decimation unit is used to extract an accumulated value from the phase signal at regular intervals using a control factor. The differential operation unit is used to perform a differential operation on two consecutive accumulated values ​​extracted by the decimation unit to obtain frequency offset information. The frequency correction unit is used to multiply the frequency offset information by a scaling factor to obtain frequency-corrected frequency offset information. The second accumulation unit is used to accumulate the frequency-corrected frequency offset information to obtain the filtered phase code. The filtered phase code is used to generate the transmit channel clock.

2. The phase code digital low-pass filter circuit as described in claim 1, characterized in that, The time control factor is denoted as T, and the scaling factor is denoted as... ,but ; and / or, The time control factor = , where n is an integer, n≥1.

3. The phase code digital low-pass filter circuit as described in claim 2, characterized in that, The bandwidth of the phase code digital low-pass filter circuit is adjusted based on the time control factor.

4. A retimer based on a PI-based architecture, characterized in that, It includes an analog-to-digital conversion module, a demodulation module, a clock data recovery module, a transmitter phase interpolator, and a phase code digital low-pass filter circuit as described in any one of claims 1 to 3; wherein, The data sampled by the analog-to-digital conversion module is processed by the demodulation module to generate timing error information; The clock data recovery module is used to generate initial frequency control information based on the timing error information; The phase code digital low-pass filter circuit is used to perform digital low-pass filtering on the initial frequency control information to generate a filtered phase code. The transmitting phase interpolator is used to generate the transmitting channel clock based on the filtered phase code.

5. The retimer based on a PI-based architecture as described in claim 4, characterized in that, It also includes a receiver phase interpolator; wherein, The clock data recovery module is also used to generate an initial phase code, and the receiving phase interpolator is used to generate a receiving channel clock based on the initial phase code.

6. The retimer based on a PI-based architecture as described in claim 5, characterized in that, It also includes a first-in-first-out buffer; among which, The data sampled by the analog-to-digital conversion module is processed by the demodulation module to generate initial transmission data, which is written into the first-in-first-out buffer based on the clock of the receiving channel. The initial transmission data stored in the first-in-first-out buffer is read out based on the transmission channel clock.

7. The retimer based on a PI-based architecture as described in claim 6, characterized in that, It also includes a reference clock oscillator and a phase-locked loop (PLL), wherein the reference clock oscillator works in conjunction with the PLL to generate a reference clock; and... Both the transmitting-end phase interpolator and the receiving-end phase interpolator are constructed based on the reference clock.

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