Fractional frequency divider and integrated circuit

Abstract

The embodiment of the invention discloses a fractional frequency divider and an integrated circuit, relates to the technical field of circuit design, and aims to enrich generation modes of fractional frequency division clock signals. The fractional frequency divider comprises a delay-locked loop used for generating a plurality of clock signals according to an original clock signal; the first state machine is used for generating a first clock selection signal and a second clock selection signal according to a preset frequency division step length; the first multi-channel clock signal selector is respectively connected with the delay phase-locked loop and the first state machine and is used for selecting a first target clock signal and a second target clock signal from the clock signals according to the first clock selection signal and the second clock selection signal; and the frequency division module is connected with the output end of the first multi-channel clock signal selector and is used for generating a fractional frequency division clock signal according to the first target clock signal and the second target clock signal. The method is suitable for performing fractional frequency division on the original clock signal.

Description

Technical Field

[0001] The present application relates to the field of circuit design technology, and in particular to a fractional frequency divider and an integrated circuit. Background Art

[0002] In large-scale integrated circuits (LSIs), clock signals drive sequential logic devices and determine the chip's operating frequency. As chip operating frequencies continue to increase, the requirements for clock signal quality are becoming increasingly stringent.

[0003] In the prior art circuit design, frequency division processing is performed according to the input clock signal source to generate a clock signal of a specific frequency. Figure 1 As shown, a conventional phase-locked loop (PLL) clock divider circuit includes a phase detector (PD), a loop filter (LF), a voltage-controlled oscillator (VCO), and a clock divider. By setting the division value of divider M or N, the input clock signal can be divided to obtain a clock signal of a specific frequency. However, the conventional method of frequency division, which is achieved by setting the division value, results in a relatively limited number of frequency division methods. Finding a more comprehensive range of frequency division methods is a technical problem that needs to be addressed by those skilled in the art. Summary of the Invention

[0004] In view of this, embodiments of the present application provide a fractional frequency divider and an integrated circuit, which can enrich the generation methods of fractional frequency clock signals.

[0005] In the first aspect, an embodiment of the present application provides a fractional frequency divider, comprising: a delay phase-locked loop, for generating multiple clock signals based on an original clock signal; wherein the phases of the clock signals are arranged in order from small to large or from large to small, and the phase differences of adjacent clock signals after arrangement are equal; a first state machine, for generating a first clock selection signal and a second clock selection signal according to a preset frequency division step; a first multi-channel clock signal selector, respectively connected to the delay phase-locked loop and the first state machine, for selecting a first target clock signal and a second target clock signal from each clock signal according to the first clock selection signal and the second clock selection signal; a frequency division module, connected to the output end of the first multi-channel clock signal selector, for generating a fractional frequency divided clock signal according to the first target clock signal and the second target clock signal.

[0006] According to a specific implementation method of an embodiment of the present application, the delay locked loop includes: a delay link, the delay link includes a first buffer and a multi-stage delay unit; the input end of the first buffer is used to input the original clock signal; the output end of the first buffer is connected to the input end of the first-stage delay unit in the multi-stage delay unit, and the output ends of the other delay units in the multi-stage delay unit except the last-stage delay unit are connected to the input end of the next-stage delay unit; a phase detector, the first input end of the phase detector is connected to the output end of the first buffer, and the second input end is connected to the output end of the last-stage delay unit in the multi-stage delay unit; a second state machine, the input end of the second state machine is connected to the output end of the phase detector, and multiple output ends are respectively connected to the delay units of each stage in a one-to-one correspondence, and is used to control the phase of the clock signal output by the delay units of each stage according to the output signal of the phase detector, so that the delay units of adjacent stages in the delay units of each stage output multiple clock signals with equal phase differences.

[0007] According to a specific implementation method of an embodiment of the present application, each level of delay units in each level of delay units includes a second buffer and an adjustable load capacitor; wherein, the output end of the second buffer in each level of delay unit is connected to the adjustable load capacitor of the delay unit at the same level; the output end of the second buffer in each level of delay unit is connected to the input end of the second buffer in the next level of delay unit; the state machine is specifically used to generate multiple configuration signals based on the output signal of the phase detector, so that the delay units at each level adjust their own delay phase values ​​according to their corresponding configuration signals, and based on the delay phases of the delay units at each level, the delay units of adjacent levels in the delay units at each level generate multiple clock signals with equal phase differences.

[0008] According to a specific implementation method of an embodiment of the present application, the first state machine includes a configuration information input interface, which is specifically used to receive configuration information through the configuration information input interface, and generate a first clock selection signal and a second clock selection signal according to the frequency division step in the configuration information.

[0009] According to a specific implementation method of an embodiment of the present application, the clock input end of the first state machine is connected to the output end of the frequency division module, and is specifically used to generate a first clock selection signal and a second clock selection signal based on a preset frequency division step and the frequency division signal output by the frequency division module.

[0010] According to a specific implementation method of an embodiment of the present application, the frequency division module includes a clock signal processing unit and a frequency division unit; the first input end of the clock signal processing unit is connected to the first output end of the first multi-channel clock signal selector, and the first output end is connected to the frequency division unit to transmit the first target clock signal to the frequency division unit; the second input end of the clock signal processing unit is connected to the second output end of the first multi-channel clock signal selector, and the second output end is connected to the frequency division unit to invert the second target clock signal and transmit it to the frequency division unit.

[0011] According to a specific implementation method of an embodiment of the present application, the frequency division unit includes a second multi-channel clock signal selector and a trigger; the first clock signal input end of the second multi-channel clock signal selector is connected to the first output end of the clock signal processing unit, and the second clock signal input end is connected to the second output end of the clock signal processing unit; the selection signal input end of the second multi-channel clock signal selector is connected to the output end of the trigger; the clock signal output end of the second multi-channel clock signal selector is connected to the clock signal input end of the trigger; the output end of the trigger is connected to the input end of the first inverter, and the data input end of the trigger is connected to the output end of the first inverter; the input end of the second inverter is connected to the output end of the first inverter, and the output end is connected to the selection end of the second multi-channel clock signal selector.

[0012] According to a specific implementation of the embodiment of the present application, the output end of the first inverter is connected to the clock signal input end of the first state machine.

[0013] According to a specific implementation method of an embodiment of the present application, the frequency division unit includes a pulse generator and a latch; the first input end of the pulse generator is connected to the first output end of the clock signal processing unit, and the first output end is connected to the set end of the latch; the second input end of the pulse generator is connected to the second output end of the clock signal processing unit, and the second output end is connected to the reset end of the latch; the first output end of the pulse generator is used to output a fractional frequency-divided clock signal.

[0014] According to a specific implementation of the embodiment of the present application, the second output terminal of the latch is connected to the clock signal input terminal of the state machine.

[0015] According to a specific implementation of the embodiment of the present application, the frequency division module further includes: an integer frequency division unit; the integer frequency division unit is connected to the output end of the frequency division unit.

[0016] According to a specific implementation method of an embodiment of the present application, it also includes: a third multi-channel clock signal selector; the first input end of the third multi-channel clock signal selector is connected to the output end of the frequency division module, the second input end is used to input any clock signal generated by the delay locked loop, and the third input end is used to input an enable signal.

[0017] In a second aspect, the present application provides an integrated circuit, comprising a fractional frequency divider, wherein the fractional frequency divider is the fractional frequency divider described in any of the aforementioned implementations.

[0018] The fractional frequency divider and integrated circuit of this embodiment generate multiple clock signals based on the original clock signal. The phase of each clock signal is arranged in order from small to large or from large to small. The phase difference of each adjacent clock signal after arrangement is equal. Then, according to the preset frequency division step, a first clock selection signal and a second clock selection signal are generated. According to the first clock selection signal and the second clock selection signal, a first target clock signal and a second target clock signal are selected from each clock signal. Finally, according to the first target clock signal and the second target clock signal, a fractional frequency divided clock signal is generated. In this way, the generation method of the fractional frequency divided clock signal is enriched. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 It is a structural diagram of a phase-locked loop in the prior art; Figure 2 A schematic structural diagram of a fractional frequency divider provided in one embodiment of the present application; Figure 3 A schematic structural diagram of a delay-locked loop provided in yet another embodiment of the present application; Figure 4 A schematic structural diagram of a fractional frequency divider provided in one embodiment of the present application; Figure 5 1 is a waveform diagram of a clock signal output by a delay-locked loop in one embodiment of the present application; Figure 6 A schematic structural diagram of a fractional frequency divider provided in one embodiment of the present application; Figure 7 The waveform diagram of each signal in the fractional frequency divider in one embodiment of the present application; Figure 81 is a waveform diagram of each signal in a fractional frequency divider in another embodiment of the present application. DETAILED DESCRIPTION

[0021] The embodiments of the present application are described in detail below with reference to the accompanying drawings. It should be understood that the embodiments described are only a portion of the embodiments of the present application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0022] like Figure 1 As shown, the input signal Clk_ref is fed into the M prescaler, where it is divided by M to produce a reference clock signal with a frequency equal to Clk_ref's frequency, Fref / M. This reference clock signal forms one input to the phase detector (PD). The other input to the PD is the feedback signal derived from the output signal Clk_out, which is fed through the divide-by-N counter.

[0023] If the PLL is locked, the frequencies of the two signals are nearly the same. The output of the phase detector is a voltage proportional to the phase difference between the two inputs.

[0024] If the PLL loop starts or there is a large instantaneous change in the input frequency, the phase detector operates, switching the operating frequency of the PLL output signal to the desired frequency. When this frequency is reached, the PD returns to phase detector mode, and its output is proportional to the phase difference between the reference and feedback signals.

[0025] The phase detector drives a charge pump, which is a bipolar switched current source. This means it can output both positive and negative current pulses to the PLL's loop filter. The loop filter removes the phase error signal and also determines the PLL's dynamic characteristics.

[0026] The filtered signal is used to control the voltage-controlled oscillator (VCO), whose output frequency varies with the input control voltage. The VCO output frequency is N times the input frequency of the phase detector input stage feedback signal, which is N / M times the input signal Clk_ref. Therefore, after the PLL is locked, the output frequency of Clk_out is equal to Fref. N / M. Using this method, fractional frequency division of the input signal can be achieved.

[0027] However, existing frequency division methods are limited. To enrich the frequency division methods of clock signals, the inventors discovered during their research that two clock signals with different phases can be provided to a clock signal selector, thereby driving a frequency division module. This causes the high level of the frequency division module's output signal to be delayed by a phase difference compared to the high level of the reference input signal. Similarly, the low level of the frequency division module's output signal is delayed by a phase difference compared to the low level of the reference input signal. Relative to the input signal, both the high and low levels of the output signal are delayed by a phase difference, thereby achieving fractional frequency division of the input signal.

[0028] In order to enable those skilled in the art to better understand the technical concepts, implementation plans and beneficial effects of the embodiments of the present application, specific examples are described in detail below.

[0029] In one embodiment, Figure 2 As shown, the fractional frequency divider includes a delay lock loop (DLL) and a digital frequency generator (DFG). The DLL receives the input clock signal ClkIn and outputs n+1 equally phased clock signals PH[n:0]. Dll_lock is the DLL lock flag. The DFG receives the equally phased clock signals PH[n:0] from the DLL circuit and dynamically adjusts the output frequency based on the frequency division select signal Cfg[i:0]. The En signal enables the entire fractional frequency divider circuit. During power-up, the DFG must first lock the DLL to function properly. That is, after the circuit is started, the DLL automatically tracks the input clock phase. Once tracking is complete, the DLL enters a locked state and generates equally phased clock signals. The clock divider circuit only functions after outputting the Dll_lock signal.

[0030] It is understandable that, in a specific implementation, the digital frequency generator 2 may further include a first state machine 20 , a first multi-channel clock signal selector 22 and a frequency division module 24 .

[0031] like Figure 3 and 4 As shown, the fractional divider of this embodiment may include: a delay locked loop 1, a first state machine 20, a first multi-channel clock signal selector 22 and a frequency division module 24; the first multi-channel clock signal selector 22 is connected to the delay locked loop and the first state machine 20 respectively; the output end of the first multi-channel clock signal selector 22 is connected to the frequency division module 24.

[0032] The delay-locked loop is used to generate multiple clock signals based on the original clock signal; wherein the phases of the clock signals are arranged in order from small to large or from large to small, and the phase differences of the adjacent clock signals after arrangement are equal; the first state machine 20 is used to generate a first clock selection signal and a second clock selection signal according to a preset division step; the first multi-channel clock signal selector 22 is used to select a first target clock signal and a second target clock signal from each clock signal according to the first clock selection signal and the second clock selection signal; the frequency division module 24 is used to generate a fractional-frequency divided clock signal according to the first target clock signal and the second target clock signal.

[0033] The original clock signal includes a period and a phase. The delay-locked loop 1 can generate multiple clock signals based on the original clock signal. The multiple clock signals can have equal periods but different phases. After the clock signals are arranged in order of phase from smallest to largest or from largest to smallest, the phase differences between adjacent clock signals are equal.

[0034] The frequency division step can be determined according to the frequency of the divided clock signal.

[0035] The first clock selection signal and the second clock selection signal generated according to the preset frequency division step are used to select two clock signals capable of generating a fractional frequency-divided clock signal from a plurality of clock signals.

[0036] The fractional frequency divider of this embodiment can divide the frequency of the original clock signal to obtain a fractional frequency divided clock signal.

[0037] In this embodiment, multiple clock signals are generated based on the original clock signal, and the phases of the clock signals are arranged in order from small to large or from large to small. The phase differences of the adjacent clock signals after arrangement are equal. Then, according to a preset frequency division step, a first clock selection signal and a second clock selection signal are generated. According to the first clock selection signal and the second clock selection signal, a first target clock signal and a second target clock signal are selected from the clock signals. Finally, according to the first target clock signal and the second target clock signal, a fractional frequency-divided clock signal is generated. In this way, the generation method of the fractional frequency-divided clock signal is enriched, and the problem of a relatively single frequency division method caused by achieving frequency division only by setting a frequency division value in the prior art is avoided.

[0038] For some examples, see Figure 3The delay locked loop 1 may include: a delay link 10, a phase detector 12 and a second state machine 14; wherein the delay link 10 includes a first buffer 10a and a multi-stage delay unit 10b; the input end of the first buffer 10a is used to input the original clock signal; the output end of the first buffer 10a is connected to the input end of the first stage delay unit 10b in the multi-stage delay unit 10b, and the output ends of the other delay units 10b in the multi-stage delay unit 10b except the last stage delay unit 10b are connected to the input end of the next stage delay unit 10b; the phase detector 12 and the second state machine 14 A first input end of the phase detector 12 is connected to the output end of the first buffer 10a, and a second input end is connected to the output end of the delay unit 10b of the last stage in the multi-stage delay unit 10b. An input end of the second state machine 14 is connected to the output end of the phase detector 12, and multiple output ends are connected one-to-one with the delay units 10b of each stage, respectively. The second state machine 14 is configured to control the phase of the clock signal output by each stage of the delay unit 10b according to the output signal of the phase detector 12, so that the delay units 10b of adjacent stages in the delay units 10b output multiple clock signals with equal phase differences.

[0039] The first buffer 10 a can enhance the input original clock signal, and the output signal of the first buffer 10 a is more stable.

[0040] like Figure 3 In the embodiment shown, the original clock signal ClkIn passes through the first buffer 10 a to obtain the clock signal PH[0], which can be used as a reference clock signal for the entire delay chain 10 .

[0041] like Figure 3 In the embodiment shown, the delay unit 10b has n stages, the input end of the first stage is connected to the output end of the first buffer, and the output end is connected to the input end of the second stage; the output end of the second stage is connected to the input end of the third stage, and so on, until the output end of the (n-1)th stage is connected to the input end of the nth stage.

[0042] Driven by the PH[0] signal, the first-stage delay unit 10b generates PH[1]. PH[1] and PH[0] have the same frequency, but differ in phase by one delay unit 10b. The PH[1] signal drives the second-stage delay unit 10b to generate PH[2]. PH[2] and PH[1] differ in phase by one delay unit 10b, and so on, continuously generating PH[3], ..., PH[n-1], and PH[n] clock signals. All PH[n:0] signals have the same frequency, and the phases of the clock signals generated by adjacent delay units 10b differ by one delay unit 10b.

[0043] The two input terminals of the phase detector 12 are respectively connected to the output terminal of the first buffer 10 a and the output terminal of the delay unit 10 b of the last stage in the multi-stage delay unit. The phase detector 12 is used to monitor the phase difference between the reference clock signal PH[0] and the clock signal PH[n] output by the n-th stage delay unit 10 b, and send the difference to the second state machine 14 (DLL FSM).

[0044] In some examples, the phase detector 12 can be implemented using a flip-flop (DFF), PH[0] is used as a sampling clock and connected to the clock port of the flip-flop, and PH[n] is used as a sampling signal and connected to the data port of the flip-flop, so that PH[0] is used to sample the value of PH[n] and then send it to the second state machine 14.

[0045] In some examples, second state machine 14 is the state controller of delay-locked loop 1. It receives sampling signals from phase detector 12 and dynamically adjusts configuration codes D1, D2, ..., Dn of delay cell 10b based on the sampled values. Initially, all configuration codes are equal to 0. The configuration code values ​​are then continuously incremented, increasing the delay of delay cell 10b. The configuration code values ​​are then dynamically adjusted based on the sampled values ​​to ultimately generate the clock signal output by delay cell 10b.

[0046] like Figure 3 The delay phase-locked loop 1 shown in FIG. 1 , the corresponding waveform is as follows Figure 5 As shown, adjacent delay units 10b in each level of delay unit 10b output multiple clock signals with equal phase differences. Tcyc represents the clock period of the original clock signal. When the delay phase-locked loop 1 is locked, the phase difference between PH[n:1] and PH[0] is shown in Table 1. PH[0] is used as the reference clock signal. The phase difference between PH[n] and PH[0] is exactly one clock period. The phase difference between PH[1] and PH[0] is 1 / n clock period. The phase difference between PH[2] and PH[0] is 2 / n clock period. The phase difference between PH[n / 2] and PH[0] is 1 / 2 clock period. The phase difference between PH[n-1] and PH[0] is (1-1 / n) clock period.

[0047]

[0048] When the delay locked loop 1 is locked, a flag signal DLL_lock is generated, indicating that the delay locked loop 1 is in a locked state, the PH[n:0] clock signal has been generated, and the divided clock signal can be generated.

[0049] In order to flexibly adjust the delay phase of the delay unit 10b, in some examples, each level of delay unit 10b in each level of delay unit 10b includes a second buffer and an adjustable load capacitor; wherein the output end of the second buffer in each level of delay unit 10b is connected to the adjustable load capacitor of the delay unit 10b at the same level; the output end of the second buffer in each level of delay unit 10b is connected to the input end of the second buffer in the next level of delay unit 10b; the state machine is specifically used to generate multiple configuration signals based on the output signal of the phase detector 12, so that the delay units 10b at each level adjust their own delay phase values ​​according to their corresponding configuration signals, and based on the delay phases of the delay units 10b at each level, the delay units 10b at adjacent levels in the delay units 10b at each level generate multiple clock signals with equal phase differences.

[0050] See also Figure 3 The adjustable load capacitor C in each delay unit 10b receives configuration codes D1 to Dn generated by the second state machine 14. Each configuration code represents a set of bus signals. Taking the first-stage delay unit 10b as an example, when configuration code D1 is 0, the second buffer in the delay unit 10b does not drive the load capacitor, and the delay of the delay unit 10b is minimal. As the value of D1 increases, the value of the load capacitor C1 increases synchronously, and the delay value of the second buffer also increases synchronously. Thus, by adjusting the value of D1, the delay value of the delay unit 10b can be adjusted, thereby enabling each delay unit 10b to generate multiple clock signals with equal phase differences.

[0051] In practical applications, it is necessary to flexibly adjust the operating frequency of the clock signal. Figure 1 In the prior art, when the operating frequency of the output signal Clk_out needs to be changed, the frequency division value of the frequency divider M or N needs to be modified. In this case, the phase-locked loop (PLL) transitions from a locked state to an unlocked state. The entire PLL takes some time to stabilize and return to a locked state, allowing the voltage-controlled oscillator (VCO) to output a clock signal at a specific frequency. If the output clock frequency needs to be frequently switched during chip operation, the phase-locked loop (PLL) must switch back from an unlocked state to a locked state each time, which takes a long time. In some examples, the first state machine 20 may include a configuration information input interface, specifically for receiving configuration information via the configuration information input interface and generating the first clock selection signal and the second clock selection signal based on the frequency division step size in the configuration information.

[0052] like Figure 4In the embodiment shown, the configuration information Cfg[i:0] is input into the first state machine 20 through the configuration information input interface of the first state machine 20. The first state machine 20 generates a first clock selection signal and a second clock selection signal according to the frequency division step in the configuration information Cfg[i:0].

[0053] The frequency division step size can be determined according to the actual required clock frequency output by the fractional divider.

[0054] A specific frequency division step can generate a specific selection signal, thereby selecting a specific target clock signal, and further outputting a clock signal of a specific frequency, thereby achieving fractional frequency division of the original clock signal.

[0055] Different frequency division steps can generate different selection signals. Furthermore, different target clock signals can be selected according to different selection signals. In actual usage scenarios, the clock signal output by the fractional divider can be switched from one frequency to another. In this embodiment, configuration information is received through the configuration information input interface. According to the frequency division step in the configuration information, two selection signals can be generated, and then two target clock signals are further determined based on the two selection signals. Finally, a fractional frequency division clock signal can be generated according to the two target clock signals. In this way, frequency switching can be achieved quickly.

[0056] When the first state machine 20 generates the first clock selection signal and the second clock selection signal, the clock input end of the first state machine 20 needs to input the clock signal. The input clock signal can be generated by another module. This will cause the module of the fractional divider to be more complicated. In order to make the structure of the fractional divider simpler, in one example, the clock input end of the first state machine 20 is connected to the output end of the frequency division module 24, which is specifically used to generate the first clock selection signal and the second clock selection signal according to the preset frequency division step and the frequency division signal output by the frequency division module 24.

[0057] The clock input terminal of the first state machine 20 can be set to trigger the operation of the first state machine 20 on a falling edge, or can be set to trigger the operation of the first state machine 20 on a rising edge.

[0058] In some examples, the first state machine 20 is designed to operate as a falling edge triggered signal. When the output end of the frequency division module 24 outputs a low level, the clock input end of the first state machine 20 receives the low level and triggers the generation of a first clock selection signal and a second clock selection signal. Furthermore, the first target clock signal and the second target clock signal are selected according to the first clock selection signal and the second clock selection signal. According to the first target clock signal and the second target clock signal, the frequency division module 24 can generate a cycle of a fractional-frequency clock signal; when the output fractional-frequency clock signal is a high level, the first state machine 20 is not triggered. When the fractional-frequency clock signal is a low level, the first state machine 20 is triggered to produce a new first clock selection signal and a new second clock selection signal. Furthermore, according to the new first clock selection signal and the new second clock selection signal, a new first target clock signal and a new second target clock signal are selected, and then the fractional-frequency clock signal of the next cycle is further generated. And so on, a stable fractional-frequency clock signal is generated.

[0059] In some examples, the frequency division module 24 includes a clock signal processing unit 240 and a frequency division unit 242; the first input end of the clock signal processing unit 240 is connected to the first output end of the first multi-channel clock signal selector 22, and the first output end is connected to the frequency division unit 242 to transmit the first target clock signal to the frequency division unit 242; the second input end of the clock signal processing unit 240 is connected to the second output end of the first multi-channel clock signal selector 22, and the second output end is connected to the frequency division unit 242 to invert the second target clock signal and transmit it to the frequency division unit 242.

[0060] like Figure 4 The clock signal processing unit 240 shown may include a first branch 240 a and a second branch 240 b .

[0061] Among them, the first branch 240a includes a third buffer and a transmission gate, the input end of the third buffer is connected to the first output end of the first multi-channel clock signal selector 22, the output end of the third buffer is connected to the input end of the transmission gate, and the output end of the transmission gate is connected to the frequency division unit 242. In this way, the first target clock signal output from the first output end of the first multi-channel clock signal selector 22 can be transmitted to the frequency division unit 242.

[0062] The second branch 240b includes a fourth buffer and an inverter. The input end of the fourth buffer is connected to the second output end of the first multi-channel clock signal selector 22, the output end of the fourth buffer is connected to the input end of the inverter, and the output end of the inverter is connected to the frequency division unit 242. In this way, the second target clock signal output from the second output end of the second multi-channel clock signal selector can be inverted and then transmitted to the frequency division unit 242.

[0063] The frequency dividing unit 242 may generate a fractional frequency-divided clock signal according to the first target clock signal and the inverted second target clock signal.

[0064] The structure of the frequency dividing unit 242 can be arbitrary, as long as it can generate a fractional frequency-divided clock signal based on the first target clock signal and the inverted second target clock signal. In order to make the structure of the frequency dividing unit 242 simpler, in some examples, the frequency dividing unit 242 includes a second multi-channel clock signal selector 242a and a trigger 242b; the first clock signal input end of the second multi-channel clock signal selector 242a is connected to the first output end of the clock signal processing unit 240, and the second clock signal input end is connected to the second output end of the clock signal processing unit 240; The selection signal input end of the second multi-channel clock signal selector 242a is connected to the output end of the trigger 242b; the clock signal output end of the second multi-channel clock signal selector 242a is connected to the clock signal input end of the trigger 242b; the output end of the trigger 242b is connected to the input end of the first inverter 242c, and the data input end of the trigger 242b is connected to the output end of the first inverter 242c; the input end of the second inverter 242d is connected to the output end of the first inverter 242c, and the output end is connected to the selection end of the second multi-channel clock signal selector 242a.

[0065] When the output end of the trigger 242b outputs a high level, the data input end of the trigger 242b inputs a low level, and the selection end input of the second multi-channel clock signal selector 242a is also a high level. The selection end of the second multi-channel clock signal selector 242a is a high level, which can transmit the inverted signal of PH[1] input at the second clock signal input end of the second multi-channel clock signal selector 242a to the clock signal input end of the trigger 242b. After a specific clock cycle delay, the rising edge of PH[1] arrives, triggering the trigger 242b to flip, and transmitting the low level of the data input end of the trigger 242b to the output end, so that the signal output from the output end of the trigger 242b is inverted from a high level to a low level.

[0066] The output end of the trigger 242b outputs a low level and then passes through the first inverter 242c, setting the data input end of the trigger 242b to a high level, and setting the data selection end of the second multi-channel clock signal selector 242a to a low level. This low level sends PH[2] input from the first clock signal input end of the second multi-channel clock signal selector 242a to the clock signal input end of the trigger 242b. After a specific clock cycle delay, the rising edge of PH[2] arrives, triggering the flip-flop 242b to flip, and transmitting the high level of the data input end of the trigger 242b to the output end. As a result, the signal output from the output end of the trigger 242b is inverted from a low level to a high level.

[0067] In some examples, the output terminal of the first inverter 242 c is connected to the clock signal input terminal of the first state machine 20 .

[0068] The first state machine 20 can be set to falling edge trigger, that is, when the falling edge of the signal input to the clock signal input end of the first state machine 20 occurs, the first clock selection signal and the second clock selection signal are determined, and when the next falling edge occurs, the new first clock selection signal and the new second clock selection signal are determined.

[0069] As an alternative embodiment of the specific structure of the frequency dividing unit 242, see Figure 6 The frequency dividing unit 242 may include a pulse generator 242e and a latch 242f; the first input end of the pulse generator 242e is connected to the first output end of the clock signal processing unit 240, and the first output end is connected to the set end of the latch 242f; the second input end of the pulse generator 242e is connected to the second output end of the clock signal processing unit 240, and the second output end is connected to the reset end of the latch 242f.

[0070] The first target clock signal inputted to the first output terminal of the clock signal processing unit 240 can drive the pulse generator 242e to generate a set pulse signal. The first target clock signal can drive the pulse generator 242e to generate a reset pulse signal.

[0071] The set pulse signal is at a high level, so that the first output end of the latch 242f is at a high level. After a specific delay, the reset pulse signal is at a high level, so that the first output end of the latch 242f is reversed from a high level to a low level. When the set pulse signal is at a high level, the first output end of the latch 242f outputs a fractional frequency division signal.

[0072] In some examples, the second output terminal of the latch 242f is connected to the clock signal input terminal of the state machine, so that the signal output from the second output terminal of the latch 242f can be provided to the clock signal input terminal of the first state machine 20 to generate a first clock selection signal and a second clock selection signal.

[0073] In actual applications, there may be situations where the numerical requirements for the division ratio of the fractional divider are high. In order to adapt to such application scenarios, in some embodiments, the division module 24 also includes: an integer division unit 244242; the integer division unit 244242 is connected to the output end of the division unit 242.

[0074] The signal output by the frequency dividing unit 242 is further divided by the integer frequency dividing unit 244242, thereby increasing the frequency dividing ratio.

[0075] See also Figure 4 and Figure 6In order to flexibly control the output of the fractional divider, in some examples, it can also include: a third multi-channel clock signal selector 3; the first input end of the third multi-channel clock signal selector 3 is connected to the output end of the frequency division module 24, the second input end is used to input any clock signal generated by the delay locked loop 1, and the third input end is used to input an enable signal.

[0076] The output end of the third multi-channel clock signal selector 3 is used to output a fractional frequency clock signal.

[0077] like Figure 4 and Figure 6 In the embodiment shown, PH[0] is input to the second input end of the third multi-channel clock signal selector 3. When the enable signal of the third multi-channel clock signal selector 3 is 0, PH[0] is sent to the output end of the third multi-channel clock signal selector 3, that is, PH[0] is the output of the fractional-frequency clock signal of this embodiment, and the frequency of the output clock signal cannot be adjusted; when the enable signal is 1, the output signal of the frequency division module 24 is sent to the output end of the third multi-channel clock signal selector 3, that is, the output signal of the frequency division module 24 is used as the output of the fractional frequency divider in this embodiment. If the output frequency needs to be adjusted, the frequency division ratio can be input through the configuration information input interface of the first state machine 20 to realize the conversion of the fractional-frequency clock signal from one frequency to another.

[0078] The fractional frequency divider in the above embodiment is a digital circuit with a small area, thus avoiding the problem of a large circuit area caused by analog circuit design in the prior art.

[0079] The following two specific embodiments describe in detail the generation scheme of the fractional frequency division clock signal of the present application. Example 1

[0080] See also Figure 4 In this embodiment, the first multi-channel clock signal selector 22 receives the PH[n:0] clock signal from the delay-locked loop 1. The two selection signals of the first multi-channel clock signal selector 22 are the input signals RSEL[a:0] and FSEL[b:0]. RSEL[a:0] and FSEL[b:0] originate from the first state machine 20. By configuring the input signal Cfg[i:0], the first state machine 20 can generate a specific sequence of RSEL[a:0] and FSEL[b:0], selecting two sets of clock signals from PH[n:0].

[0081] Configure the values ​​of RSEL[a:0] and FSEL[b:0] to transmit the two specific clock signals in PH[n:0] to the two ports of the second multi-channel clock signal selector 242a. Clk0 represents the first target clock signal output from the first output port of the second multi-channel clock signal selector 242a after passing through a first-level buffer and a transmission gate. Clk1 represents the second target clock signal output from the second output port of the second multi-channel clock signal selector 242a after passing through a first-level buffer and an inverter. The output clock signal Clki of the second multi-channel clock signal selector 242a is transmitted to the clock port CK of the flip-flop 242b (DFF). The input signal En is an asynchronous reset signal for the flip-flop 242b and the first state machine 20. When En is 0, the flip-flop 242b and the first state machine 20 are reset. When En is 1, the flip-flop 242b and the first state machine 20 operate normally. The output clock signal of the flip-flop 242b is Gclk.

[0082] The En signal is also used as the clock signal PH[0] and the output signal Gclk of the frequency divider at the two input terminals of the third multi-channel clock signal selector 3. When En is equal to 0, PH[0] is sent to the output port ClkOut of the third multi-channel clock signal selector 3, and the output signal frequency cannot be adjusted; when En is equal to 1, the Gclk signal is sent to the ClkOut port.

[0083] The output signal Gclk of flip-flop 242b passes through first inverter 242c and is connected to data port Din of flip-flop 242b. Din then drives second inverter 242d to generate signal S, which is connected to the select port of second multi-channel clock signal selector 242a. When S is 0, Clk0 is transmitted to the output port of second multi-channel clock signal selector 242a. When S is 1, Clk1 is transmitted to the output port of second multi-channel clock signal selector 242a.

[0084] Taking the frequency division step size f=2 as an example, the process of generating a fractional frequency divided clock signal is explained.

[0085] Set the frequency division step size to f=2, such as Figure 4 The embodiment shown generates a fractional frequency signal 1+2 / N (N represents the number of stages of the DLL delay chain). The waveform is shown in FIG. Figure 7 shown.

[0086] When En is equal to 0, the first state machine 20 is asynchronously cleared and reset, RSEL[a:0] and FSEL[b:0] output a fixed value of 0, and the two clock signals output by the first multi-channel clock signal selector 22 are both PH[0]. After passing through a first-level buffer and a first-level transmission gate, Clk0 equals PH[0]. Similarly, after passing through a first-level buffer and a first-level inverter, Clk1 equals the inverse of PH[0].

[0087] Flip-flop 242b is in a reset state. Its output signal Gcl0k remains low, and the output signal Din of the first inverter 242c is set to 1. Din then passes through the second inverter 242d, setting the signal S to 0. The low level of S sends Clk0 (PH[0]) to the clock input of flip-flop 242b. Flip-flop 242b is in a reset state and cannot generate a frequency-divided signal.

[0088] When a high level is applied to the En port, flip-flop 242b operates normally. At this point, Din is equal to 0, and the clock signal Clki input to the clock input of flip-flop 242b is equal to PH[0]. The rising edge of PH[0] triggers flip-flop 242b, transmitting Din to the Q port of flip-flop 242b. The Gclk signal flips from a low level to a high level, passing through the first inverter 242c, setting Din to 0. Din is then connected to the clock input port CK of the first state machine 20, which is designed to be falling-edge triggered.

[0089] When the CK terminal of the first state machine 20 falls, the first state machine 20 starts working, setting FSEL[b:0] to 1 and RSEL[a:0] to 2. FSEL[b:0] equals 1, driving the first multi-channel clock signal selector 22, which transmits PH[1] through the inverter to the second port of the second multi-channel clock signal selector 242a. Clk1 equals PH[1] inverted. RSEL[a:0] equals 2, driving the first multi-channel clock signal selector 22, which transmits PH[2] through the buffer to the first port of the second multi-channel clock signal selector 242a. Clk0 equals PH[2].

[0090] The falling edge of Din passes through the second inverter 242d, driving the selection end signal S of the second multi-channel clock signal selector 242a to invert from a low level to a high level. The high level of S transmits Clk1 (PH[1] inverted) to the output end to obtain the output signal Clki. After a delay of (0.5+1 / N) After the Tcyc clock cycle, the rising edge of Clki (the falling edge of PH[1]) triggers the flip-flop 242b to flip, transmitting Din = 0 to the Q port, and the Gclk signal is reversed from high level to low level. The duration of Gclk high level is equal to (0.5+1 / N) Tcyc clock cycle.

[0091] After the high level of Gclk passes through the first inverter 242c, Din is set to 1. Din passes through the second inverter 242d, and S is set to 0. The low level of S sends Clk0 (PH[2]) to the clock input port CK of the flip-flop 242b, and then delays (0.5+1 / N) After the Tcyc clock cycle, the rising edge of Clki (the rising edge of PH[2]) triggers the flip-flop 242b to flip, transmitting Din = 1 to the Q port, and the Gclk signal is reversed from low level to high level. The duration of Gclk low level is equal to (0.5+1 / N) Tcyc clock cycle.

[0092] With this operation, both the high and low clock periods of Gclk are equal to (0.5 + 1 / N) Tcyc, Gclk period equals (1+2 / N) Tcyc implements the (1+2 / N) fractional division of ClkIn.

[0093] After the high level of Gclk passes through the first inverter 242c, Din is set to 0. The clock input terminal CK of the first state machine 20 receives a falling edge, and the first state machine 20 sets FSEL[b:0] to 3 and RSEL[a:0] to 4. FSEL[b:0] = 3 drives the first multi-channel clock signal selector 22 to transmit PH[3] through the inverter and then to the second output terminal of the second multi-channel clock signal selector 242a. Clk1 is equal to the inverse of PH[3]. RSEL[a:0] = 4 drives the first multi-channel clock signal selector 22 to transmit PH[4] through the buffer and then to the first output terminal of the second multi-channel clock signal selector 242a. Clk0 is equal to PH[4].

[0094] The first state machine 20 continuously changes the values ​​of RSEL[a:0] and FSEL[b:0], so that RSEL[a:0] is at the rising edge of Gclk: RSEL[a:0] = 0, 2, 4, 6,…, N, 2, 4 CLK0 = PH[0], PH[2], PH[4], PH[6],…, PH[N], PH[2] Make FSEL[b:0] at the rising edge of Gclk: FSEL[b:0] = 0, 1, 3, 5,…, N-1, 1, 3, 5 CLK1 = PH[0], PH[1], PH[3], PH[5], PH[7],…, PH[N-1], PH[1] negation Among them, RSEL[a:0] =0, FSEL[b:0]=0 is the initial state, and the state machine continuously changes the values ​​of RSEL[a:0] and FSEL[b:0].

[0095] Then, Din is used to drive the S port of the second multi-channel clock signal selector 242a, and Clk0 or Clk1 is transmitted to the output end in turn. When the output signal Clki rises, Din = 0 or 1 is transmitted to the Q port, and a fractional frequency signal of the input clock ClkIn can be generated.

[0096] PH[1] is delayed by 1 / N clock cycle relative to PH[0], and Gclk high level maintains (0.5+1 / N) clock cycle. PH[2] is delayed by 1 / N clock cycle relative to PH[1], and Gclk low level maintains (0.5+1 / N) clock cycle. In this way, the clock period of Gclk is equal to (1+2 / N) Tcyc clock cycle.

[0097] If it is necessary to switch to another divided clock signal, the delay step f is changed by configuring the Cfg[i:0] signal, and the first state machine 20 is used to continuously change the values ​​of RSEL[a:0] and FSEL[b:0] so that RSEL[a:0] is at the rising edge of Gclk: RSEL[a:0] = 0, f, 2f, 3f,…, f, 2f CLK0 = PH[0], PH[f], PH[2f], PH[3f],…, PH[f] Make FSEL[b:0] at the rising edge of Gclk: FSEL[b:0] = 0, f / 2, 3f / 2, 5f / 2,…, f / 2, 3f / 2 CLK1 = PH[0], PH[f / 2], PH[3f / 2], PH[5f / 2],…, PH[f / 2] negation Through the above process, a (1+f / N) fractional frequency divided clock signal may be generated at the output port of the flip-flop 242 b , and the duty cycle of the signal is equal to 50%.

[0098] When f=2, we can achieve Figure 7 The 1+2 / N fractional frequency signal shown in . When f=2 / N, a 1.5 frequency division signal can be achieved. By changing the delay step f, a very fine fractional frequency division signal can be generated.

[0099] When f is an even number, the duty cycle of the generated frequency-dividing signal is 50%. When f is an odd number, the fractional frequency-dividing function can also be realized, but the duty cycle of the generated clock signal is not equal to 50%.

[0100] Table 2 shows the adjustable division ratio range and division adjustment step size for different numbers of delay stages, N, where N represents the number of delay unit 10b stages in the DLL. Theoretically, when N equals 10, the minimum division ratio is 1.2, the maximum division ratio is 1.8, and the division adjustment step size is 0.2. When N equals 20, the minimum division ratio is 1.1, the maximum division ratio is 1.9, and the division adjustment step size is 0.1. When N equals 40, the minimum division ratio is 1.05, the maximum division ratio is 1.95, and the division adjustment step size is 0.05. A larger N value increases the finer the adjustment step size for fractional frequency signals, and the wider the signal adjustment range.

[0101]

[0102] As can be seen from Table 2, the frequency division ratio of the fractional divider will not exceed 2. If a frequency division ratio greater than 2 is to be achieved, an integer frequency division circuit can be loaded after the trigger 242b, and the frequency division ratio is M. In this way, a frequency division coefficient greater than 2 can be achieved, and the frequency division ratio of the entire circuit is equal to M. (1+f / N). This method can realize the fractional frequency division function of any format.

[0103] By changing the value of Cfg[i:0], you can quickly switch from one division ratio signal to another based on actual application requirements. The fractional divider can generate a clock signal with a division ratio precisely equal to the set value, and the adjustment range is very wide. The larger the number of levels N, the smaller the adjustment step size and the finer the adjustment range.

[0104] Example 2: See also Figure 6 The waveform of the 1+2 / N fractional frequency division signal generated in this embodiment is as follows: Figure 8 shown.

[0105] By configuring the Cfg[i:0] signal, a clock selection signal is generated, and PH[0] and PH[1] are determined as two target clock signals. After the clock processing unit, signals Clk0 and Clk1 are obtained. Clk0 is equal to PH[0], and Clk1 is equal to the inverse of PH[1]. The phase difference between PH[1] and PH[0] is 1 / N clock cycles.

[0106] The first state machine 20 continuously changes the values ​​of RSEL[a:0] and FSEL[b:0], so that RSEL[a:0] is at the rising edge of Gclk: RSEL[a:0] = 0, 2, 4, 6,…, N, 2, 4 CLK0 = PH[0], PH[2], PH[4], PH[6],…, PH[N], PH[2] Make FSEL[b:0] on the rising edge of Gclk: FSEL[b:0] = 0, 1, 3, 5,…, N-1, 1, 3, 5 CLK1 = PH[0], PH[1], PH[3], PH[5], PH[7],…, PH[N-1], PH[1] negation When the En signal is equal to 0, Gclk remains at a low level. After the En signal is enabled, Clk0 drives the pulse generator (PG) to generate a set pulse signal, and Clk1 drives the pulse generator to generate a reset pulse signal.

[0107] The high level of the Set signal causes Gclk to flip to a high level. After a delay of (0.5+1 / N) clock cycles, the high level of the Reset signal causes Gclk to flip to a low level. The high level of Gclk lasts for (0.5+1 / N) clock cycles. After another delay of (0.5+1 / N) clock cycles, the high level of the Set signal causes Gclk to flip to a high level. The low level of Gclk lasts for (0.5+1 / N) clock cycles. And so on. In this way, a (1+2 / N) fractional frequency clock signal can be generated.

[0108] The present application also provides an integrated circuit, which includes a fractional frequency divider, wherein the fractional frequency divider is the fractional frequency divider in any of the aforementioned embodiments.

[0109] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply the existence of any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or device comprising the element.

[0110] Each embodiment in this specification is described in a related manner. The same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments.

[0111] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present application should be included in the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A fractional frequency divider, characterized in that: include: A delay-locked loop (DLL) is configured to generate multiple clock signals based on an original clock signal, wherein the phases of the clock signals are arranged in ascending order or descending order, and the phase differences of adjacent clock signals after the arrangement are equal; A first state machine is configured to generate a first clock selection signal and a second clock selection signal according to a preset frequency division step size; a first multi-channel clock signal selector, connected to the delay locked loop and the first state machine respectively, for selecting a first target clock signal and a second target clock signal from each clock signal according to the first clock selection signal and the second clock selection signal; The frequency division module is connected to the output end of the first multi-channel clock signal selector, and is used to generate a fractional frequency division clock signal according to the first target clock signal and the second target clock signal.

2. The fractional frequency divider according to claim 1, wherein: The delay locked loop comprises: A delay chain, the delay chain comprising a first buffer and a multi-stage delay unit; an input end of the first buffer is used to input an original clock signal; an output end of the first buffer is connected to an input end of a first-stage delay unit in the multi-stage delay unit, and output ends of all delay units in the multi-stage delay unit except the last-stage delay unit are connected to an input end of a next-stage delay unit; a phase detector, wherein a first input terminal of the phase detector is connected to the output terminal of the first buffer, and a second input terminal of the phase detector is connected to the output terminal of the delay unit of the last stage in the multi-stage delay unit; A second state machine, wherein the input end of the second state machine is connected to the output end of the phase detector, and multiple output ends are respectively connected to the delay units of each stage in a one-to-one correspondence, and is used to control the phase of the clock signal output by the delay units of each stage according to the output signal of the phase detector, so that the delay units of adjacent levels in each stage of the delay units output multiple clock signals with equal phase differences.

3. The fractional frequency divider according to claim 2, wherein: Each delay unit in each level of delay units includes a second buffer and an adjustable load capacitor; Wherein, the output end of the second buffer in each level of delay unit is connected to the adjustable load capacitor of the delay unit at the same level; The output end of the second buffer in each stage of the delay unit is connected to the input end of the second buffer in the next stage of the delay unit; The state machine is specifically configured to generate a plurality of configuration signals based on the output signal of the phase detector, so that each delay unit adjusts its own delay phase value according to its corresponding configuration signal, and based on the delay phase of each delay unit, adjacent delay units in each delay unit generate a plurality of clock signals with equal phase differences.

4. The fractional frequency divider according to claim 1, wherein: The first state machine includes a configuration information input interface, specifically configured to receive configuration information through the configuration information input interface, and generate a first clock selection signal and a second clock selection signal according to a frequency division step in the configuration information.

5. The fractional frequency divider according to claim 4, wherein: The clock input terminal of the first state machine is connected to the output terminal of the frequency division module, and is specifically used to generate a first clock selection signal and a second clock selection signal according to a preset frequency division step and the frequency division signal output by the frequency division module.

6. The fractional frequency divider according to claim 1, wherein: The frequency division module includes a clock signal processing unit and a frequency division unit; The first input terminal of the clock signal processing unit is connected to the first output terminal of the first multi-channel clock signal selector, and the first output terminal is connected to the frequency dividing unit to transmit the first target clock signal to the frequency dividing unit; The second input end of the clock signal processing unit is connected to the second output end of the first multi-channel clock signal selector, and the second output end is connected to the frequency dividing unit to invert the second target clock signal and transmit it to the frequency dividing unit.

7. The fractional frequency divider according to claim 6, wherein: The frequency division unit includes a second multi-channel clock signal selector and a trigger; The first clock signal input terminal of the second multi-channel clock signal selector is connected to the first output terminal of the clock signal processing unit, and the second clock signal input terminal is connected to the second output terminal of the clock signal processing unit; The selection signal input terminal of the second multi-channel clock signal selector is connected to the output terminal of the trigger; the clock signal output terminal of the second multi-channel clock signal selector is connected to the clock signal input terminal of the trigger; The output terminal of the trigger is connected to the input terminal of the first inverter, and the data input terminal of the trigger is connected to the output terminal of the first inverter; The input end of the second inverter is connected to the output end of the first inverter, and the output end of the second inverter is connected to the selection end of the second multi-channel clock signal selector.

8. The fractional frequency divider according to claim 7, wherein: An output terminal of the first inverter is connected to a clock signal input terminal of the first state machine.

9. The fractional frequency divider according to claim 6, wherein: The frequency division unit includes a pulse generator and a latch; The first input terminal of the pulse generator is connected to the first output terminal of the clock signal processing unit, and the first output terminal is connected to the set terminal of the latch; The second input terminal of the pulse generator is connected to the second output terminal of the clock signal processing unit, and the second output terminal is connected to the reset terminal of the latch; The first output terminal of the pulse generator is used to output a fractional frequency clock signal.

10. The fractional frequency divider according to claim 9, wherein: The second output terminal of the latch is connected to the clock signal input terminal of the state machine.

11. The fractional frequency divider according to claim 6, wherein: The frequency division module further includes: an integer frequency division unit; The integer frequency division unit is connected to the output end of the frequency division unit.

12. The fractional frequency divider according to claim 1, wherein: Also includes: A third multi-channel clock signal selector; The first input end of the third multi-channel clock signal selector is connected to the output end of the frequency division module, the second input end is used to input any clock signal generated by the delay locked loop, and the third input end is used to input an enable signal.

13. An integrated circuit, characterized in that: The integrated circuit comprises a fractional frequency divider, wherein the fractional frequency divider is the fractional frequency divider according to any one of claims 1 to 12.

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