Integrated circuit system and control method of memory controller in integrated circuit system

Abstract

A memory controller in an integrated circuit system performs bidirectional data transfer between the memory controller and a memory module at a clock frequency. The data transmission in the first direction adopts a first pulse amplitude modulation level, and the data transmission in the second direction adopts a second pulse amplitude modulation level. When an indication of an increase in the first direction data transfer demand is received, the memory controller raises the first pulse amplitude modulation level to a target pulse amplitude modulation level for the first direction data transfer while maintaining the clock frequency and the second pulse amplitude modulation level unchanged in the second direction. According to the invention, under the condition that the clock frequency and the second pulse amplitude modulation level are kept unchanged, the data transmission rate in the first direction is increased by improving the first pulse amplitude modulation level; therefore, the negative effect of increasing the re-locking time required by the phase-locked loop or the delay-locked loop due to the change of the clock frequency can be avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to integrated circuit systems and control methods for memory controllers in integrated circuit systems. Background Technology

[0002] Modern memory controllers support efficient, low-latency data transfer between processors and memory devices. The memory controller translates and coordinates high-level memory access requests from the processor into low-level electrical signals for reading or writing to memory. Based on the memory access request, the memory controller determines which row and column of the memory cell array to access.

[0003] The memory controller also schedules memory I / O commands from the processor according to timing rules, such as read, write, start (row access), precharge (row close), and refresh memory. Furthermore, the memory controller performs timing management and read / write data buffering to manage data rate or timing differences between the processor and memory.

[0004] Memory controller designs are constantly evolving to support faster, larger, and more energy-efficient computing. The requirements for memory controllers in terms of timing, power consumption, and reliability are continuously increasing. Therefore, further improvements to memory controller technology are needed. Summary of the Invention

[0005] In view of this, the present invention provides an integrated circuit system and a control method for a memory controller in an integrated circuit system, so as to further maintain the performance stability and reliability of the integrated circuit system.

[0006] According to a first aspect of the present invention, a control method for a memory controller in an integrated circuit system is provided, comprising: performing bidirectional data transmission between a memory controller and a memory module at a clock frequency, wherein the data transmission in a first direction employs a first pulse amplitude modulation level and the data transmission in a second direction employs a second pulse amplitude modulation level; receiving an indication of increased data transmission demand in the first direction; and increasing the first pulse amplitude modulation level to a target pulse amplitude modulation level for data transmission in the first direction, while maintaining the clock frequency and the second pulse amplitude modulation level in the second direction.

[0007] Furthermore, it also includes: receiving another indication of reduced data transmission demand in the second direction; and reducing the second pulse amplitude modulation level in the second direction independently of the target pulse amplitude modulation level in the first direction. Therefore, the change in pulse amplitude modulation level in the first direction and the change in pulse amplitude modulation level in the second direction are independent of each other and do not interfere with each other, thereby independently handling data transmission demands in both the read and write directions, improving data transmission efficiency and flexibility.

[0008] Furthermore, receiving the instruction also includes receiving a data transfer request from a processor coupled to the memory controller that the first direction is more than the second direction. A more data transfer request may indicate that more data needs to be transferred, thus requiring an increase in the transfer rate, thereby further increasing the corresponding pulse amplitude modulation level.

[0009] Furthermore, the memory controller adjusts the pulse amplitude modulation level used for data transmission and reception based on the states of the write queue and read queue within the memory controller, respectively. By monitoring the write and read queues, it can determine whether the amount of data to be transmitted has increased or decreased, thus indicating whether the transmission rate needs to be increased or decreased, and adjusting the pulse amplitude modulation level accordingly.

[0010] Furthermore, the first direction is the direction read from the memory module. The method also includes: when increasing the first pulse amplitude modulation level, activating an additional voltage comparator to compare the received data voltage with a voltage threshold of the target pulse amplitude modulation level. This determines whether the pulse amplitude modulation level has been adjusted to the target pulse amplitude modulation level to achieve the intended purpose.

[0011] Furthermore, the first direction is the direction of writing to the memory module, and the method further includes: activating an additional weighted current source to convert the output symbol into a voltage level of the target pulse amplitude modulation level. This determines whether the pulse amplitude modulation level has been adjusted to the target pulse amplitude modulation level to achieve the intended purpose.

[0012] Furthermore, this memory module is based on a double data rate memory module or a high-bandwidth memory module to adapt to different application requirements.

[0013] According to a second aspect of the present invention, a control method for a memory controller in an integrated circuit system is provided, comprising: sending write data to a memory module at a first pulse amplitude modulation level; receiving read data from the memory module at a second pulse amplitude modulation level; receiving an indication of a change in operating conditions affecting the performance of the integrated circuit system; and changing at least one of the first pulse amplitude modulation level and the second pulse amplitude modulation level in response to the change in operating conditions, wherein any change to the first pulse amplitude modulation level is independent of the second pulse amplitude modulation level, and any change to the second pulse amplitude modulation level is independent of the first pulse amplitude modulation level.

[0014] Furthermore, it also includes: dynamically increasing at least one of the first pulse amplitude modulation level and the second pulse amplitude modulation level in response to an increase in the workload of the integrated circuit system. An increase in the workload of the integrated circuit system may indicate that more data needs to be transmitted, thus increasing the pulse amplitude modulation level increases the transmission rate.

[0015] Furthermore, it also includes: dynamically reducing at least one of the first pulse amplitude modulation level and the second pulse amplitude modulation level in response to changes in the power state of the integrated circuit system. This allows for adjustment of the pulse amplitude modulation level according to different requirements.

[0016] Furthermore, this memory module is either a double data rate memory module or a high-bandwidth memory module, to adapt to different application requirements.

[0017] According to a third aspect of the present invention, an integrated circuit system is provided, comprising: a memory module; and a memory controller coupled to the memory module, the memory controller being configured to perform the control method as described in any of the preceding claims.

[0018] The control method for the memory controller in the integrated circuit system of the present invention includes: performing bidirectional data transmission between the memory controller and the memory module at a clock frequency, wherein data transmission in the first direction uses a first pulse amplitude modulation level and data transmission in the second direction uses a second pulse amplitude modulation level; receiving an indication of increased data transmission demand in the first direction; and increasing the first pulse amplitude modulation level to the target pulse amplitude modulation level for data transmission in the first direction, while maintaining the clock frequency and the second pulse amplitude modulation level in the second direction. By employing the above-described scheme of the present invention, the data transmission rate in the first direction can be increased by increasing the first pulse amplitude modulation level while keeping the clock frequency and the second pulse amplitude modulation level constant. Therefore, the negative impact of increased relocking time required by the phase-locked loop or delay-locked loop due to clock frequency changes can be avoided, maintaining the stability and reliability of the integrated circuit system. Attached Figure Description

[0019] Figure 1 This is a block diagram illustrating an integrated circuit system in which embodiments of the present invention may operate.

[0020] Figure 2 This is a block diagram illustrating a memory controller and a memory module according to one embodiment.

[0021] Figure 3 This is a block diagram illustrating components of a memory controller according to one embodiment.

[0022] Figure 4A This is a block diagram illustrating the Rx circuitry in a memory controller according to one embodiment.

[0023] Figure 4B This is a block diagram illustrating the Tx circuitry in a memory controller according to one embodiment.

[0024] Figure 5 This is a block diagram illustrating an integrated circuit system in which a memory controller may operate according to another embodiment.

[0025] Figure 6A This is a flowchart illustrating a method performed by a memory controller according to one embodiment.

[0026] Figure 6B This is a flowchart illustrating a method performed by a memory controller according to another embodiment.

[0027] Figure 7A , Figure 7B , Figure 7C and Figure 7D A memory controller connected to different types of memory modules is shown according to some embodiments. Detailed Implementation

[0028] The following description is for illustrative purposes only and should not be construed as limiting. The scope of the invention is best determined by reference to the appended claims. In embodiments of the invention, when a component or layer is referred to as being “located,” “connected to,” or “coupled to” another component or layer, it may be directly located, connected to, or coupled to that other component or layer, or there may be intermediate components or layers. Conversely, when a component is referred to as being “directly located,” “directly connected to,” or “directly coupled to” another component or layer, there are no intermediate components or layers. The same numbers always refer to the same component. The term “and / or” as used herein includes any and all combinations of one or more of the associated listed items. “Directly above” or “directly below” may indicate that the projections of two or more of them at least partially overlap, while “not directly above” or “directly below” may indicate that the projections of two or more of them do not overlap at all.

[0029] This invention describes a memory controller that provides a dynamically adjustable modulation level. In one embodiment, the memory controller communicates with a memory module using pulse amplitude modulation (PAM) with an adjustable PAM level. The term "PAM level" refers to the number of different voltage levels used to represent symbols transmitted in PAM. For example, "PAM-N" means that N voltage levels are used to represent symbols transmitted in PAM. In the following description, specific PAM levels will be used as examples. It should be understood that the disclosed memory controller is not limited to the specific PAM levels described herein.

[0030] In one embodiment, the memory controller can send data to the memory module at a first PAM level and receive data from the memory module at a second PAM level different from the first PAM level. In another embodiment, the memory controller can respond to changes in runtime operating conditions by adjusting the PAM level used for single-directional or bi-directional communication with the memory module.

[0031] Non-limiting examples of memory modules include: one or more memory dies, a memory chip containing one or more memory dies, and a circuit board containing multiple memory chips, each memory chip containing one or more memory dies. The memory dies in the memory module may be stacked together and communicate with each other via through-silicon vias (TSVs) or wire bonding. Alternatively, the memory dies in the memory module may be arranged side-by-side. The memory module can be manufactured using any memory technology capable of PAM communication with a memory controller. Non-limiting examples of memory modules are referenced. Figures 7A-7D Provided.

[0032] As used herein, the term "die" refers to a semiconductor integrated circuit on which memory cells and / or logic circuit components are built. The term "data transfer rate" refers to the rate at which data bits are transmitted over a signal channel.

[0033] Figure 1This is a block diagram illustrating an integrated circuit system 100 (“System 100”) in which embodiments of the present invention may operate. System 100 includes a processor 110 coupled to a memory controller 130, which reads from and writes to a memory module 120 under instructions from the processor 110. The memory module 120 includes an array 122 of memory cells for data storage. In one embodiment, the memory controller 130 may be co-located on a single chip with the host processor 110, while the memory module 120 may be located externally to that chip. In another embodiment, the memory controller 130, the processor 110, and the memory module 120 may be co-located on the same chip.

[0034] although Figure 1 Only one processor 110 is shown, but it will be understood that system 100 may include multiple processors, and each processor may include one or more processing cores or computing units. Non-limiting examples of processor 110 include a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor (DSP), a neural processing unit (NPU), and any processing unit that uses a memory controller to access memory module 120.

[0035] Figure 2This is a block diagram illustrating further details of a memory controller 130 and a memory module 120 according to one embodiment. The memory controller 130 includes a transmitter (Tx) circuit 250, a receiver (Rx) circuit 270, and a PAM controller 230. The Tx circuit 250 and Rx circuit 270 in the memory controller 130 communicate with the Rx circuit 260 and Tx circuit 240 in the memory module 120, respectively. The PAM controller 230 in the memory controller 130 controls the PAM level communicating with the memory module 120. The PAM controller 230 coordinates the PAM level used for data transmission and reception with a memory-side PAM regulator 220. More specifically, when the PAM controller 230 determines the PAM level used for data transmission and / or reception, it requests the PAM regulator 220 to adjust that PAM level accordingly. The data transmission rate can be adjusted by adjusting the PAM level without changing the clock frequency. Maintaining the same clock frequency eliminates the re-locking time required by phase-locked loops (PLLs) or delay-locked loops (DLLs). The memory controller 130 also includes multiple queues 210 for temporarily storing read data, write data, and commands from the processor 110.

[0036] Figure 3 This is a block diagram illustrating further details of a memory controller 130 according to one embodiment. In the memory controller 130, a Tx circuit 250 sends data to a memory module 120, while an Rx circuit 270 receives data from the memory module 120. The Tx circuit includes circuit components such as a serializer 350 and a driver 355. The serializer 350 converts parallel outgoing data bits into a serial bitstream and creates bit groups to form symbols according to a modulation scheme. Each bit group represents a symbol. For PAM-2 (also known as non-return-to-zero, NRZ), each symbol contains 1 bit; for PAM-4, each symbol contains 2 bits; for PAM-8, each symbol contains 3 bits, and so on. The Tx path also includes a driver 355 for converting the serialized digital symbols into corresponding analog voltage levels.

[0037] In addition to other circuit components, Rx circuit 270 includes an equalizer and a gain amplifier circuit (“EQ_GA 375”, or gain amplifier circuit 375 in the figure) to compensate for signal loss and distortion along the Rx path. Rx circuit 270 also includes a symbol detector 370 for sampling and detecting symbols in the received data signal. The output of symbol detector 370 is a bitstream, with each bitstream representing a symbol. Deserializer 372 converts the symbol stream (bitstream) into parallel data for use by downstream digital circuitry.

[0038] In addition to Tx circuit 250 and Rx circuit 270, memory controller 130 also includes timing control logic 330 for managing timing constraints of data communication. Queues 210 in memory controller 130 also include write queue 311, read queue 312, and command queue 313. Read queue 312 temporarily stores data to be forwarded to processor 110. Figure 1 The incoming data bits are written to queue 311, which temporarily stores the outgoing data bits to be sent to memory module 120. Command queue 313 temporarily stores commands issued by processor 110. Non-limiting examples of these commands include memory access commands, such as read and write commands.

[0039] In one embodiment, the PAM controller 230 determines the PAM levels for data transmission and reception based on the rates at which the memory controller 130 receives write and read commands, respectively. In one embodiment, the PAM controller 230 can monitor the number of read and write commands awaiting execution in the command queue 313. In one embodiment, the PAM controller 230 may receive more data transmission requests from the processor 110 in a first direction (i.e., one of Tx and Rx) than in a second direction (i.e., the other of Tx and Rx), and accordingly increase the PAM level in the first direction or decrease the PAM level in the second direction. In one embodiment, the PAM controller 230 can decide to change the PAM level of the Tx circuit 250 based on the state of the write queue 311, for example, when the occupied capacity of the write queue 311 exceeds the upper limit (indicating a need to increase the PAM level) or falls below the lower limit (indicating an opportunity to decrease the PAM level). Similarly, the PAM controller 230 can decide to change the PAM level of the Rx circuit 270 based on the state of the read queue 312. The PAM controller 230 can independently adjust the PAM levels for read and write operations. In other words, the memory controller 130 can send data to the memory module 120 at a first PAM level and receive data from the memory module 120 at a second PAM level, wherein the first PAM level may be different from the second PAM level.

[0040] When the PAM controller 230 decides to increase the PAM level used for data transfer to the memory module 120, it signals the memory-side PAM regulator 220 to coordinate the increase. The PAM controller 230 also signals the serializer 350 and driver 355 to dynamically increase the PAM level without changing the clock frequency. When the serializer 350 increases the PAM level from, for example, PAM-2 to PAM-4, it dynamically changes the number of packets in the outgoing bitstream from 1 bit per bit group to 2 bits. Correspondingly, the driver 355 also increases the number of voltage levels according to the increased PAM level, so that each bit group maps to the corresponding voltage level. The PAM regulator 220 in the memory module 120 also makes a similar change to the number of voltage levels according to the increased PAM level.

[0041] Conversely, when the PAM controller 230 decides to reduce the PAM level of data transmission, it signals the memory-side PAM regulator 220 to coordinate the reduction of the PAM level. The PAM controller 230 signals the serializer 350 and the driver 355 to dynamically reduce the PAM level without changing the clock frequency. When reducing the PAM level, the serializer 350 dynamically changes the grouping of the outgoing bitstream to reduce the number of bits per bit group. Correspondingly, the driver 355 also reduces the number of voltage levels according to the reduced PAM level. The PAM regulator 220 in the memory module 120 also makes a similar change to the number of voltage levels according to the reduced PAM level.

[0042] When the PAM controller 230 decides to increase the PAM level of data received from the memory module 120, it signals the memory-side PAM regulator 220 to coordinate the increase of the PAM level. Then, the PAM controller 230 signals the symbol detector 370 to dynamically increase the PAM level without changing the clock frequency. For example, when the PAM level increases from PAM-2 to PAM-4, the symbol detector 370 increases the number of thresholds within the receiver voltage range according to the increased PAM level. In the example of PAM-4, the voltage (v) of each received data sample after equalization and gain amplification is compared with three voltage thresholds (e.g., T1, T2, and T3) that define the four voltage levels of PAM-4 (e.g., v < T1, T1 < v < T2, T2 < v < T3, and v > T3). The symbol detector 370 generates a symbol corresponding to the matched voltage level. Conversely, when the PAM level is reduced, the symbol detector 370 reduces the number of voltage thresholds within the receiver voltage range so that the voltage of each received data sample after equalization and gain amplification can be compared with the voltage thresholds of the reduced PAM level to identify the matched voltage level. Then, the symbol detector 370 generates a symbol corresponding to the matched voltage level. The PAM regulator 220 in the memory module 120 makes a similar change to the number of voltage levels mapped to the reduced PAM level.

[0043] Figure 4A is a block diagram showing the Rx circuit in the memory controller 130 according to an embodiment. Refer to Figure 2 and Figure 4AThe Rx circuit 270 includes a set of voltage comparators 420 (also known as slicers) connected in parallel. Each voltage comparator 420 compares the voltage of the received data signal with a corresponding PAM voltage level. For example, a PAM-4 receiver may include three voltage comparators 420, each with a corresponding voltage threshold at T1, T2, and T3. In one embodiment, the PAM controller 230 dynamically turns each individual voltage comparator 420 on and off based on the PAM level selected for data reception. The lower the PAM level, the fewer voltage comparators 420 are turned on, resulting in lower power consumption. Conversely, the higher the PAM level, the more voltage comparators 420 are turned on, resulting in higher power consumption. Similarly, the Rx circuit 260 in the memory module 120 may have the same voltage comparators 420 or similar circuitry for data reception.

[0044] Figure 4B This is a block diagram illustrating the Tx circuitry in a memory controller 130 according to one embodiment. (See reference...) Figure 2 and Figure 4B The Tx circuit 250 includes a weighted current source 450 connected to the current-steering digital-to-analog DAC and driver 455. The memory controller 130 can activate (enable) different groups of weighted current sources 450 for different PAM levels. When the PAM level in the transmission path used for a write operation is increased, the memory controller 130 can activate additional (or supplementary) weighted current sources 450 to generate an additional voltage level for the increased PAM level. Conversely, when the PAM level in the transmission path used for a write operation is decreased, the memory controller 130 can deactivate some of the already activated weighted current sources 450 to generate less voltage level for the decreased PAM level.

[0045] The memory controller 130 can dynamically adjust the PAM level based on the power and performance requirements of its system. At the same clock frequency, a higher PAM level increases the data transfer rate between the memory controller 130 and the memory module 120 because each symbol corresponds to more bits per unit time. At the same clock frequency, a lower PAM level decreases the data transfer rate because each symbol corresponds to fewer bits per unit time. Higher PAM levels typically require higher power consumption because the receiver needs to compare more voltage thresholds, and the transmitter needs to generate more voltage levels and more bits per voltage level. Therefore, lowering the PAM level helps reduce power consumption.

[0046] Figure 5This is a block diagram illustrating an integrated circuit system (“System 500”) in which a memory controller 130 according to another embodiment may operate. In this embodiment, System 500 includes an operating condition monitor 510 for monitoring the operating conditions of System 500 and / or processor 110. Non-limiting examples of operating conditions include power consumption, workload, and current or expected power and / or performance requirements of System 500 and / or processor 110. Furthermore, operating conditions may also include workload requirements of the software running on processor 110 and / or System 500, power / battery status, temperature, and performance targets of processor 110 and / or System 500. Changes in operating conditions can affect the performance of System 500. When the operating condition monitor 510 detects a change (modification) in operating conditions, System 500 may use dynamic voltage and frequency scaling (DVFS) techniques to adjust the operating frequency and voltage of one or more processors. Additionally or alternatively, System 500 may adjust system performance by adjusting memory I / O data transfer rates. For example, system 500 can improve system performance by increasing the data transfer rate or reduce power consumption by decreasing the data transfer rate. In one embodiment, performance improvement and power reduction can be achieved by changing the PAM level of data transfer between the memory controller 130 and the memory module 120.

[0047] In one embodiment, when a change in operating conditions indicates a change in the power state (e.g., when system 500 enters a low-power mode or battery mode), power consumption needs to be reduced. In response to the change in operating conditions, memory controller 130 may reduce the PAM level in one or both of the transmit and receive directions. The reduction of the PAM level can be performed independently, regardless of whether the clock frequency changes. Reducing memory I / O power consumption can improve system performance. Similarly, when a change in operating conditions indicates a need to improve the performance of processor 110 and / or system 500 (e.g., when workload increases), memory controller 130 may increase the PAM level in one or both of the transmit and receive directions to increase the data transfer rate. The increase of the PAM level can be performed independently, regardless of whether the clock frequency changes. By changing the PAM level for data transmission and / or reception, system 500 can improve system performance while maintaining the clock frequencies of processor 110, memory controller 130, and memory module 120.

[0048] Figure 6AThis is a flowchart illustrating a (control) method 600 performed by a memory controller 130 according to one embodiment. The (control) method 600 begins at step 610, where the memory controller 130 performs bidirectional data transmission between the memory controller and the memory module at a certain clock frequency, using a first PAM level in a first direction and a second PAM level in a second direction. In some embodiments, the first PAM level and the second PAM level may be different. At step 620, the memory controller 130 receives an indication of increased data transmission demand in the first direction. At step 630, the memory controller 130 increases the first PAM level to the target PAM level for data transmission in the first direction, while maintaining the clock frequency and the second PAM level in the second direction. In some embodiments, the clock frequency in the first direction may also remain unchanged, thus avoiding the negative impact of clock frequency changes. In some embodiments, the clock frequencies in the first and / or second directions may change or remain unchanged, so changes in the first and / or second PAM levels can be completely independent and unaffected by other factors (e.g., clock frequency, other circuit levels, etc.). In this embodiment of the invention, the change in pulse amplitude modulation level in the first direction and the change in pulse amplitude modulation level in the second direction are independent of each other and do not interfere with each other, thereby independently handling the data transmission needs in both the read and write directions, improving the efficiency and flexibility of data transmission.

[0049] In one embodiment, upon receiving another indication of reduced data transfer demand in the second direction, the memory controller reduces the second PAM level in the second direction independently of the target PAM level in the first direction. In one embodiment, the indication of increased data transfer demand in the first direction may be that there are more data transfer requests in the first direction than in the second direction, where these requests originate from a processor coupled to the memory controller. In one embodiment, the memory controller adjusts the PAM levels for data transfer and reception based on the states of the write queue and read queue in the memory controller, respectively.

[0050] In embodiments where the first direction is the read direction from the memory module, the memory controller may activate (or enable) an additional (or extra) voltage comparator when the first PAM level is increased. The additional (or extra) voltage comparator is used to compare the received data voltage with a voltage threshold of the target PAM level. In embodiments where the first direction is the write direction to the memory module, the memory controller may activate (or enable) an additional (or extra) weighted current source to convert the outgoing symbol to a voltage level of the target PAM level. In one embodiment, the memory module is a DDR (low-power double data rate) based memory module. In an alternative embodiment, the memory module is an HBM (high bandwidth memory) module. In some embodiments, the (control) method 600 may also include additional steps, such as the operations and steps described above, and related to... Figures 1 to 5 The related operations and steps are described. For example, (control) method 600 may also include, in step 620, memory controller 130 receiving an indication of increased data transfer demand in a first direction, receiving the indication further including: receiving from a processor coupled to the memory controller that the first direction requires more data transfer than the second direction.

[0051] Figure 6B This is a flowchart illustrating a (control) method 650 executed by a memory controller 130 according to another embodiment. The (control) method 650 begins at step 660, whereby the memory controller 130 sends write data to the memory module at a first PAM level, and begins at step 670, whereby the memory controller 130 receives read data from the memory module at a second PAM level. At step 680, the memory controller 130 receives an indication of a change in operating conditions affecting the performance of the integrated circuit system. At step 690, in response to the change in operating conditions, the memory controller 130 changes at least one of the first PAM level and the second PAM level. Any change in the first PAM level is independent of the second PAM level, and any change in the second PAM level is also independent of the first PAM level.

[0052] In one embodiment, the memory controller dynamically increases at least one of a first PAM level and a second PAM level in response to an increase in the workload of the integrated circuit system. In another embodiment, the memory controller dynamically decreases at least one of the first PAM level and the second PAM level. The PAM level changes in response to a change in the power state of the integrated circuit system. In one embodiment, the memory module is a DDR-based memory module. In an alternative embodiment, the memory module is an HBM module. In some embodiments, the (control) method 650 may also include other steps, such as the operations and steps described above, and related to... Figure 1 The operation and steps are described in Figure 6.

[0053] Figures 7A-7D A memory controller 130 is shown connected to different types of memory modules according to some embodiments. The memory controller 130 controls the PAM levels used for reading from and writing to the memory modules, wherein the PAM levels used for reading and writing can be adjusted independently of each other. Figure 7A The memory controller 130 is connected to one or more memory chips 710. The memory chips 710 can be manufactured using any known manufacturing technology and can communicate with the memory controller 130 according to any known memory I / O protocol. For example, the memory chip 710 can be dynamic random access memory (DRAM), synchronous DRAM (SDRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. Figure 7BIn this embodiment, the memory controller 130 communicates with a high-bandwidth memory (HBM) module 720, which contains memory dies arranged in a vertical stack and accessible via a TSV (through silicon via) 721. The memory controller 130 and the HBM module 720 can be co-located on a base die 723, which sits on top of the interposer and substrate 725. It is important to note that stacked memory technology is not limited to the HBM module 720. The memory controller 130 described above can be used in conjunction with memory stacks formed by other memory technologies, such as low-power double data rate (LPDDR) memory stacks. In one embodiment, LPDDR memory dies can be vertically stacked via wire bonding, with the bottom LPDDR die wire bonded to a package substrate. Alternatively, the LPDDR memory stack can be packaged in a single package. Figure 7C This illustration shows the communication between the memory controller 130 and a DDR-based memory chip 730 (e.g., DDR4, DDR5, DDR6, LPDDR, graphics DDR (GDDR) memory chip). The memory controller 130 and the DDR-based memory chip 730 can be co-located on the same package substrate 735. Alternatively, the DDR-based memory chip 730 can be located in a different package from the memory controller 130. Figure 7D The illustration shows the communication between the memory controller 130 and a DIMM (Dual In-line Memory Module) 740, which contains multiple memory chips. The memory controller 130 and the DIMM 740 can be co-located on the same printed circuit board (PCB) 745. Figures 7A-7D The memory controller 130 performs the aforementioned memory access operations with a dynamically adjustable PAM level, and the PAM level can be asymmetrically adjusted for reads and writes. More specifically, Figures 7A-7D The operations performed by the memory controller 130 include (control) method 600. Figure 6A ) and (control) methods 650 ( Figure 6B ).

[0054] In some embodiments, the integrated circuit system of this invention (e.g., integrated circuit system 100 or 500 described above) may include: a memory module (e.g., memory module 120); and a memory controller (e.g., memory controller 130) coupled to the memory module (e.g., memory module 120), the memory controller being configured to perform any of the control methods described above (e.g., control methods 600 and 650). In some embodiments, the memory module (e.g., memory module 120) may include one or more memory dies (e.g., memory die 730). In some embodiments, the memory controller (e.g., memory controller 130) includes a transmitter circuit (e.g., transmitter circuit 250) and a receiver circuit (e.g., receiver circuit 270) for bidirectional data transmission with the memory module (e.g., memory module 120) at a (certain) clock frequency, the bidirectional data transmission being performed at a first pulse amplitude modulation (PAM) level in a first direction and at a second PAM level in a second direction. When the memory controller (e.g., memory controller 130) receives an indication of increased data transmission demand in the first direction, the memory controller (e.g., memory controller 130) raises the first PAM level to the target PAM level for data transmission in the first direction, while maintaining the clock frequency and the second PAM level in the second direction.

[0055] In some embodiments, when the memory controller (e.g., memory controller 130) receives another indication of reduced data transfer demand in the second direction, the memory controller (e.g., memory controller 130) reduces the second PAM level in the second direction independently of the target PAM level in the first direction.

[0056] In some embodiments, a memory controller (e.g., memory controller 130) is coupled to a processor (e.g., processor 110), and an indication of increased demand is that there are more data transfer requests from the processor (e.g., processor 110) in a first direction than in a second direction.

[0057] In some embodiments, the memory controller (e.g., memory controller 130) adjusts the PAM levels for data transmission and reception based on the states of the write queue (e.g., write queue 311) and the read queue (e.g., read queue 312) in the memory controller (e.g., memory controller 130), respectively.

[0058] In some embodiments, when the first direction is the direction of reading from the memory module (e.g., memory module 120), when the first PAM level is increased, the memory controller (e.g., memory controller 130) activates an additional voltage comparator to compare the received data voltage with a voltage threshold of the target PAM level.

[0059] In some embodiments, when the first direction is the direction of writing to the memory module, when the first PAM level is increased, the memory controller (e.g., memory controller 130) activates an additional weighted current source to convert the output symbol to the voltage level of the target PAM level.

[0060] In some embodiments, when a memory controller (e.g., memory controller 130) receives an indication of a change in operating conditions affecting the performance of an integrated circuit system (e.g., system 100, 500), the memory controller (e.g., memory controller 130) responds to the change by altering at least one of a first PAM level and a second PAM level.

[0061] In some embodiments, the memory module (e.g., memory module 120) is a double data rate (DDR) based memory module. In some embodiments, the memory module (e.g., memory module 120) is a high bandwidth memory (HBM) module.

[0062] In some embodiments of the invention, the memory controller (e.g., memory controller 130) may be a calculator device, including a storage medium storing program code that can be read and executed by the calculator device (e.g., memory controller 130). By reading this program code from the storage medium, the calculator device (e.g., memory controller 130) can execute the control methods described above (e.g., control methods 600 and 650).

[0063] In some embodiments, the control method of the present invention involves a first step of performing bidirectional data transmission between a memory controller and a memory module at a clock frequency, transmitting at a first PAM level in a first direction and at a second PAM level in a second direction. A second step involves receiving an indication of increased data transmission demand in the first direction. A third step involves raising the first PAM level to the target PAM level for data transmission in the first direction while maintaining the clock frequency and the second PAM level in the second direction.

[0064] In some embodiments, the control method of the present invention involves the following steps: First, transmitting write data to a memory module at a first PAM level. Second, receiving read data from the memory module at a second PAM level. Third, receiving an indication of a change in operating conditions affecting the performance of the integrated circuit system. Fourth, changing at least one of the first PAM level and the second PAM level according to the change in operating conditions. Any change in the first PAM level is independent of the second PAM level, and any change in the second PAM level is independent of the first PAM level.

[0065] Referenced Figure 1-5The exemplary embodiments described in FIG7 are as follows Figure 6A and Figure 6B The flowchart operation. However, it should be understood that Figure 6A and Figure 6B The operation of the flowchart can be performed by, except Figure 1-5 The embodiments of the present invention are performed in addition to those shown in Figure 7, and Figure 1-5 The embodiments shown in Figure 7 can perform operations different from those discussed in the flowchart of the reference figure. Although Figure 6A and Figure 6B The flowchart illustrates a specific sequence of operations performed by certain embodiments of the present invention, but it should be understood that the sequence is exemplary (e.g., alternative embodiments may perform operations in a different order, combine certain operations, overlap certain operations, etc.).

[0066] While the invention has been described by way of example and according to preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. Rather, it is intended to cover various modifications and similar arrangements (as will be apparent to those skilled in the art). Therefore, the scope of the appended claims should be given the broadest interpretation to cover all such modifications and similar arrangements.

Claims

1. A control method for a memory controller in an integrated circuit system, characterized in that, include: Bidirectional data transmission is performed between the memory controller and the memory module at a clock frequency. Data transmission in the first direction uses a first pulse amplitude modulation level, and data transmission in the second direction uses a second pulse amplitude modulation level. Receive an indication of increased data transmission demand in the first direction; as well as The first pulse amplitude modulation level is boosted to the target pulse amplitude modulation level for data transmission in the first direction, while the clock frequency and the second pulse amplitude modulation level are maintained in the second direction.

2. The control method as described in claim 1, characterized in that, Also includes: Receive another indication of reduced data transmission demand in the second direction; as well as Independent of the target pulse amplitude modulation level in the first direction, the second pulse amplitude modulation level in the second direction is reduced.

3. The control method as described in claim 1, characterized in that, Receiving this instruction also includes: The processor coupled to the memory controller receives a data transfer request in the first direction that is greater than that in the second direction.

4. The control method as described in claim 1, characterized in that, The memory controller adjusts the pulse amplitude modulation level used for data transmission and reception based on the states of the write queue and read queue within the memory controller, respectively.

5. The control method as described in claim 1, characterized in that, The first direction is the direction read from the memory module, and the method further includes: When the first pulse amplitude modulation level is increased, an additional voltage comparator is activated to compare the received data voltage with the voltage threshold of the target pulse amplitude modulation level.

6. The control method as described in claim 1, characterized in that, The first direction is the direction of writing to the memory module, and the method further includes: Activate an additional weighted current source to convert the output symbol to the voltage level of the target pulse amplitude modulation level.

7. The control method as described in claim 1, characterized in that, This memory module is either a double data rate memory module or a high bandwidth memory module.

8. A control method for a memory controller in an integrated circuit system, characterized in that, include: Write data is sent to the memory module at the first pulse amplitude modulation level; Data is received and read from the memory module using the second pulse amplitude modulation level; Receive indications of changes in operating conditions that affect the performance of the integrated circuit system; as well as In response to changes in operating conditions, at least one of a first pulse amplitude modulation level and a second pulse amplitude modulation level is changed, wherein any change to the first pulse amplitude modulation level is independent of the second pulse amplitude modulation level, and any change to the second pulse amplitude modulation level is independent of the first pulse amplitude modulation level.

9. The control method as described in claim 8, characterized in that, Also includes: In response to an increase in the workload of the integrated circuit system, at least one of the first pulse amplitude modulation level and the second pulse amplitude modulation level is dynamically increased; and / or In response to changes in the power state of the integrated circuit system, at least one of the first pulse amplitude modulation level and the second pulse amplitude modulation level is dynamically reduced.

10. An integrated circuit system, characterized in that, include: Memory module; as well as A memory controller coupled to the memory module is configured to perform the control method as described in any one of claims 1 to 9.

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