HDMI automatic screen lighting test method and system

Abstract

The invention relates to the technical field of video interface testing, in particular to an HDMI automatic screen lighting testing method and system. The method comprises the steps of configuring an initial state of a system, detecting signal input of an HDMI receiving end, calculating a TMDS clock frequency, automatically configuring system parameters, verifying stability of the clock frequency of a data channel and the like, and signal self-adaptive synchronization is achieved through formulation calculation and dynamic adjustment of a register. The system is composed of a power supply system, a signal system, an automatic screen lighting system and a peripheral interface, the signal system comprises a plurality of HDMI receiving interfaces, a signal processing module and a plurality of sending modules, the power supply system provides stable voltage through a multi-stage power supply module, and the automatic screen lighting system controls a test process through a main I2C interface. According to the method, automatic identification, parameter optimization and integrity verification of the HDMI signal are realized, the test efficiency and precision are improved, and the method is particularly suitable for reliability evaluation in a high-resolution and high-refresh-rate scene.

Description

Technical Field

[0001] This invention relates to the field of video interface testing technology, and specifically to an HDMI automatic screen testing method and system. Background Technology

[0002] As the mainstream standard in the current audio and video transmission field, HDMI (High-Definition Multimedia Interface) testing technology is crucial for ensuring the reliability of display devices, signal sources, and transmission links. In existing technologies, HDMI testing typically relies on manual operation or semi-automated solutions, resulting in significant efficiency and accuracy bottlenecks. Traditional testing systems often require manual intervention in signal source switching and parameter configuration. Especially when dealing with signals of various resolutions and refresh rates, testers must repeatedly adjust device register settings, a process that is not only time-consuming and labor-intensive but also prone to introducing human error, leading to inconsistent test results. Furthermore, existing systems are insufficient in signal synchronization processing. For example, when the signal source frequently switches output modes, the receiver may not be able to quickly lock onto the clock frequency, causing issues such as screen flickering and audio interruptions, making it difficult to meet the stringent requirements of high-bandwidth applications such as 4K / 8K. At the system architecture level, most traditional solutions lack intelligent signal monitoring and adaptive mechanisms, cannot verify the stability of the data channel in real time, and have relatively crude power management, which may affect the performance of sensitive modules (such as phase-locked loops and reference voltage sources) due to voltage fluctuations, thereby reducing test accuracy. While some improvement solutions attempt to incorporate automation, their core remains reliant on preset fixed parameters, lacking adaptability to dynamic signals and failing to achieve closed-loop optimization across the entire process from signal detection and parameter configuration to integrity verification. Therefore, there is an urgent need in the field for an HDMI testing method and system capable of automatically identifying signal characteristics, dynamically adjusting system parameters, and continuously monitoring signal quality to improve testing efficiency, accuracy, and reliability.

[0003] Therefore, the existing technology still needs further development. Summary of the Invention

[0004] The purpose of this invention is to overcome the above-mentioned technical deficiencies and provide an HDMI automatic screen testing method and system to solve the problems existing in the prior art.

[0005] To achieve the above-mentioned technical objectives, according to a first aspect of the present invention, the present invention provides an HDMI automatic screen testing method, comprising: S100, Initial state of configuring the HDMI test system; S200: Detect whether there is a signal input at the HDMI receiver; S300. When a signal input is detected, calculate the TMDS clock frequency; S400. Automatically configure the parameters of the HDMI system based on the TMDS clock frequency; S500 verifies the clock frequency stability of the HDMI data channel.

[0006] Specifically, the initial state of the configured HDMI test system includes: Disable the physical layer driver on the HDMI receiver and set the HDMI data channel to power deceleration mode.

[0007] Specifically, setting the HDMI data channel to power-down mode includes: The power descent mode is triggered by detecting the voltage difference of the TMDS differential signal, and the receiver termination resistor is enabled to match the transmission line impedance.

[0008] Specifically, detecting whether there is a signal input at the HDMI receiver includes: Monitor the TMDS port status flag of the HDMI receiver and determine that there is a signal input when the status flag is detected to be valid.

[0009] Specifically, the monitoring of TMDS port status flags includes: enabling hot-plug detection function and delaying the waiting for status flag changes, wherein the delay time is configurable.

[0010] Specifically, the calculation of the TMDS clock frequency includes: The physical layer register value of the HDMI receiver is read, and the frequency value is calculated based on a predetermined formula, wherein the calculation includes multiple reads to verify frequency stability.

[0011] Specifically, the parameters for automatically configuring the HDMI system include: Based on the TMDS clock frequency, configure the divider coefficients, oversampling rate, and phase-locked loop parameters to synchronize the clock signal.

[0012] Specifically, verifying the clock frequency stability of the HDMI data channel includes: The clock frequency value of the data channel is read multiple times and compared with the target frequency. When the frequency deviation is within the predetermined range, it is determined to be stable.

[0013] Specifically, once the frequency is verified to be stable, the verification steps are repeated cyclically to continuously monitor signal integrity.

[0014] According to a second aspect of the present invention, an HDMI automatic screen testing system is provided, comprising: A power supply system used to provide a stable voltage supply through multi-stage power modules; The signal system includes multiple HDMI receiving interfaces, an HDMI receiving module, a control module, an eARC transmitting module, an LVDS transmitting module, and an HDMI transmitting module, wherein the control module is configured to process signals and transmit them in a directional manner; The automatic screen activation system communicates with the control module via the main I2C interface to automatically execute signal detection and configuration processes. Peripheral interfaces, including I2C and QSPI interfaces, are used to connect to external memory.

[0015] Beneficial effects: The HDMI automatic screen testing method and system provided by this invention achieves many significant benefits through collaborative innovation in hardware architecture and process design.

[0016] Firstly, at the methodological level, a fully automated signal detection and parameter configuration process is adopted. By calculating the TMDS clock frequency in real time and dynamically adjusting the frequency divider, oversampling rate, and PLL parameters based on the results, the lag and subjectivity of traditional manual operation are completely eliminated. This not only improves testing efficiency several times over but also ensures the accuracy of clock synchronization under high-resolution signals, effectively avoiding display anomalies caused by synchronization mismatch. At the system level, through the refined design of multi-level power modules, stable and low-noise power supply is provided to different functional modules, significantly reducing the interference of power fluctuations on the signal processing link, thereby improving the consistency of test results.

[0017] Secondly, this invention introduces a multi-channel parallel verification mechanism. By independently monitoring the clock frequency stability of each data channel, it can accurately locate signal degradation problems in specific channels, achieving comprehensive performance evaluation from the overall system to its local components, and greatly enhancing the system's fault diagnosis capabilities. Furthermore, in terms of hardware integration, standardized interfaces (such as master / slave I2C and QSPI) connect the automatic screen-reading system to the peripheral memory, enabling the system to possess both high automation and good scalability, facilitating integration into more complex testing environments.

[0018] Finally, the entire solution seamlessly integrates signal detection, parameter calculation, configuration optimization, and continuous monitoring to form a closed-loop control. This not only adapts to dynamic scenarios with frequent signal source switching but also ensures signal integrity during long-term testing through a cyclic verification mechanism.

[0019] In summary, this invention improves testing accuracy, efficiency, and reliability while also possessing the advantages of clear structure and simple implementation, providing a complete solution for high-quality verification of HDMI devices. Attached Figure Description

[0020] Figure 1 This is a flowchart illustrating the HDMI automatic screen testing method provided in a specific embodiment of the present invention; Figure 2 This is a schematic diagram of the system composition of the HDMI automatic screen testing system provided in a specific embodiment of the present invention; Figure 3This is a schematic diagram illustrating the specific components of the HDMI testing system provided in a specific embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings. Based on the embodiments in this application, other similar embodiments obtained by those skilled in the art without creative effort should all fall within the scope of protection of this application. Furthermore, directional terms mentioned in the following embodiments, such as "up," "down," "left," and "right," are only for reference to the directions in the accompanying drawings; therefore, the directional terms used are for illustrative purposes and not for limiting the invention.

[0022] The present invention will be further described below with reference to the accompanying drawings and preferred embodiments.

[0023] Please see Figure 1 This invention provides an HDMI automatic screen tapping test method, comprising: S100, initial state of configuring the HDMI test system.

[0024] It should be further explained that configuring the initial state of the HDMI test system involves setting software or hardware control registers, such as disabling the physical layer driver of the HDMI receiver. Specifically, this includes setting registers reg_rxb_scl_func_sel=1 and reg_rxb_sda_func_sel=1 to disable the DDC response, and setting reg_rx_phy_port_sel=portB and reg_rx_port_sel=BCD to select the RXB path.

[0025] S200: Detect whether there is a signal input at the HDMI receiver.

[0026] It should be further explained that when the detection signal is input, the TMDS port status flag regr_rx_phy_tmds_port_flag is monitored. When the flag is 1, it indicates that a device has been connected.

[0027] S300. When a signal input is detected, calculate the TMDS clock frequency.

[0028] It should be further explained that the TMDS clock frequency is calculated using formula (1): tmds_clock_freq=regr_rx_phy_tmds_clk_frq / 2048 27, where regr_rx_phy_tmds_clk_frq is the TMDS clock frequency register value of the HDMI receiver physical layer, 2048 is a frequency division constant used to convert the register value to the base frequency, and 27 is a scaling factor used to convert the frequency unit to MHz.

[0029] S400: Automatically configure the parameters of the HDMI system based on the TMDS clock frequency.

[0030] It should be further explained that the automatic configuration parameters include setting the divider coefficient reg_rx_phy_cr_prediv, the oversampling rate reg_rx_phy_osr, and phase-locked loop parameters such as reg_tx_pll1_prediv and reg_tx_pll1_sscg_plln based on the calculated tmds_clock_freq to ensure clock synchronization.

[0031] S500 verifies the clock frequency stability of the HDMI data channel.

[0032] It should be further explained that, when verifying frequency stability, the clock frequency values ​​regr_rx_phy_lane_clk_frq_0, regr_rx_phy_lane_clk_frq_1, and regr_rx_phy_lane_clk_frq_2 of the data channel are read multiple times, and the actual frequencies lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real are calculated using the formula. These are then compared with the target frequency lane_clock_freq_target. If the deviation is within 1%, it is considered stable.

[0033] Understandably, this method achieves rapid detection and configuration of HDMI signals through automated steps, reducing manual intervention and improving testing efficiency; the formulaic frequency calculation and parameter configuration ensure high-precision synchronization, which is particularly suitable for high-resolution display devices and avoids signal distortion; the overall process is based on hardware register operations, enhancing reliability and repeatability.

[0034] Specifically, the initial state of the HDMI test system configuration includes: disabling the physical layer driver of the HDMI receiver and setting the HDMI data channel to power degradation mode.

[0035] It should be further explained that disabling the physical layer driver involves configuring relevant registers, such as reg_rx_phy_port_sel and reg_rx_port_sel, to disable the PHY function and prevent signal interference. Setting the data channel to power-down mode involves triggering mode switching by detecting the voltage difference between the TMDS differential signal pairs and enabling the receiver termination resistor to match the transmission line impedance and reduce signal reflection; specific register settings include configuring the lane to Powerdown mode and enabling the termination resistor function. This step is performed during system startup to ensure reduced power consumption when there is no signal input.

[0036] Understandably, this initial configuration optimizes system energy efficiency and avoids unnecessary power loss; the use of power descent mode and terminating resistors improves signal integrity and provides a clean environment for subsequent detection; and hardware-level drive control enhances system stability and anti-interference capabilities.

[0037] Specifically, setting the HDMI data channel to power-down mode includes: triggering entry into power-down mode by detecting the voltage difference of the TMDS differential signal, and enabling the receiver termination resistor to match the transmission line impedance.

[0038] It should be further explained that the TMDS differential signal voltage difference is detected by comparing the voltage values ​​of the positive and negative signal lines. When the voltage difference falls below a threshold, a power descent mode is triggered. This threshold can be set based on the hardware design, for example, a typical value of 100mV, to ensure rapid entry into power-saving mode in the absence of a signal. Enabling the terminating resistor involves setting a register to activate the resistor network, with an impedance value matched to the transmission line characteristics, such as 75 ohms, to reduce reflections. This process is completed automatically by the hardware circuitry without software intervention.

[0039] Understandably, voltage difference detection provides an efficient power management mechanism, extending device lifespan; matching of terminating resistors optimizes signal transmission quality, preventing ringing and distortion; and the overall design, based on hardware automation, improves response speed and reliability.

[0040] Specifically, detecting whether there is a signal input at the HDMI receiver includes: monitoring the TMDS port status flag of the HDMI receiver, and determining that there is a signal input when the status flag is detected to be valid.

[0041] It should be further explained that the monitoring of the TMDS port status flag `regr_rx_phy_tmds_port_flag` is implemented by periodically querying the register value. When the flag is 1, it indicates that a valid signal input has been detected. The query period is configurable, for example, reading after a 50ms delay to avoid false positives. The judgment logic is based on the flag value; if it remains valid, the signal is confirmed to be connected; otherwise, the detection is repeated. This step is integrated after system initialization to ensure timely response to signal changes.

[0042] Understandably, status flag monitoring provides a simple hardware-level detection mechanism, reducing complexity; configurable delays enhance flexibility and adapt to different signal sources; and automated judgment reduces human error and improves the degree of test automation.

[0043] Specifically, the monitoring of TMDS port status flags includes: enabling hot-plug detection function and delaying the waiting for status flag changes, wherein the delay time is configurable.

[0044] It should be further explained that enabling the hot-plug detection function is achieved by setting the relevant HPD control bits in the register `reg_rx_phy_tmds_port_flag`, for example, enabling the HPD circuitry to monitor the port connection status. The delay involves inserting a configurable delay period, such as 50ms or 100ms, after enabling HPD to ensure signal stability; the delay time can be adjusted via software parameters to accommodate different device response speeds. Flag change detection occurs after the delay, confirming the status by reading the register value.

[0045] Understandably, the hot-plug detection function enhances the system's adaptability to dynamic connections and supports plug-and-play scenarios; configurable delay avoids false alarms caused by jitter and improves detection accuracy; and the combination of hardware and delay optimizes the user experience.

[0046] Specifically, the calculation of the TMDS clock frequency includes: reading the physical layer register value of the HDMI receiver and calculating the frequency value based on a predetermined formula, wherein the calculation includes multiple readings to verify frequency stability.

[0047] It should be further explained that reading the physical layer register value regr_rx_phy_tmds_clk_frq is accomplished by accessing the register via I2C or a similar interface, and the value is read ten times to obtain multiple samples. The frequency is calculated based on formula (1): tmds_clock_freq = regr_rx_phy_tmds_clk_frq / 2048 27, where regr_rx_phy_tmds_clk_frq is the original value of the TMDS clock frequency register, in units of counts; 2048 is a division factor used to convert the count value to the base frequency; and 27 is a multiplication factor used to scale the frequency to MHz. To verify stability, the deviations of ten calculations are compared. If all values ​​are within the range of 25MHz to 380MHz and differ by less than 1%, the frequency is considered stable. The physical meanings of the formula components are: regr_rx_phy_tmds_clk_frq represents the output of the hardware counter, reflecting the number of clock cycles; 2048 is the standard division ratio used for normalization; and 27 is a constant in the HDMI specification used for frequency conversion.

[0048] Understandably, multiple readings and formula calculations ensure high accuracy in frequency measurement and reduce random errors; stability verification avoids the impact of instantaneous fluctuations and improves test reliability; and formula processing simplifies implementation and facilitates integration into automated systems.

[0049] Specifically, the parameters of the automatically configured HDMI system include: configuring the divider coefficient, oversampling rate, and phase-locked loop parameters based on the TMDS clock frequency to synchronize the clock signal.

[0050] It should be further explained that the frequency divider coefficient reg_rx_phy_cr_prediv is set according to the value of tmds_clock_freq. For example, it is set to 1 when tmds_clock_freq is less than 100MHz, 2 when it is between 100MHz and 200MHz, and 4 when it is greater than or equal to 200MHz. The oversampling rate reg_rx_phy_osr is configured based on DataRate, which is calculated by formula (3): DataRate = lane_clock_freq_target 10, where lane_clock_freq_target is derived from formula (2): lane_clock_freq_target = tmds_clock_freq The ratio is set according to regc_SCDC_TMDSBITCLKRATIO (ratio=1 when 0, ratio=4 when 1). PLL parameters include reg_tx_pll1_prediv and reg_tx_pll1_sscg_plln, set according to lane_clock_freq_target and DataRate. For example, reg_tx_pll1_prediv is set to 1 between 25MHz and 50MHz, and so on. Synchronization is achieved through register writing.

[0051] Understandably, automatic parameter configuration optimizes clock synchronization, ensuring the processing accuracy of high-resolution signals; frequency-based dynamic adjustment enhances system adaptability; and hardware parameterization reduces latency and improves overall performance.

[0052] Specifically, verifying the clock frequency stability of the HDMI data channel includes: repeatedly reading the clock frequency value of the data channel and comparing it with the target frequency; when the frequency deviation is within a predetermined range, it is determined to be stable.

[0053] It should be further explained that reading the clock frequency value of the data channel multiple times involves accessing registers regr_rx_phy_lane_clk_frq_0, regr_rx_phy_lane_clk_frq_1, and regr_rx_phy_lane_clk_frq_2 ten times each, and the actual frequency is calculated using formulas (6), (7), and (8): lane0_clock_freq_real = regr_rx_phy_lane_clk_frq_0 / 2048 27, lane1_clock_freq_real=regr_rx_phy_lane_clk_frq_1 / 2048 27, lane2_clock_freq_real=regr_rx_phy_lane_clk_frq_2 / 2048 27. The target frequency lane_clock_freq_target is derived from formula (2). When comparing deviations, the predetermined range is 1%, that is, if the absolute value of the difference between all actual frequencies and the target frequency is less than 1%, it is considered stable. The physical meaning of the formula components: regr_rx_phy_lane_clk_frq_0, regr_rx_phy_lane_clk_frq_1 and regr_rx_phy_lane_clk_frq_2 represent the clock count register values ​​of the three data channels, respectively; the meanings of 2048 and 27 are the same as in formula (1), used for frequency conversion.

[0054] Understandably, multi-channel frequency verification ensures the consistency of the signal path and improves the comprehensiveness of the test; setting the deviation threshold to 1% balances accuracy and fault tolerance, avoiding overly strict judgment; automated comparison reduces subjective errors and enhances the reliability of the results.

[0055] Specifically, once the frequency is verified to be stable, the verification steps are repeated cyclically to continuously monitor signal integrity.

[0056] It should be further explained that the cyclical verification step includes periodically reading register values ​​and calculating the frequency after the frequency stabilizes, for example, every 100ms, continuously comparing the actual frequency with the target frequency. If the deviation exceeds 1%, a reconfiguration process is triggered. The cycle period is configurable to accommodate long-term testing needs. This process is implemented through a hardware timer or software loop to ensure real-time monitoring.

[0057] Understandably, cyclic monitoring provides continuous signal quality assurance and prevents runtime degradation; configurable cycles enhance flexibility and support different application scenarios; and automated reconfiguration improves the system's self-healing capabilities.

[0058] Please see Figure 2 The present invention provides another embodiment, which provides an HDMI automatic screen testing system, the HDMI automatic screen testing system comprising: (1) Power supply system 100, used to provide a stable voltage supply through a multi-stage power supply module.

[0059] It should be further explained that the power system 100 adopts a multi-stage design. The first stage is a DC-DC power supply such as TPS54302, with an input of 4.5V to 28V and an output of 5V, with a load capacity of 3A. The second stage includes multiple LDO branches, such as LP3983SAB5F, with outputs of 3.3V, 0.9V and 1.8V, to power various modules, such as AVDD33BG and AVDD33RX.

[0060] (2) Signal system 200, including multiple HDMI receiving interfaces, HDMI receiving module, control module, eARC transmitting module, LVDS transmitting module and HDMI transmitting module, wherein the control module is configured to process signals and transmit them in a directional manner.

[0061] It should be further explained that the HDMI receiving interface of the signal system 200 includes HDMI-A, B, C and D interfaces, each with three data paths. After receiving the signal, the HDMI receiving module splits it into dout_lane0, dout_lane1 and dout_lane2. The control module processes the signal and sends it to the eARC, LVDS and HDMI transmitting modules.

[0062] (3) Automatic screen-pointing system 300 communicates with the control module through the main I2C interface and is used to automatically execute signal detection and configuration processes.

[0063] It should be further noted that the automatic screen activation system 300 communicates via the main I2C interface. The peripheral interface 400, including a slave I2C interface and a QSPI interface, is used to connect to external memory.

[0064] (4) Peripheral interface 400, including I2C interface and QSPI interface, for connecting external memory.

[0065] It should be further noted that the peripheral interface 400 connects to EEPROM and FLASH for storing configuration and programs. All connections are implemented via hardware buses, such as PCB traces.

[0066] Understandably, multi-stage power supplies provide efficient and stable power supply and reduce noise interference; modular signal systems support parallel testing and improve throughput; standardized interfaces enhance scalability and facilitate system integration; and the overall hardware design optimizes signal integrity, meeting the needs of high-bandwidth applications.

[0067] In other preferred embodiments, please refer to Figure 3 This invention provides an HDMI testing system, comprising: It includes a power system, a signal system, an automatic screen activation system, and peripherals. The signal system includes multiple HDMI receiving interfaces, an HDMI receiving module, a control module, an eARC transmitting module, an LVDS transmitting module, and an HDMI transmitting module. The HDMI receiving interfaces are connected to the HDMI receiving modules, the HDMI receiving modules are connected to the control module, and the control module is connected to the eARC transmitting module, the LVDS transmitting module, and the HDMI transmitting module, respectively, for transmitting audio and video signals to external receiving devices.

[0068] It should be further explained that the HDMI testing system of the present invention achieves efficient signal transmission and processing through the integrated connection of hardware modules. Specifically, the power supply system provides stable power to the entire system, the signal system is responsible for receiving, parsing, and forwarding HDMI signals, the automatic screen-pointing system realizes automatic signal identification and switching, and peripherals include storage devices to support system configuration. Each of the multiple HDMI receiving interfaces (such as HDMI-A, HDMI-B, HDMI-C, and HDMI-D interfaces) has three data paths (0, 1, 2) for receiving differential signals from a signal source (such as a 780E device); these interfaces are directly connected to the HDMI receiving module, which splits the received three data paths into three 20-bit channels: dot_lane0, dot_lane1, and dot_lane2. The control module, as the core processing unit, is connected to the HDMI receiving module and outputs audio signals to the eARC transmitting module (for transmission to audio equipment), video signals to the LVDS transmitting module (for transmission to the FPGA acquisition and analysis system), and complete signals to the HDMI transmitting module (for transmission to a 4K display). This modular connection ensures clear and isolated signal paths, avoiding signal interference.

[0069] For better understanding, please continue reading. Figure 3 The accompanying drawings illustrate the overall system architecture of one embodiment of the present invention. Figure 3 The HDMI test system and its interconnections are clearly illustrated in a block diagram: The signal system includes a signal source, HDMI-A to HDMI-D interfaces, an HDMI receiver module, a control module, a master / slave I2C interface, a QSPI interface, an automatic screen activation system, and peripheral memory (EEPROM and FLASH). The signal source is connected to the HDMI receiver module via multiple HDMI interfaces. The output of this module is connected to the control module, which communicates with the automatic screen activation system, peripheral memory, and subsequent transmission modules. The receiving devices include audio equipment, an FPGA acquisition and analysis system, and a 4K display. These are connected to the control module via an eARC transmission module, an LVDS transmission module, and an HDMI transmission module, respectively, to receive processed audio and video signals. The power system supplies power to the PLL module, LDO module, and BG module, which provide clock and reference voltages to the various functional modules in the signal system. Figure 3 The arrows and lines clearly show the flow of data from the signal source through reception, control, and transmission, as well as the power supply path, fully presenting the hardware structure of the system and the physical connections between modules.

[0070] Understandably, through the fixed connection of hardware modules, the system can stably process signals of different frequencies and refresh rates, improving test accuracy and reliability; direct data transmission between modules reduces latency, making it suitable for high-resolution 4K / 8K test scenarios; the overall structure is compact, easy to implement and maintain.

[0071] Specifically, the power system includes multi-stage power modules, which provide power outputs of different voltages to the signal system, automatic screen activation system, and peripherals.

[0072] It should be further explained that the multi-stage design of the power supply system ensures the stability and efficiency of power supply. The multi-stage power module is divided into two stages: the first stage is a DC-DC power module (such as TPS54302), which converts the input voltage of 4.5~28V to 5V output (±2% accuracy, load capacity 3A), serving as the main power supply for the system; the second stage includes multiple branch power modules, such as LDO modules (such as LP3983SAB5F) and DC-DC modules (such as JW5250S), which subdivide the 5V voltage into different levels such as 3.3V, 0.9V, and 1.8V, providing customized power supply for various modules of the signal system (such as HDMI receiving module, control module, eARC transmitting module, etc.) and peripherals. For example, the 3.3V branch powers the AVDD33BG (reference voltage module, 10mA power consumption) and AVDD33RX (HDMI receiver module, 80mA power consumption); the 0.9V branch powers the AVDD09PLL (master clock phase-locked loop module, 15mA power consumption); and the 1.8V branch powers other peripherals. This multi-stage power module reduces energy loss through graded conversion and improves power stability by utilizing the low-noise characteristics of LDOs.

[0073] Understandably, multi-level power supply matches the power consumption requirements of different modules, avoiding signal distortion caused by voltage fluctuations; the combination of DC-DC and LDO optimizes energy efficiency and extends system lifespan; modular power branches simplify wiring and enhance system scalability and reliability.

[0074] Specifically, the multi-stage power supply module includes a first-stage DC-DC power supply module and a second-stage LDO power supply module. The first-stage DC-DC power supply module converts the input voltage to a 5V output, and the second-stage LDO power supply module includes multiple branch circuits for subdividing the 5V voltage into 3.3V, 0.9V and 1.8V outputs, and powering the various modules of the signal system.

[0075] It should be further explained that the first-stage DC-DC power module adopts a high-efficiency switching power supply design with a wide input range (4.5~28V) and a stable 5V output, providing the basic power supply for the system. The second-stage LDO power module is based on the linear regulation principle to achieve low-noise voltage conversion. The specific branch circuit includes: the first branch is an LDO (such as LP3983SAB5F), with a 5V input and a 3.3V output (300mA load capacity), and Vout=0.8V is set through a feedback resistor. (1 + 33 / 10.5) = 3.3V, powering modules such as AVDD33BG and AVDD33RX; the second branch is a DC-DC converter (such as JW5250S), with a 5V input and a 0.9V output (1A load capacity), powering the main module; the third branch is an LDO, with a 5V input and a 0.9V output (300mA load capacity), powering modules such as AVDD09PLL and AVDD09TXPLL0; the fourth branch is an LDO, with a 5V input and a 1.8V output (300mA load capacity), powering other peripherals. These branch circuits are directly connected to the power pins of the corresponding modules through PCB wiring, ensuring a short power supply path.

[0076] Understandably, the high efficiency of the DC-DC module reduces heat loss, and the low noise characteristics of the LDO module ensure the clock accuracy of signal processing modules (such as PLL and BG modules); the multi-branch design achieves power isolation and prevents crosstalk between modules; the overall power structure improves the system's stability and anti-interference capability in high-speed signal testing.

[0077] Specifically, the plurality of HDMI receiving interfaces include an HDMI-A interface, an HDMI-B interface, an HDMI-C interface, and an HDMI-D interface. Each HDMI receiving interface has three data paths for receiving differential signals from the signal source.

[0078] It should be further explained that the diversified design of the HDMI receiving interface enhances the system's compatibility and signal reception capabilities. Each of the HDMI-A, HDMI-B, HDMI-C, and HDMI-D interfaces is configured with three data paths (0, 1, and 2), employing TMDS (Transmission Differential Signal Minimization) to receive signals of different frequencies and refresh rates from a signal source (such as a 780E device). The interface physical layer matches the characteristic impedance of the transmission line through terminating resistors, reducing signal reflection. These interfaces are directly soldered onto the PCB board, and their arrangement facilitates connection to external signal sources. Furthermore, the data path of each interface is connected to the HDMI receiving module via differential pair cables.

[0079] Understandably, the multi-interface support for parallel signal testing improves testing efficiency; the three-data-path structure ensures signal integrity and is suitable for high-bandwidth applications; and the fixed layout of the hardware interfaces reduces the risk of connection errors.

[0080] Specifically, the HDMI receiving module is configured to receive three data path signals from the HDMI receiving interface and output separate dout_lane0, dout_lane1 and dout_lane2 channel data to the control module.

[0081] It should be further explained that the HDMI receiver module, as the core of signal analysis, uses a dedicated integrated circuit to split the signal. This module receives the TMDS differential signal from the 0, 1, and 2 data paths of the HDMI receiver interface and uses an internal clock data recovery circuit to extract three independent 20-bit channel data: dot_lane0, dot_lane1, and dot_lane2. The module is connected to the control module via a parallel data bus, resulting in a shorter transmission path and reduced signal latency. Physically, the HDMI receiver module is integrated on the PCB, close to the interface to minimize transmission loss.

[0082] Understandably, the channel separation design allows for independent testing and evaluation of each data path, improving fault diagnosis accuracy; hardware-level parsing avoids the uncertainties introduced by software processing, ensuring signal authenticity; and the fixed connection relationship of the modules optimizes signal flow, making it suitable for automated testing scenarios.

[0083] Specifically, the control module is connected to a main I2C interface and a slave I2C interface. The main I2C interface is connected to the automatic screen-pointing system for communication, and the slave I2C interface is connected to the peripheral EEPROM for reading configuration information.

[0084] It should be further explained that the control module implements system communication and configuration through a standard interface. The main I2C interface uses a two-wire system (SCL and SDA), directly connecting to the automatic screen-on system for transmitting control commands and status data, enabling automatic switching of signal sources. The secondary I2C interface connects to the peripheral EEPROM memory, automatically reading configuration information such as EDID from the EEPROM after system power-on. The physical connection of the interface is implemented through PCB traces, with fixed pin assignments (e.g., reg_rxb_scl_func_sel=1 and reg_rxb_sda_func_sel=1 settings).

[0085] Understandably, the hardware-based communication of the I2C interface ensures the reliability of data transmission and avoids the overhead of software protocols; the configuration storage of EEPROM enables the system to be plug-and-play, improving its usability; and the separate design of the interface (master-slave mode) optimizes the collaboration efficiency between system modules.

[0086] Specifically, the peripheral device also includes a FLASH memory, which is connected to the signal system via a QSPI interface and is used to store program information.

[0087] It should be further explained that the FLASH memory, as part of the peripheral device, is connected to the signal system via QSPI (Q4-Wire Serial Peripheral Interface). The QSPI interface includes clock, data, and chip select signals, and is physically fixed to the control module via a PCB connector. After the system powers on, it automatically reads program information from the FLASH to initialize the system's operating state. The memory is packaged as a surface mount device and installed in a reserved area on the PCB.

[0088] Understandably, the high-speed nature of the QSPI interface ensures fast program loading and improves system startup efficiency; hardware storage avoids repeated configuration for each test, enhancing system stability; and the modular design of peripherals facilitates maintenance and upgrades.

[0089] Specifically, the eARC transmitting module is used to send audio signals to audio equipment, the LVDS transmitting module is used to send video signals to the FPGA acquisition and analysis system through three LVDS channels, and the HDMI transmitting module is used to send video signals to a 4K display.

[0090] It should be further explained that the specialized design of the output modules enables multi-channel signal transmission. The eARC transmitting module receives the audio signal parsed by the control module and outputs it to the audio equipment through a dedicated audio channel; the LVDS transmitting module converts the data from the three channels dout_lane0, dout_lane1, and dout_lane2 into LVDS differential signals and transmits them to the FPGA acquisition and analysis system through three independent channels for channel-level quality testing; the HDMI transmitting module receives the complete video signal, parses it, and outputs it to the 4K display. The modules are connected via a data bus, and the LVDS channels use shielded cables to reduce interference.

[0091] Understandably, the hardware separation of the signal path ensures independent processing of audio and video, avoiding crosstalk; LVDS multi-channel supports parallel analysis, improving test coverage; and the direct drive capability of the transmitting module enhances the integrity of signal transmission.

[0092] Specifically, the LVDS transmission module is configured to transmit the data from the dou_lane0, dou_lane1, and dou_lane2 channels parsed by the control module through three independent LVDS channels to test the transmission quality of each channel.

[0093] It should be further noted that the independent channel design of the LVDS transmitter module improves test accuracy. The module contains three independent LVDS drivers, corresponding to the dout_lane0, dout_lane1, and dout_lane2 data channels respectively. Each channel uses differential pair transmission (positive and negative signal lines), physically led out to the FPGA system via connectors. The module's electrical characteristics are set in hardware via registers (such as reg_tx_phy3_res_diff and reg_tx_phy3_bias_db) to ensure impedance matching.

[0094] Understandably, independent channels allow for individual evaluation of each data path, facilitating the location of signal degradation points; the noise immunity of LVDS technology ensures the reliability of long-distance transmission; and the hardware configuration simplifies the testing process.

[0095] Specifically, the signal system also includes a PLL module and a BG module. The PLL module is connected to the HDMI receiving module and the transmitting module to provide a clock signal, and the BG module provides a reference voltage for the signal system.

[0096] It should be further explained that the integration of the clock and reference modules enhances system synchronization. The PLL (Phase-Locked Loop) module generates the clock signals required by the system, such as the master clock and LVDS transmit clock, which are connected to the HDMI receive and transmit modules via clock lines; the BG (Reference Voltage) module provides a stable reference for each level of the signal system, such as the AVDD33BG output reference voltage. The modules are packaged in integrated circuits and soldered onto the PCB, close to the load module to reduce voltage drop.

[0097] Understandably, the PLL's hardware clock synchronization ensures the accuracy of data sampling, making it particularly suitable for high-frequency signals; the BG module's reference voltage improves measurement consistency; and the fixed positional relationship of the modules optimizes system timing and enhances overall performance.

[0098] Furthermore, the solution of the present invention will be further described below. The HDMI testing system of the present invention specifically includes the following design: 1. The HDMI testing system consists of six parts: power system, signal source, signal system, receiving device, automatic screen detection system, and peripherals.

[0099] 2. The power system is divided into two levels of power modules.

[0100] ① The first level is the main power supply of the HDMI test system. To reduce energy loss, a DC-DC power supply (represented by TPS54302) is used to achieve an input power of 4.5~28V, an output of 5V (±2%), and a load capacity of 3A.

[0101] ② The second level is the power supply that is subdivided from 5V to each branch, which supplies power to each module of the HDMI test system.

[0102] (1) The first branch is an LDO (represented by LP3983SAB5F), which implements 5V input and 3.3V output, with a load capacity of 300mA, and can power the following modules: AVDD33BG: BG module, i.e., reference voltage module, with a power consumption requirement of 10mA; AVDD33RX: HDMI receiver module, power consumption requirement is 80mA; AVDD33EARC: eARC transmitter module, power consumption requirement is 33mA; AVDD33TX: LVDS transmitter module, power consumption requirement is 150mA; AVDD33HDMITX: HDMI transmitter module, power consumption requirement is 5mA; AVDDIO_LEFT: The left part of the control module, with a power consumption requirement of 5mA; AVDDIO_RIGHT: The right part of the control module, with a power consumption requirement of 5mA; VDD33: Peripherals, including FLASH and EEPROM, with a power consumption requirement of 10mA.

[0103] (2) The second branch is a DC-DC power supply (represented by JW5250S), which realizes 5V input and 0.9V output, with a load capacity of 1A, and can power the main module.

[0104] (3) The third branch is an LDO (represented by LP3983SAB5F), which implements 5V input and 0.9V output, with a load capacity of 300mA, and can power the following modules: AVDD09PLL: Master clock phase-locked loop module, power consumption requirement is 15mA; AVDD09TXPLL0: LVDS transmitter module clock phase-locked loop module, power consumption requirement is 5mA; AVDD09TXPLL1: HDMI transmitter module clock phase-locked loop module, power consumption requirement is 5mA; AVDD09RX: HDMI receiver module, power consumption requirement is 20mA; AVDD09TX: LVDS transmitter module, power consumption requirement is 15mA; AVDD09HDMITX: HDMI transmitter module, power consumption requirement is 10mA.

[0105] (4) The fourth branch is an LDO (represented by LP3983SAB5F), which implements 5V input and 1.8V output, with a load capacity of 300mA, and can power other peripherals.

[0106] 3. The signal source is mainly used to send signals of different frequencies and refresh rates to the signal system. A typical device is the 780E.

[0107] 4. The signal system includes four HDMI receiving interfaces: HDMI-A, HDMI-B, HDMI-C, and HDMI-D; an HDMI receiving module; a control module; an eARC transmitting module; an LVDS transmitting module; an HDMI transmitting module; a PLL module; an LDO module; a BG module; a master I2C interface; a slave I2C interface; and a QSPI interface, etc. Furthermore, the four HDMI receiver interfaces—HDMI-A, HDMI-B, HDMI-C, and HDMI-D—receive signals of various frequencies and refresh rates from the signal source and transmit them to the HDMI receiver module. Each interface has three data paths: 0, 1, and 2.

[0108] Furthermore, the HDMI receiver module separates the three data paths (0, 1, and 2) received from the HDMI interface, denoted as dout_lane0, dout_lane1, and dout_lane2, respectively, with each channel being 20 bits.

[0109] Furthermore, the control module processes the signal received by the HDMI receiving module, separates the audio signal, and sends it out through the eARC transmitting module to audio devices such as speakers.

[0110] Furthermore, the control module parses and converts the data from the three channels dou_lane0, dou_lane1, and dou_lane2 split from the HDMI receiving module, and sends them out through the LVDS transmitting module to the FPGA acquisition and analysis system for more comprehensive analysis and evaluation of the signal.

[0111] Furthermore, the control module does not split or extract the information received by the HDMI receiving module, but only parses and converts it before sending it out through the HDMI transmitting module to display devices such as 4K monitors, testing the integrity of signal transmission.

[0112] Furthermore, the eARC transmission module is a dedicated audio channel, and the transmission control module separates the audio information data from the video information data.

[0113] Furthermore, the LVDS transmitting module divides the three channels dout_lane0, dout_lane1, and dout_lane2 parsed by the control module into three LVDS channels and sends them to the FPGA acquisition and analysis system, which can test and evaluate the transmission quality of the three channels dout_lane0, dout_lane1, and dout_lane2 respectively.

[0114] Furthermore, the HDMI transmitting module receives the complete transmission signal parsed by the control module and sends it out to the display device to test the integrity of the signal transmission.

[0115] Furthermore, the PLL module is the clock module of the signal system, providing various clock signals required for the operation of the signal system, including the system master clock, the LVDS transmitter module clock, etc.

[0116] Furthermore, the BG module is the reference module of the signal system, providing reference voltages for various levels of the signal system to ensure the accuracy of measurement, control, and signal processing.

[0117] Furthermore, the LDO module provides the signal system with power at various required levels, with low noise, high stability, and load-level compatibility.

[0118] Furthermore, the main I2C interface connects to the automatic screen activation system, enabling communication between the signal system and the automatic screen activation system.

[0119] Furthermore, the peripheral EEPROM is connected via the I2C interface. After the system is powered on, the signal system automatically reads the configuration information (EDID, etc.) from the EEPROM via the I2C interface.

[0120] Furthermore, the QSPI interface connects to the peripheral FLASH, and after the system is powered on, the signal system automatically reads program information from the FLASH through the QSPI interface.

[0121] 5. Receiving equipment includes FPGA acquisition and analysis systems, audio and video receiving devices such as speakers and 4K displays.

[0122] 6. Peripherals mainly include EEPROM and FALSE.

[0123] 7. The automatic screen-pointing system enables the signal source to switch freely between signal frequency and refresh rate. The signal system can automatically identify the signal, analyze the received signal, and transmit it to the 4K display, so that the video and audio signals are displayed completely on the display.

[0124] Furthermore, the solution of the present invention will be further described below. The HDMI testing solution of the present invention specifically includes the following design: Step 1: Configure the common registers and disable the physical layer (PHY) driver for the HDMI receiver (RX): 1.1 Disable HDMI DDC (Display Data Channel) response, do not transmit EDID (Extended Display Identification Data), maintain MAC status monitoring, and set reg_rxb_scl_func_sel=1 and reg_rxb_sda_func_sel=1.

[0125] 1.2. Select the RXB path on the HDMI receiver and set reg_rx_phy_port_sel=portB and reg_rx_port_sel=BCD.

[0126] 1.3. Configure the independent channel lane used for data transmission within the HDMI interface to Power Down mode, using TMDS (Transmission Minimized Differential Signaling). This mode is triggered by detecting the voltage difference between the differential signal pairs. Enable the receiver's terminating resistor to match the characteristic impedance of the transmission line, reducing signal reflection and ensuring signal integrity. Turn on the power switch of the receiver's (RX) physical layer (PHY). Enable the receiver's (RX) physical layer (PHY) TMDS clock detection function to accurately synchronize the TMDS clock, ensuring the receiver can correctly lock onto the clock signal from the transmitter. Configure the receiver's (RX) physical layer (PHY) multiplexing mode (MUX Mode) to use bwset mode. In this mode, the PHY operates according to the configured bandwidth parameters. Enable the receiver's (RX) physical layer (PHY) bandwidth setting function and set the bandwidth value.

[0127] 1.4 Configure the physical layer (PHY) of the HDMI transmitter (TX), select the clock reference, select the division factor, conform to the 20-bit mode, turn on the power switch of the physical layer (PHY) of the transmitter (TX), and turn off the driver.

[0128] 1.5. Disable the Hot Plug Detect (HPD) function for the HDMI interface.

[0129] 2. Step 2: Set the independent channel lane used for data transmission inside the HDMI to Power down mode with a delay of 100ms (configurable) and enable the hot-plug detection function of the HDMI interface.

[0130] 3. Step 3: Delay for 50ms (configurable), monitor the TMDS port status flag regr_rx_phy_tmds_port_flag of the HDMI receiver (RX). If the status flag is 1, it means that an HDMI device is connected; if the status flag is 0, it means that no HDMI device is connected. Continue to loop and delay until the status flag is 1.

[0131] 4. Step 4: Read the value of the TMDS clock frequency register regr_rx_phy_tmds_clk_frq of the physical layer (PHY) of the HDMI receiver (RX), and use the formula: tmds_clock_freq = regr_rx_phy_tmds_clk_frq / 2048 27 …… (1) Calculate the TMDS clock frequency tmds_clock_freq of the physical layer (PHY) of the HDMI receiver (RX), in MHz.

[0132] Read the register value regr_rx_phy_tmds_clk_frq ten times to calculate ten TMDS clock frequencies tmds_clock_freq. If these ten TMDS clock frequencies tmds_clock_freq are all between 25MHz and 380MHz, it means that the TMDS clock frequency tmds_clock_freq is a valid clock frequency. If the difference between these ten TMDS clock frequencies tmds_clock_freq is within 1%, it means that the TMDS clock frequency tmds_clock_freq is stable, and then the TMDS clock frequency tmds_clock_freq is a valid frequency; otherwise, it is an invalid frequency.

[0133] If the TMDS clock frequency tmds_clock_freq is a valid frequency, proceed to step 5; otherwise, disable the hot-plug detection function of the HDMI interface and return to step 2 to continue execution.

[0134] 5. Step 5: Read the status parameters 5.1 Read the bit clock ratio used to configure the TMDS clock and data signal in the HDMI SCDC (State and Control Data Channel) protocol – regc_SCDC_TMDSBITCLKRATIO.

[0135] If regc_SCDC_TMDSBITCLKRATIO=0, let ratiao=1; If regc_SCDC_TMDSBITCLKRATIO=1, let ratiao=4; 5.2 Calculate the target clock frequency (lane_clock_freq_target) and data transfer rate (DataRate) of the HDMI transmission channel (lane) to ensure synchronization between the source and receiver, especially in high-resolution 4K / 8K transmission. The formula is as follows: lane_clock_freq_target = tmds_clock_freq ratiao …… (2) DataRate = lane_clock_freq_target 10 …… (3) 5.3 Configure the clock prescaler reg_rx_phy_cr_prediv of the physical layer (PHY) of the HDMI receiver (RX) according to the value of tmds_clock_freq. By adjusting the prescaler coefficient, ensure that the clock frequency of the HDMI receiver is synchronized with the source, especially in high-resolution 4K / 8K transmission. The details are as follows: tmds_clock_freq<100MHz: reg_rx_phy_cr_prediv=1; 100MHz≤tmds_clock_freq<200MHz: reg_rx_phy_cr_prediv=2; 200MHz≤tmds_clock_freq:reg_rx_phy_cr_prediv=4; 5.4 Configure the oversampling rate of the physical layer (PHY) of the HDMI receiver (RX) according to the DataRate value. By adjusting the oversampling rate reg_rx_phy_osr, the decoding accuracy of the HDMI receiver for TMDS signals is enhanced, especially in high-resolution 4K / 8K transmission. The details are as follows: 0.25Gbps≤DataRate<0.5Gbps: reg_rx_phy_osr=3; 0.5Gbps≤DataRate<1Gbps: reg_rx_phy_osr=2; 1Gbps≤DataRate<2Gbps: reg_rx_phy_osr=1; 2Gbps≤DataRate<6Gbps: reg_rx_phy_osr=0; 5.5. Assign the value of reg_rx_phy_osr to the variable osr_ratiao, with the following content: Set reg_rx_phy_osr=3, and set osr_ratiao=0.5; Set reg_rx_phy_osr=2, and set osr_ratiao=1; Set reg_rx_phy_osr=1, and set osr_ratiao=2; Set reg_rx_phy_osr=0, and set osr_ratiao=4; 5.6 Configure the register reg_rx_phy_cr_fbdiv of the physical layer (PHY) feedback divider of the HDMI receiver (RX) to adjust the division ratio of the internal clock feedback path of the receiver, ensuring clock synchronization and data recovery stability. The formula is as follows: reg_rx_phy_cr_fbdiv = reg_rx_phy_cr_prediv ratiao 10 / osr_ratiao…… (4) 5.7 Configure the prescaler coefficient reg_tx_pll1_prediv of the phase-locked loop (PLL) of the HDMI transmitter (TX) according to the target clock frequency lane_clock_freq_target. This determines the division ratio between the PLL reference clock and the output clock, ensuring that the clock generated by the PLL for high-speed serial data transmission meets the requirements of the HDMI specification. The details are as follows: 25MHz≤lane_clock_freq_target<50MHz: reg_tx_pll1_prediv=1; 50MHz≤lane_clock_freq_target<100MHz: reg_tx_pll1_prediv=2; 100MHz≤lane_clock_freq_target<200MHz: reg_tx_pll1_prediv=4; 200MHz≤lane_clock_freq_target<400MHz: reg_tx_pll1_prediv=8; 400MHz≤lane_clock_freq_target<600MHz: reg_tx_pll1_prediv=16; 5.8. Configure the feedback division coefficient reg_tx_pll1_sscg_plln of the phase-locked loop (PLL) of the HDMI transmitter (TX) according to the DataRate value to precisely control the PLL output frequency, thereby meeting the transmission requirements of HDMI at different resolutions (4K / 8K) and refresh rates (60Hz). The details are as follows: 250MHz≤DataRate<4GHz: reg_tx_pll1_sscg_plln=40; 4GHz≤DataRate<6GHz: reg_tx_pll1_sscg_plln=80; 5.9 Configure the register reg_tx_pll1_postdiv0 for the post-division factor of the phase-locked loop (PLL) of the HDMI transmitter (TX). This register determines the division ratio between the PLL output clock and the core clock provided to the HDMI transmitter, ensuring that the clock required for high-speed serial data transmission generated by the PLL meets the requirements of the HDMI specification. The formula is as follows: reg_tx_pll1_postdiv0=reg_tx_pll1_sscg_plln / reg_rx_phy_cr_prediv / 5…… (5) 5.10. According to ratiao, configure the physical layer (PHY) of the HDMI transmitter (TX) to control the differential signal register reg_tx_phy3_res_diff and the bias register reg_tx_phy3_bias_db, in order to manage the electrical characteristics of the differential signal and ensure signal integrity during high-speed transmission. The details are as follows: ratiao=1, let reg_tx_phy3_res_diff=0, reg_tx_phy3_bias_db=0; ratiao=4, let reg_tx_phy3_res_diff=10, reg_tx_phy3_bias_db=1; 5.11 Simultaneously release the reset signals of all four data lanes (lanes) of the physical layer (PHY) of the HDMI receiver (RX), and the PHY will start working normally after a delay of 100ms.

[0136] Step 6: Read the register values ​​regr_rx_phy_lane_clk_frq_0, regr_rx_phy_lane_clk_frq_1, and regr_rx_phy_lane_clk_frq_2 of the target clock frequencies for the 0th, 1st, and 2nd data channels of the HDMI receiver (RX) physical layer (PHY). Calculate the target clock frequency values ​​lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real for the 0th, 1st, and 2nd data channels of the HDMI receiver (RX) physical layer (PHY) using the following formula: lane0_clock_freq_real = regr_rx_phy_lane_clk_frq_0 / 2048 27 ……(6) lane1_clock_freq_real = regr_rx_phy_lane_clk_frq_1 / 2048 27 ……(7) lane2_clock_freq_real = regr_rx_phy_lane_clk_frq_2 / 2048 27 ……(8) Read the register values ​​regr_rx_phy_lane_clk_frq_0, regr_rx_phy_lane_clk_frq_1, and regr_rx_phy_lane_clk_frq_2 ten times to calculate the target clock frequency values ​​lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real for the 0th, 1st, and 2nd data channels of the physical layer (PHY) of the ten HDMI receivers (RX). If the target clock frequency values ​​lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real of the channels differ from lane_clock_freq_target by less than 1%, it indicates that the target clock frequency values ​​lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real of the physical layer (PHY) of the HDMI receiver (RX) are stable and effective. Then proceed to step 7; otherwise, return to step 2.

[0137] Step 7: Clear the buffered data in the physical layer (PHY) of the HDMI transmitter (TX) to prevent incorrect data from being saved in the buffer due to clock mismatch during the intermediate process. This is done by first setting the register reg_tx_phy_bypass_clr to 1 and then to 0. The physical layer (PHY) driver of the HDMI transmitter (TX) is then enabled, and the PHY begins to work normally.

[0138] Step 8: After a 100ms delay, read the register values ​​regr_rx_phy_lane_clk_frq_0, regr_rx_phy_lane_clk_frq_1, and regr_rx_phy_lane_clk_frq_2 of the target clock frequencies for the 0th, 1st, and 2nd data channels of the physical layer (PHY) of the HDMI receiver (RX). Calculate the target clock frequency values ​​lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real for the 0th, 1st, and 2nd data channels of the physical layer (PHY) of the HDMI receiver (RX) using formulas (6), (7), and (8). Read the register values ​​regr_rx_phy_lane_clk_frq_0, regr_rx_phy_lane_clk_frq_1, and regr_rx_phy_lane_clk_frq_2 ten times to calculate ten sets of HDMI receiver (RX) values. If the target clock frequency values ​​(lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real) of the 0th, 1st, and 2nd data channels of the physical layer (PHY) of the ten HDMI receivers (RX) are all within 1% of lane_clock_freq_target, it indicates that the target clock frequency values ​​(lane0_clock_freq_real, lane1_clock_freq_real, and lane2_clock_freq_real) of the 0th, 1st, and 2nd data channels of the physical layer (PHY) of the HDMI receivers (RX) are stable and effective, then step 8 is executed repeatedly; otherwise, step 2 is returned.

[0139] In a preferred embodiment, this application also provides an electronic device, the electronic device comprising: The computer device includes a memory and a processor, wherein the memory stores computer-readable instructions that, when executed by the processor, implement the HDMI automatic screen-pointing test method. The computer device can be broadly categorized as a server, terminal, or any other electronic device with the necessary computing and / or processing capabilities. In one embodiment, the computer device may include a processor, memory, network interface, communication interface, etc., connected via a system bus. The processor of the computer device can be used to provide the necessary computing, processing, and / or control capabilities. The memory of the computer device may include a non-volatile storage medium and internal memory. The non-volatile storage medium may store an operating system, computer programs, etc. The internal memory can provide an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface and communication interface of the computer device can be used to connect and communicate with external devices via a network. When the computer program is executed by the processor, it performs the steps of the method of the present invention.

[0140] This invention can be implemented as a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, causes the steps of the methods of embodiments of the invention to be performed. In one embodiment, the computer program is distributed across multiple network-coupled computer devices or processors, such that the computer program is stored, accessed, and executed in a distributed manner by one or more computer devices or processors. A single method step / operation, or two or more method steps / operations, may be executed by a single computer device or processor or by two or more computer devices or processors. One or more method steps / operations may be executed by one or more computer devices or processors, and one or more other method steps / operations may be executed by one or more other computer devices or processors. One or more computer devices or processors may execute a single method step / operation, or execute two or more method steps / operations.

[0141] Those skilled in the art will understand that the method steps of this invention can be performed by a computer program instructing related hardware, such as a computer device or processor, to perform the steps of this invention when executed. Depending on the context, any references herein to memory, storage, databases, or other media may include non-volatile and / or volatile memory. Examples of non-volatile memory include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, etc. Examples of volatile memory include random access memory (RAM), external cache memory, etc.

[0142] The technical features described above can be combined arbitrarily. Although not all possible combinations of these technical features are described, any combination of these technical features should be considered to be covered by this specification, provided that such combination does not contain contradictions.

[0143] The specific embodiments of the present invention described above do not constitute a limitation on the scope of protection of the present invention. Any other corresponding changes and modifications made in accordance with the technical concept of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. An HDMI automatic screen tapping test method, characterized in that, Includes the following steps: S100, Initial state of configuring the HDMI test system; S200: Detect whether there is a signal input at the HDMI receiver; S300. When a signal input is detected, calculate the TMDS clock frequency; S400. Automatically configure the parameters of the HDMI system based on the TMDS clock frequency; S500 verifies the clock frequency stability of the HDMI data channel.

2. The HDMI automatic screen testing method according to claim 1, characterized in that, The initial state of configuring the HDMI test system includes: Disable the physical layer driver on the HDMI receiver and set the HDMI data channel to power deceleration mode.

3. The HDMI automatic screen tapping test method according to claim 2, characterized in that, Setting the HDMI data channel to power-down mode includes: The power descent mode is triggered by detecting the voltage difference of the TMDS differential signal, and the receiver termination resistor is enabled to match the transmission line impedance.

4. The HDMI automatic screen tapping test method according to claim 1, characterized in that, The detection of whether the HDMI receiver has a signal input includes: Monitor the TMDS port status flag of the HDMI receiver and determine that there is a signal input when the status flag is detected to be valid.

5. The HDMI automatic screen tapping test method according to claim 4, characterized in that, The monitoring TMDS port status flags include: enabling hot-plug detection function and delaying the status flag change, wherein the delay time is configurable.

6. The HDMI automatic screen tapping test method according to claim 1, characterized in that, The calculation of the TMDS clock frequency includes: The physical layer register value of the HDMI receiver is read, and the frequency value is calculated based on a predetermined formula, wherein the calculation includes multiple reads to verify frequency stability.

7. The HDMI automatic screen tapping test method according to claim 6, characterized in that, The parameters for automatically configuring the HDMI system include: Based on the TMDS clock frequency, configure the divider coefficients, oversampling rate, and phase-locked loop parameters to synchronize the clock signal.

8. The HDMI automatic screen tapping test method according to claim 1, characterized in that, The verification of the clock frequency stability of the HDMI data channel includes: The clock frequency value of the data channel is read multiple times and compared with the target frequency. When the frequency deviation is within the predetermined range, it is determined to be stable.

9. The HDMI automatic screen tapping test method according to claim 8, characterized in that, Once the frequency is verified to be stable, the verification steps are repeated cyclically to continuously monitor signal integrity.

10. An HDMI automatic screen testing system, characterized in that, include: A power supply system used to provide a stable voltage supply through multi-stage power modules; The signal system includes multiple HDMI receiving interfaces, an HDMI receiving module, a control module, an eARC transmitting module, an LVDS transmitting module, and an HDMI transmitting module, wherein the control module is configured to process signals and transmit them in a directional manner; The automatic screen activation system communicates with the control module via the main I2C interface to automatically execute signal detection and configuration processes. Peripheral interfaces, including I2C and QSPI interfaces, are used to connect to external memory.

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