Undoped tunneling junction line tunneling field effect transistor and preparation method thereof

Abstract

The invention discloses an undoped tunneling junction line tunneling field effect transistor and a preparation method thereof. The line tunneling field effect transistor comprises a substrate, a drain electrode, an N + Si layer, SiO2 isolation, intrinsic Si, an L-shaped metal structure, intrinsic Ge, a grid electrode, a first oxide layer and a second oxide layer, stacking drain electrodes on the two sides of the N + Si layer on the substrate; intrinsic Si is stacked on the N + Si layer, and SiO2 isolation is stacked on the two sides of the intrinsic Si; intrinsic Ge is stacked on the two sides of the upper portion of the intrinsic Si, and a grid electrode is arranged between the intrinsic Ge; a second oxide layer covers the upper part of the SiO2 isolator and the outer side of the intrinsic Ge; high-work-function metal is stacked on the outer side of the second oxide layer and above the intrinsic Ge to form an L-shaped metal structure; a source electrode is formed above the intrinsic Ge, and a back gate is formed on the outer side of the second oxide layer. According to the invention, the line tunnel junction is formed on the intrinsic Ge, so that the on-state current of the transistor is improved, the sub-threshold swing is reduced, and the switching performance is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of microelectronic devices, and in particular relates to an undoped tunneling junction tunneling field effect transistor and a preparation method thereof. Background Art

[0002] As MOSFETs shrink, the switching speed, high-frequency performance, density, cost, and functionality of integrated circuits have been greatly improved. However, as the voltage of integrated circuits continues to shrink, high power consumption has become a serious problem in modern integrated circuits.

[0003] Unlike traditional MOSFET devices, TFET (tunneling field-effect transistor) devices mainly rely on the band-to-band tunneling mechanism for current conduction, overcoming the limitations of thermal electron emission, having lower off-state leakage current, and being able to achieve a subthreshold swing of less than 60mV / decade, with faster switching speeds. However, the source and drain regions of traditional TFET devices are obtained through a heavy doping process, resulting in the preparation of transistors that will cause doping volatility and high thermal budget. In addition, traditional silicon-based TFETs have a small on-state current due to the point tunneling mechanism and the high bandgap width, which seriously limits the application of TFET devices.

[0004] Therefore, there is an urgent need for a TFET device with a lower subthreshold swing, a larger on-state current, and the ability to overcome the effects of the heavy doping process. Summary of the Invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides an undoped tunneling junction tunneling field effect transistor and a preparation method thereof.

[0006] The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0007] An undoped tunneling junction tunneling field effect transistor comprises: a substrate, a drain, an N+Si layer, SiO2 isolation, intrinsic Si, an L-shaped metal structure, intrinsic Ge, a gate, a first oxide layer and a second oxide layer;

[0008] The N+Si layer is stacked on the substrate, and the drain is stacked on both sides of the N+Si layer; the intrinsic Si is stacked in the middle of the upper part of the N+Si layer, and the SiO2 is stacked on both sides of the intrinsic Si for isolation; the intrinsic Ge is stacked on both sides of the upper part of the intrinsic Si, and the gate is provided between the intrinsic Ge on both sides, and the gate and the intrinsic Ge and the intrinsic Si are all separated by the first oxide layer;

[0009] The second oxide layer is covered above the SiO2 isolation and outside the intrinsic Ge; a high work function metal is stacked on the outside of the second oxide layer and above the intrinsic Ge to form the L-shaped metal structure; the high work function metal stacked above the intrinsic Ge forms a source, and the high work function metal stacked on the outside of the second oxide layer forms a back gate.

[0010] Optionally, the doping concentration of the N+Si layer is 1×10 19 / cm 3 ~1×10 21 / cm 3 , with a thickness of 10nm to 20nm.

[0011] Optionally, the intrinsic Ge is unintentionally doped Ge, and its intrinsic carrier concentration is 1×10 15 / cm 3 ~1×10 17 / cm 3 , its thickness is 30nm~45nm.

[0012] Optionally, the intrinsic Si is unintentionally doped Si, and its intrinsic carrier concentration is 1×10 15 / cm 3 -1×10 17 / cm 3 , and its thickness is 15nm~45nm.

[0013] Optionally, the first oxide layer and the second oxide layer are both HfO2 oxide layers, and their thickness is 2nm to 3nm.

[0014] Optionally, the gate is made of metal aluminum.

[0015] Optionally, the high work function metal includes platinum.

[0016] The present invention also provides a method for preparing an undoped tunneling junction tunneling field effect transistor, comprising:

[0017] Step 1: growing an N+Si layer on a substrate and depositing drain electrodes on both sides of the N+Si layer;

[0018] Step 2: growing intrinsic Si on the N+Si layer, etching both sides of the intrinsic Si to form an isolation region, and depositing SiO2 isolation in the isolation region;

[0019] Step 3: growing intrinsic Ge on the intrinsic Si, and etching the middle of the intrinsic Ge to form a gate groove to expose the intrinsic Si underneath;

[0020] Step 4: Deposit a layer of oxide on the surface of the current sample;

[0021] Step 5: depositing a gate in the gate groove, removing the oxide above the intrinsic Ge and the oxide above the gate in the gate groove; wherein the remaining oxide in the gate groove constitutes a first oxide layer, and the oxide above the SiO2 isolation and outside the intrinsic Ge constitutes a second oxide layer;

[0022] Step 6: Depositing a high work function metal on the outside of the second oxide layer and on the intrinsic Ge to form an L-shaped metal structure; wherein the high work function metal deposited on the intrinsic Ge forms a source, and the high work function metal deposited on the outside of the second oxide layer forms a back gate;

[0023] Step 7: Photolithography is performed to form electrode windows on the drain, source, and gate electrodes, thereby completing the lead-out of the drain, source, and gate electrodes and completing device preparation.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] The undoped tunneling junction wire tunneling field-effect transistor of the present invention has a dual-source structure, and uses germanium material to prepare the tunneling region. When the gate is energized, the gate electric field is used to induce an N+ electron region in the intrinsic Ge near the first oxide layer to form a wire tunneling junction. When the source is energized, the source electric field is used to induce a P+ Ge source region in the intrinsic Ge below, and the back gate is used to induce a P+ hole region in the intrinsic Ge near the second oxide layer to form a wire tunneling junction. Therefore, by introducing a dual-source structure and a wire tunneling junction, the present invention improves the tunneling probability and tunneling area, enhances the tunneling current, thereby increasing the on-state current of the transistor, reducing the subthreshold swing, and thus improving the switching performance of the circuit. In addition, the present invention effectively overcomes the effects of doping volatility and high thermal budget caused by the heavy doping process of traditional TFET devices through electron doping.

[0026] The present invention will be further described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 1 is a schematic structural diagram of an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0028] Figures 2 and 3 This is a diagram showing the effect of executing step 1 in a method for preparing an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0029] Figures 4 to 6 This is a diagram showing the effect of executing step 2 in a method for preparing an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0030] Figures 7 and 8This is a diagram showing the effect of executing step 3 in a method for preparing an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0031] Figure 9 This is a diagram showing the effect of executing step 4 in a method for preparing an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0032] Figures 10 and 11 This is a diagram showing the effect of executing step 5 in a method for preparing an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0033] Figure 12 This is a diagram showing the effect of executing step 6 in a method for preparing an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0034] Figure 13 This is a diagram showing the effect of executing step 7 in a method for preparing an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0035] Figure 14 is a transfer curve diagram of an undoped tunneling junction tunneling field effect transistor provided by an embodiment of the present invention;

[0036] Reference numerals:

[0037] 1. Substrate; 2. N+Si layer; 3. Drain; 4. Intrinsic Si; 5. SiO2 isolation; 6. Gate; 7. Intrinsic Ge; 8. L-shaped metal structure; 9. First oxide layer; 10. Second oxide layer; 11. Back gate; 12. Source. DETAILED DESCRIPTION

[0038] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the following is a detailed description of an undoped tunneling junction tunneling field effect transistor and a preparation method thereof proposed by the present invention in combination with the accompanying drawings and specific embodiments.

[0039] The aforementioned and other technical contents, features, and effects of the present invention are clearly presented in the following detailed description of the specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a deeper and more specific understanding of the technical means and effects adopted by the present invention to achieve the intended purpose can be obtained. However, the accompanying drawings are provided for reference and illustration purposes only and are not intended to limit the technical solutions of the present invention.

[0040] The undoped tunneling junction tunneling field effect transistor provided by the embodiment of the present invention is shown in FIG. Figure 1, including: substrate 1, N+Si layer 2, drain 3, intrinsic Si 4, SiO2 isolation 5, gate 6, intrinsic Ge 7, L-shaped metal structure 8, first oxide layer 9 and second oxide layer 10;

[0041] An N+Si layer 2 is stacked on a substrate 1, with drain electrodes 3 stacked on both sides of the N+Si layer 2. An intrinsic Si layer 4 is stacked above the middle of the N+Si layer 2, and SiO2 isolation layers 5 are stacked on both sides of the intrinsic Si layer 4 to suppress off-state leakage current.

[0042] Intrinsic Ge 7 is stacked on both sides of the intrinsic Si 4, with a gate 6 disposed between the intrinsic Ge 7 on both sides. A first oxide layer 9 is disposed between the gate 6, the intrinsic Ge 7, and the intrinsic Si 4. A second oxide layer 10 covers the top of the SiO2 isolation 5 and the outside of the intrinsic Ge 7. A high-work function metal is stacked on the outside of the second oxide layer 10 and on the top of the intrinsic Ge 7 to form an L-shaped metal structure 8. The high-work function metal stacked on the intrinsic Ge 7 forms a source 12, and the high-work function metal stacked on the outside of the second oxide layer 10 forms a back gate 11.

[0043] In an optional implementation, the substrate 1 may be a silicon dioxide substrate. Of course, the material of the substrate 1 is not limited thereto in practice. For example, the substrate 1 may also be a SiC substrate.

[0044] In an optional implementation, the impurity doped in the N+Si layer 2 may be As, wherein when As is used, the doping concentration is 1×10 19 / cm 3 ~1×10 21 / cm 3 The thickness of the N+Si layer 2 is preferably 10 nm to 20 nm. Alternatively, the impurity doped into the N+Si layer 2 may be phosphorus.

[0045] In an optional implementation, the gate 6 is preferably made of metal aluminum or copper, etc., wherein when it is metal aluminum, the thickness of the gate 6 is preferably 20nm to 30nm, and the drain 3 is preferably made of metal hafnium or metal copper, etc.

[0046] In an optional implementation, the intrinsic Si 4 is unintentionally doped Si with an intrinsic carrier concentration of 1×10 15 / cm 3 ~1×10 17 / cm 3 , and its thickness is preferably 15nm to 45nm.

[0047] In the present invention, the thickness of the SiO2 isolation 5 is the same as the thickness of the intrinsic Si 4.

[0048] In an optional implementation, the intrinsic Ge 7 is unintentionally doped Ge with an intrinsic carrier concentration of 1×10 15 / cm 3 ~1×10 17 / cm 3 The thickness is preferably 30 nm to 45 nm. Compared with silicon, germanium has a smaller band gap, which can effectively increase the tunneling probability and the tunneling current.

[0049] In an optional implementation, the high work function metal may be platinum, gold, nickel, etc., that is, the material of the L-shaped metal structure 8 may be platinum, gold, nickel, etc.

[0050] Specifically, the portion of the L-shaped metal structure 8 stacked above the intrinsic Ge 7 forms the source 12 , and the portion of the L-shaped metal structure 8 stacked outside the second oxide layer 10 forms the back gate 11 .

[0051] Thus, when the source electrode 12 is powered, a P+ Ge source region is induced in the intrinsic Ge 7 beneath it. When the source electrode 12 is powered, the back gate 11 is also powered, and the back gate 11 induces a P+ hole region in the intrinsic Ge 7 near the second oxide layer 10, forming a line tunneling junction. When the gate 6 is powered, an N+ electron region is induced in the intrinsic Ge 7 near the first oxide layer 9, forming a line tunneling junction. Thus, by generating line tunneling within the intrinsic Ge 7, the present invention not only increases the tunneling area but also enhances the tunneling current.

[0052] It can be understood that when a P+Ge source region is induced in the intrinsic Ge 7, the intrinsic Ge region therebelow becomes a Ge channel.

[0053] In an optional implementation, the first oxide layer 9 and the second oxide layer 10 may both be HfO 2 oxide layers or Al 2 O 3 oxide layers, wherein when they are HfO 2 oxide layers, their thickness is preferably 2 nm to 3 nm.

[0054] It is understandable that the HfO2 dielectric layer is a high dielectric constant material, which can increase the capacitance of the oxide layer and enhance the voltage resistance of the device.

[0055] The undoped tunneling junction tunneling field effect transistor provided by the present invention is further described below through simulation experiments.

[0056] During simulation, the material and size parameters of the device are set as follows:

[0057] The substrate of the device used in the simulation is a silicon dioxide substrate; the width of the N+Si layer is 74 nm, the thickness is 20 nm, and the doping impurity is As, where the doping concentration of As is 1×10 20 / cm 3The drain is made of hafnium. Intrinsic Si is unintentionally doped Si, and its intrinsic carrier concentration is 1×10 15 / cm 3 ~1×10 17 / cm 3 , with a width of 54nm and a thickness of 25nm; the width of the SiO2 isolation is 10nm, and its thickness is the same as that of the intrinsic Si; the gate is made of metallic aluminum, with a width of 36nm and a thickness of 20nm; the intrinsic Ge is unintentionally doped Ge, and its intrinsic carrier concentration is 1×10 15 / cm 3 ~1×10 17 / cm 3 , its width is 7nm and its thickness is 30nm; the material of the L-shaped metal structure is platinum; the first oxide layer and the second oxide layer are both HfO2 oxide layers with a thickness of 2nm.

[0058] See also Figure 14 As shown, Figure 14 The simulation results of the transfer characteristics of the undoped tunneling junction tunneling field-effect transistor of the present invention are given under the condition of a drain voltage of 1 V. The horizontal axis is the gate voltage, the vertical axis is the drain current, the solid line in the figure represents the on-state current, and the dashed line represents the off-state current.

[0059] Depend on Figure 14 It can be seen that the undoped tunneling junction tunneling field-effect transistor proposed in the present invention has a high on-state current and a low off-state current, and the average subthreshold swing is only 24mV / decade, which has a low subthreshold swing, thereby effectively improving the switching characteristics of the device. In addition, the threshold voltage of the undoped tunneling junction tunneling field-effect transistor proposed in the present invention is lower than 0.5V, which enables the device of the present invention to have a large voltage operating range in digital circuits. Therefore, the undoped tunneling junction tunneling field-effect transistor proposed in the present invention has broad application prospects in the field of low-power integrated circuits.

[0060] The undoped tunneling junction wire tunneling field-effect transistor of the present invention has a dual-source structure, and uses germanium material to prepare the tunneling region. When the gate is energized, the gate electric field is used to induce an N+ electron region in the intrinsic Ge near the first oxide layer to form a wire tunneling junction. When the source is energized, the source electric field is used to induce a P+ Ge source region in the intrinsic Ge below, and the back gate is used to induce a P+ hole region in the intrinsic Ge near the second oxide layer to form a wire tunneling junction. Therefore, the present invention improves the tunneling probability and tunneling area through the dual-source structure and wire tunneling junction, enhances the tunneling current, thereby increasing the on-state current of the transistor, reducing the subthreshold swing, and thus improving the switching performance of the circuit. In addition, the present invention effectively overcomes the effects of doping volatility and high thermal budget caused by the heavy doping process of traditional TFET devices through electron doping.

[0061] Based on the same inventive concept as the above-mentioned undoped tunneling junction tunneling field effect transistor, the embodiment of the present invention also provides a preparation method thereof, see Figure 2-13 , the preparation method comprises the following steps:

[0062] Step 1: Grow an N+Si layer on the substrate and deposit drain electrodes on both sides of the N+Si layer.

[0063] For example, see Figure 2 , the silicon dioxide substrate 1 is placed in the molecular beam epitaxy equipment, and the pressure is set to 760mT, the temperature is 700℃, and the protective gas He is introduced. Then, SiH4 gas is introduced into the equipment to grow a layer with a thickness of 20nm and a doping concentration of 1×10 20 / cm 3 After the growth of the N+Si layer 2 is completed, the temperature is densely cooled in the equipment for 1 hour.

[0064] Then, see Figure 3 Atomic layer deposition (ALD) is used to deposit drain electrodes 3 on both sides of the N+Si layer 2. The precursor is hafnium tetradimethylamine (TDMAH), and the reducing gas is high-purity H2. Ar gas is used as a carrier gas to introduce the precursor and reducing gas into the reaction chamber, while the oxide is removed. The reaction chamber temperature is set at 250°C, and hafnium metal drain electrodes 3 are deposited on both sides of the N+Si layer 2.

[0065] Step 2: Grow intrinsic Si on top of the N+Si layer, etch both sides of the intrinsic Si to form an isolation region, and deposit SiO2 isolation in the isolation region.

[0066] For example, the current sample obtained in step 1 is placed in a molecular beam epitaxy device, the pressure is set to 760mT, the temperature is set to 700°C, and the protective gas He gas is introduced. SiH4 is introduced into the device to grow a layer of intrinsic Si with a thickness of 25nm on the N+Si layer 2. Figure 4 After the intrinsic Si growth is completed, the temperature is densely cooled in the equipment for 1 hour.

[0067] Next, a photoresist is applied on top of the intrinsic Si and exposed and developed. The isolation regions are defined on both sides of the intrinsic Si upper surface using a photolithography process. The current sample after photolithography development is then fed into a plasma etcher, with the pressure set to 10mT and the power to 20W. 50sccm of Cl2 and 20sccm of O2 are input into the etching chamber to perform reactive ion etching on the isolation regions, thereby forming isolation regions on both sides of the intrinsic Si, as shown in FIG. Figure 5 shown.

[0068] Then, use a stripping solution to perform organic cleaning on the current sample to remove the residual photoresist. Using a chemical vapor deposition process at 200 ° C, SiH4 and O2 are introduced into the reaction chamber to deposit SiO2 isolation 5 with a thickness consistent with that of intrinsic Si 4 in the isolation area on both sides, as shown in FIG. Figure 6 shown.

[0069] Step 3: Grow intrinsic Ge on the intrinsic Si, and etch the middle of the intrinsic Ge to form a gate groove to expose the intrinsic Si underneath.

[0070] For example, see Figure 7 The sample was placed in a molecular beam epitaxy (MBE) apparatus, set at a pressure of 760 mT and a temperature of 700°C, with He and GeH₄ gas introduced as protective gases. A 30nm thick layer of intrinsic Geₐ₇ was grown on the intrinsic Si₄₄. After the intrinsic Geₐ₇ growth was complete, the apparatus was cooled for 1 hour.

[0071] Then, see Figure 8 , apply photoresist on the upper surface of intrinsic Ge 7 and perform exposure and development, and use photolithography to define a groove area in the middle of the upper surface of intrinsic Ge 7. The current sample after photolithography and development is sent to a plasma etcher, and the pressure is set to 10mT and the power is set to 20W. By inputting 50sccm of Cl2 and 20sccm of O2 into the etching chamber, the groove area is subjected to reactive ion etching to expose the intrinsic Si 4 underneath to form a gate groove. At the same time, a certain width of intrinsic Ge 7 is retained on both sides of the gate groove. The retained intrinsic Ge 7 is used to form a P+Ge source region and a Ge channel. For example, intrinsic Ge with a width of 7nm can be retained on both sides of the gate groove.

[0072] Step 4: Deposit a layer of oxide on the surface of the current sample.

[0073] For example, see Figure 9 A layer of HfO2 was deposited using atomic layer deposition. HfCl4 and O3 were used as precursors, and nitrogen was used as a carrier gas to introduce the precursors into the reaction chamber. Residual reaction gases were removed, and the reaction chamber temperature was set at 250°C to grow a 2nm thick HfO2 oxide film.

[0074] Step 5: Deposit a gate in the gate groove, remove the oxide above the intrinsic Ge and the oxide above the gate in the gate groove; wherein the remaining oxide in the gate groove constitutes a first oxide layer, and the oxide above the SiO2 isolation and covering the outside of the intrinsic Ge constitutes a second oxide layer.

[0075] For example, see Figure 10 As shown, a chemical vapor deposition process is used at 200° C., AlCl 3 and H 2 are introduced into the reaction chamber, and a metal aluminum gate 6 with a thickness of 20 nm is deposited in the gate groove area.

[0076] Then, see Figure 11 The sample was placed in a plasma etcher at a pressure of 10 mT and a power of 20 W. Reactive ion etching (RIE) was performed by introducing 50 sccm of Cl₂ and 20 sccm of O₂ into the etching chamber to remove the HfO₂ film above the intrinsic Ge₁₂ layer 7 and the HfO₂ film above the gate 6 in the gate groove. The remaining HfO₂ film in the gate groove now constituted a first oxide layer 9, while the HfO₂ film above the SiO₂ spacer 5 and covering the outside of the intrinsic Ge₁₂ layer 7 constituted a second oxide layer 10.

[0077] Step 6: Deposit a high work function metal on the outside of the second oxide layer and above the intrinsic Ge to form an L-shaped metal structure; wherein the high work function metal deposited above the intrinsic Ge forms a source, and the high work function metal deposited on the outside of the second oxide layer forms a back gate.

[0078] For example, see Figure 12 Using a chemical vapor deposition process at 300°C, platinum hexafluoroacetylacetonate was introduced into the reaction chamber as a precursor, and H2 was introduced as a reducing gas. Platinum metal was deposited on the outside of the second oxide layer 10 and above the intrinsic Ge 7 to form an L-shaped metal structure 8. The platinum metal deposited above the intrinsic Ge 7 formed the source 12, and the platinum metal deposited on the outside of the second oxide layer 10 formed the back gate 11.

[0079] Step 7: Photolithography is performed to form electrode windows at the drain, source, and gate electrodes, completing the lead-out of the drain, source, and gate electrodes and completing device preparation.

[0080] For example, see Figure 13 Using a chemical vapor deposition process at 200°C, SiH4 and O2 are introduced into the reaction chamber to deposit silicon dioxide, thereby providing cover and isolation protection for the device. Next, electrode windows for the drain, source, and gate electrodes are photolithographically created above the drain, source, and gate electrodes, respectively. Metal Al lead electrodes are deposited using a chemical vapor deposition process at 200°C. Finally, the remaining stripping solution is removed using ethanol and acetone, completing the fabrication of the undoped tunneling junction tunneling field-effect transistor.

[0081] The present invention uses germanium material to prepare the tunneling region. The undoped tunneling junction line tunneling field-effect transistor prepared by this method has a dual-source structure. When the gate is powered on, the gate electric field is used to induce an N+ electron region in the intrinsic Ge near the first oxide layer to form a line tunneling junction. When the source is powered on, the source electric field is used to induce a P+ Ge source region in the intrinsic Ge below, and the back gate is used to induce a P+ hole region in the intrinsic Ge near the second oxide layer to form a line tunneling junction. Therefore, through the dual-source structure and line tunneling junction, the tunneling probability and tunneling area are improved, the tunneling current is enhanced, thereby increasing the on-state current of the transistor, reducing the subthreshold swing, and thus improving the switching performance of the circuit. In addition, the present invention effectively overcomes the effects of doping volatility and high thermal budget caused by the heavy doping process of traditional TFET devices through electron doping.

[0082] In the description of the present invention, the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like to indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore should not be understood as limiting the present invention.

[0083] In the description of the present invention, unless otherwise expressly specified or limited, terms such as "mounted," "connected," "connect," and "fixed" should be understood in a broad sense. For example, they may refer to fixed or detachable connections, or integration; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0084] In the description of the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Moreover, a first feature being "above," "above," and "above" a second feature includes the first feature being directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature includes the first feature being directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0085] It should be noted that the terms "first," "second," and the like are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Instead, they are merely examples of devices and methods consistent with some aspects of the present invention.

[0086] In the description of this specification, the reference terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" mean that the specific features or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features or characteristics described can be combined in any suitable manner in any one or more embodiments or examples. In addition, those skilled in the art can combine and combine different embodiments or examples described in this specification.

[0087] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the drawings and the disclosed content. In the description of the present invention, the word "comprising" does not exclude other components or steps, "one" or "a" does not exclude multiple situations, and "multiple" means two or more, unless otherwise clearly and specifically defined. In addition, certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0088] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. An undoped tunneling junction tunneling field effect transistor, characterized in that: include: Substrate, drain, N+Si layer, SiO2 isolation, intrinsic Si, L-type metal structure, intrinsic Ge, gate, first oxide layer and second oxide layer; The N+Si layer is stacked on the substrate, and the drain is stacked on both sides of the N+Si layer; the intrinsic Si is stacked in the middle of the upper part of the N+Si layer, and the SiO2 is stacked on both sides of the intrinsic Si for isolation; the intrinsic Ge is stacked on both sides of the upper part of the intrinsic Si, and the gate is provided between the intrinsic Ge on both sides, and the gate and the intrinsic Ge and the intrinsic Si are all separated by the first oxide layer; The second oxide layer is covered above the SiO2 isolation and outside the intrinsic Ge; a high work function metal is stacked on the outside of the second oxide layer and above the intrinsic Ge to form the L-shaped metal structure; the high work function metal stacked above the intrinsic Ge forms a source, and the high work function metal stacked on the outside of the second oxide layer forms a back gate.

2. The undoped tunneling junction tunneling field effect transistor according to claim 1, characterized in that: The doping concentration of the N+Si layer is 1×10 19 / cm 3 ~1×10 21 / cm 3 , with a thickness of 10nm to 20nm.

3. The undoped tunneling junction tunneling field effect transistor according to claim 1, characterized in that: The intrinsic Ge is unintentionally doped Ge, and its intrinsic carrier concentration is 1×10 15 / cm 3 ~1×10 17 / cm 3 , its thickness is 30nm~45nm.

4. The undoped tunneling junction tunneling field effect transistor according to claim 1, characterized in that: The intrinsic Si is unintentionally doped Si, and its intrinsic carrier concentration is 1×10 15 / cm 3 -1×10 17 / cm 3 , and its thickness is 15nm~45nm.

5. The undoped tunneling junction tunneling field effect transistor according to claim 1, characterized in that: The first oxide layer and the second oxide layer are both HfO2 oxide layers, and the thickness thereof is 2 nm to 3 nm.

6. The undoped tunneling junction tunneling field effect transistor according to claim 1, characterized in that: The gate is made of metal aluminum.

7. The undoped tunneling junction tunneling field effect transistor according to claim 1, characterized in that: The high work function metal includes platinum.

8. A method for preparing an undoped tunneling junction tunneling field effect transistor, characterized in that: include: Step 1: growing an N+Si layer on a substrate and depositing drain electrodes on both sides of the N+Si layer; Step 2: growing intrinsic Si on the N+Si layer, etching both sides of the intrinsic Si to form an isolation region, and depositing SiO2 isolation in the isolation region; Step 3: growing intrinsic Ge on the intrinsic Si, and etching the middle of the intrinsic Ge to form a gate groove to expose the intrinsic Si underneath; Step 4: Deposit a layer of oxide on the surface of the current sample; Step 5: depositing a gate in the gate groove, removing the oxide above the intrinsic Ge and the oxide above the gate in the gate groove; wherein the remaining oxide in the gate groove constitutes a first oxide layer, and the oxide above the SiO2 isolation and outside the intrinsic Ge constitutes a second oxide layer; Step 6: Depositing a high work function metal on the outside of the second oxide layer and on the intrinsic Ge to form an L-shaped metal structure; wherein the high work function metal deposited on the intrinsic Ge forms a source, and the high work function metal deposited on the outside of the second oxide layer forms a back gate; Step 7: Photolithography is performed to form electrode windows on the drain, source, and gate electrodes, thereby completing the lead-out of the drain, source, and gate electrodes and completing device preparation.

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