Method for rapidly determining center position of electronic cloud cluster of reading circuit in XS anode detector

Abstract

The invention provides a method for rapidly determining the center position of an electron cloud cluster of a reading circuit in an XS anode detector, and aims to solve the problems that the existing method for calculating the center position of the electron cloud cluster of the reading circuit in the XS anode detector cannot realize higher spatial resolution, or easily causes image distortion, and is inconvenient to use. The software processing speed is slow, the FPGA is not easy to implement, or the calculation error at the edge strip is relatively large. The method for rapidly determining the center position of the electronic cloud cluster of the reading circuit in the XS anode detector is realized by adopting an FPGA (Field Programmable Gate Array), the peak value of effective data of each channel is obtained through single-channel processing, and then a corresponding drop point distribution index code is generated through table look-up and cross-channel processing; and then adaptive weight selection is carried out according to the drop point distribution index code, so that the weight accuracy of weighted average operation is ensured, key support is provided for rapid and accurate calculation of the center position of the electronic cloud cluster, and high efficiency and accuracy of the whole data processing flow are ensured.

Description

Technical Field

[0001] The present invention relates to an XS anode readout circuit, and in particular to a method for quickly determining the center position of an electron cloud in a readout circuit of an XS anode detector. Background Art

[0002] Currently, single-photon cameras are widely used in deep space exploration, Earth's ionosphere, and biological exploration. The performance of single-photon cameras is limited by two components: the front-end anode structure and the back-end readout circuit. The front-end anode structure determines the readout method of the back-end readout circuit, which in turn affects detection accuracy. In 1974, Lampton's team proposed a resistive position-sensitive anode, which solved the problems of equipment size, complexity, cost, weight, and information loss caused by the use of traditional television camera tube imaging in space exploration missions. In the following decades, anode structures such as wedge-shaped anodes, delay-line anodes, and crossed-delay-line anodes emerged to achieve larger imaging areas and better resolution. Among them, the crossed-strip position-sensitive anode (XS anode) proposed by Siegmund's team uses two layers of mutually perpendicular and insulated elongated strip electrodes to sample the spatial distribution of charge events leaving the microchannel plate (MCP) and determine the center position of each event using the signal obtained from each electrode. Compared with other detector structures, the XS anode detector has the characteristics of high parallelism, high spatial resolution, high temporal resolution and long service life, but the large amount of data it generates places higher requirements on the back-end readout circuit.

[0003] like Figure 1 As shown, the front end of the XS anode detector mainly includes an incident window 1, a photocathode 2, a microchannel plate 3, and an XS anode 4. Among them, the microchannel plate 3 and the XS anode 4 need to work in a vacuum environment. Photons are irradiated onto the photocathode 2 through the incident window 1 and converted into photoelectrons on the photocathode 2. The photoelectrons generated by the photocathode 2 are then accelerated and multiplied in the microchannel plate 3, eventually becoming an electron cloud composed of a large number of electrons, which then collide with the XS anode 4. The charge is divided by the conductive micro-strip electrodes that are isolated and orthogonal to each other in the XS anode 4. Each strip of the XS anode 4 collects the charge and transfers it to the detector port.

[0004] like Figure 2As shown, the back end of the XS anode detector is a readout circuit, which usually includes a charge sensitive amplifier 5, an X-direction ADC sub-board, a Y-direction ADC sub-board, an X-direction FPGA, and a Y-direction FPGA. After the charges on all the strips of the XS anode 4 reach the charge sensitive amplifier 5 at the back end, they are shaped and amplified into voltage signals that can be collected by the ADC sub-board. Subsequently, the voltage signals corresponding to multiple strips in the X direction will be sampled in parallel by the X-direction ADC sub-board, and the voltage signals corresponding to multiple strips in the Y direction will be sampled in parallel by the Y-direction ADC sub-board. Finally, these digital signals will be processed by the X-direction FPGA and the Y-direction FPGA respectively, and the coordinates of the center of mass of the electron cloud in the X and Y directions will be calculated. The center position of the electron cloud is obtained after the interaction between the X-direction FPGA and the Y-direction FPGA. As shown Figure 3 As shown, the center position of each electron cloud is transmitted to a computer via Gigabit Ethernet. The coordinates of each electron cloud center correspond to the position of an incident photon. After a period of exposure, the position coordinates of a large number of incident photons are accumulated to obtain a two-dimensional image of the photon source.

[0005] Existing methods for calculating the center position of the electron cloud in the readout circuit of the XS anode detector generally include interpolation convolution algorithms, fitting function algorithms, and simple weighted averaging algorithms. The interpolation convolution algorithm has a relatively good signal-to-noise ratio, and the error is relatively smooth at all positions. However, this algorithm does not expand the original signal and cannot achieve high spatial resolution. The fitting function algorithm is simple in principle and can achieve high spatial resolution, but improper selection of the fitting function may cause image distortion, slow software processing speed, and difficult to implement using FPGAs. Although the simple weighted averaging algorithm is easy to implement using FPGAs and has fast calculation speed, the calculation error at the edge strips is relatively large. If the electron cloud falls at different positions on the XS anode, the accuracy will be affected to a certain extent due to the small number of event channels. Summary of the Invention

[0006] The present invention aims to provide a method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector, in order to address the technical problems that existing methods for calculating the center position of an electron cloud in a readout circuit of an XS anode detector cannot achieve high spatial resolution, easily cause image distortion, have slow software processing speeds and are difficult to implement using FPGAs, or result in relatively large calculation errors at edge strips.

[0007] In order to achieve the above object, the technical solution provided by the present invention is as follows:

[0008] A method for quickly determining the center position of an electron cloud in a readout circuit of an XS anode detector is characterized in that it comprises the following steps:

[0009] Step 1, single-channel processing of the ADC sampling signal;

[0010] Step 1.1: When an event occurs, the X-direction FPGA in the readout circuit receives the ADC sampling signals corresponding to each X-direction strip of the XS anode in parallel, and the Y-direction FPGA receives the ADC sampling signals corresponding to each Y-direction strip of the XS anode in parallel. The X-direction FPGA and the Y-direction FPGA each compare the received ADC sampling signals with a first set threshold value, and store the ADC sampling signals that exceed the first set threshold value as valid data for the corresponding channel.

[0011] Step 1.2: Find the peak value of the valid data of each channel on the X-direction FPGA and the Y-direction FPGA respectively, and serialize the peak value of the valid data of each channel to obtain the peak data corresponding to each channel to represent the status of each channel when the event occurs;

[0012] Step 2: Perform cross-channel processing on the peak data of each channel;

[0013] Step 2.1: The X-direction FPGA and the Y-direction FPGA respectively compare the peak data of each channel with the second set threshold value, and generate a corresponding binary index code based on the comparison results;

[0014] Step 2.2: The X-direction FPGA and the Y-direction FPGA use the corresponding binary index code as the address to look up the table and generate the corresponding landing point distribution index code;

[0015] Step 2.3: Based on the landing point distribution index codes obtained by the X-direction FPGA and the Y-direction FPGA, the channel peak data that matches the current landing point distribution is selected and used as the weights for the weighted averaging operations of the X-direction FPGA and the Y-direction FPGA.

[0016] Step 3: Apply the weights of the weighted average calculations of the X-direction FPGA and the Y-direction FPGA to the corresponding weighted average calculations to obtain the centroid coordinates of the electron cloud in the X-direction and the Y-direction;

[0017] Step 4: splice the centroid coordinates of the electron cloud in the X and Y directions to obtain the center position of the electron cloud.

[0018] Furthermore, in step 1.1, asynchronous FIFO memories are respectively set in the X-direction FPGA and the Y-direction FPGA;

[0019] The X-direction FPGA and the Y-direction FPGA store the ADC sampling signals exceeding the first set threshold as valid data of the corresponding channels in the corresponding asynchronous FIFO memories.

[0020] Furthermore, in step 1.2, registers are set in the X-direction FPGA and the Y-direction FPGA respectively;

[0021] The register of the X-direction FPGA includes N storage areas, and the register of the Y-direction FPGA includes M storage areas, where N is the number of channels corresponding to the X-direction of the XS anode, and M is the number of channels corresponding to the Y-direction of the XS anode, N ≥ 6, M ≥ 6;

[0022] The peak data corresponding to the N channels in the X direction of the XS anode are respectively stored in the N storage areas of the register in the X direction FPGA;

[0023] The peak data corresponding to the M channels in the Y direction of the XS anode are respectively stored in the M storage areas of the register in the Y direction FPGA.

[0024] Furthermore, in step 1.2, the size of each storage area in the register corresponding to the X-direction FPGA and the Y-direction FPGA is 12 bits.

[0025] Furthermore, step 2.2 is specifically as follows:

[0026] A ROM storage unit is configured in each of the X-direction FPGA and the Y-direction FPGA, and a lookup table is stored in each of the ROM storage units;

[0027] The binary index codes corresponding to the X-direction FPGA and the Y-direction FPGA are input into the corresponding ROM storage unit as the address of the lookup table. The ROM storage unit locates the corresponding data in the lookup table through the address decoder and outputs the data stored at the corresponding address, thereby obtaining the landing point distribution index code.

[0028] Furthermore, in step 1.2, the peak values ​​of valid data of each channel on the X-direction FPGA and the Y-direction FPGA are found as follows:

[0029] The valid data transmitted by each channel is stored. If the valid data newly read by a channel is greater than or equal to the current value of the channel, the valid data of the channel is updated to the newly read valid data, otherwise the current value remains unchanged. Each time a comparison is made, a counting register will continuously increase the count. When the count value of the counting register is equal to the total amount of valid data of the corresponding channel, the peak value search of the channel is completed, and the current value is output as the peak value of the valid data of the channel.

[0030] Furthermore, in step 1.1, the value range of the first set threshold is 300-500;

[0031] In step 2.1, the second set threshold value ranges from 200 to 450.

[0032] Furthermore, in step 1.1, the value range of the first set threshold is 400;

[0033] In step 2.1, the value range of the second set threshold is 350.

[0034] Furthermore, step 2.1 is specifically as follows:

[0035] In step a, the X-direction FPGA and the Y-direction FPGA respectively compare the peak data of each channel with a second set threshold value through a comparator; if the peak data of the current channel exceeds the second set threshold value, the comparator outputs a logic value of 1; otherwise, the comparator outputs a logic value of 0;

[0036] Step b: Generate corresponding binary index codes according to the logic values ​​output by the respective comparators in the X-direction FPGA and the Y-direction FPGA.

[0037] Furthermore, in step 2.3, the channel peak data that is adapted to the current landing point distribution is filtered through the state machine.

[0038] The beneficial effects of the present invention compared to the prior art are as follows:

[0039] 1. The present invention provides a method for quickly determining the center position of the electron cloud cluster in the readout circuit of an XS anode detector. The system is implemented using FPGA. The peak value of the effective data of each channel is first obtained through single-channel processing, and then the corresponding landing point distribution index code is generated through table lookup combined with cross-channel processing. When encountering different numbers of event channels, adaptive weight selection will be performed according to the landing point distribution index code, ensuring the accuracy of the weights of the weighted averaging operation, providing key support for the rapid and accurate calculation of the center position of the electron cloud cluster, and ensuring the efficiency and accuracy of the entire data processing process.

[0040] 2. The present invention provides a method for quickly determining the center position of the electron cloud in the readout circuit of an XS anode detector. This method not only greatly reduces the dead time spent by the system in searching for event channels and calculating the center of mass, but also improves the spatial resolution of the imaging. While fully leveraging the high-resolution advantages of the XS anode structure, it can meet the XS anode's requirements for the back-end electronics to quickly process large amounts of data. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 This is a schematic diagram of the principle of the front end of the existing XS anode detector;

[0042] Figure 2 Schematic diagram of the principle of analyzing the center position of the electron cloud using the readout circuit in the existing XS anode detector;

[0043] Figure 1 、 Figure 2 The reference numerals in the figures are as follows: 1-incident window; 2-photocathode; 3-microchannel plate; 4-XS anode; 5-charge sensitive amplifier;

[0044] Figure 3 Schematic diagram of the imaging process of the existing XS anode detector;

[0045] Figure 4 Schematic diagram of a flow chart of a method for quickly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to the present invention;

[0046] Figure 5 Schematic diagram of the processing flow of the Y-direction FPGA in an embodiment of the present invention;

[0047] Figure 6 This is a schematic diagram of the asynchronous FIFO memory storing valid data in step 1.1 of an embodiment of the present invention;

[0048] Figure 7 Schematic diagram of calibrating channel status in step 1.1 of an embodiment of the present invention;

[0049] Figure 8 This is a schematic diagram of obtaining the binary index code INDEX1 in step 2.1 of an embodiment of the present invention;

[0050] Figure 9 This is a schematic diagram of obtaining the landing point distribution index code INDEX2 by looking up the table in step 2.2 of an embodiment of the present invention;

[0051] Figure 10 This is a schematic diagram of achieving precise control of the landing point distribution index code INDEX2 in step 2.3 of an embodiment of the present invention. DETAILED DESCRIPTION

[0052] In order to make the advantages and features of the present invention more clear, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0053] A method for quickly determining the center position of the electron cloud in the readout circuit of an XS anode detector, such as Figure 4 As shown in the figure, after the ADC sampling signals corresponding to the X-direction ADC daughter board and the Y-direction ADC daughter board in the readout circuit enter the FPGA in parallel, they need to go through three parts of processing: 1. Single-channel processing (calibrating the channel status); 2. Cross-channel processing (finding the event channel and selecting the weight); 3. Centroid calculation (weighted averaging). The steps of each part are as follows:

[0054] Step 1: Single-channel processing.

[0055] The ADC sampling signals corresponding to each stripe in the X and Y directions of the XS anode are processed independently, thus filtering out valid data from a large number of samples. At the same time, this step also determines the state of each channel when the event occurs, that is, each channel in the X and Y directions of the XS anode corresponds to a specific value.

[0056] Step 1.1, signal reception and data screening.

[0057] When an event occurs, the X-direction FPGA in the readout circuit receives the ADC sampling signals corresponding to each X-direction strip of the XS anode in parallel. The Y-direction FPGA also receives the ADC sampling signals corresponding to each Y-direction strip of the XS anode in parallel. Because the processing flows of the X-direction FPGA and Y-direction FPGA are similar, the following uses the Y-direction FPGA as an example.

[0058] like Figure 5 As shown, an asynchronous FIFO memory is set in the Y-direction FPGA; the Y-direction FPGA compares the received ADC sampling signals with the first set threshold value and performs data screening to determine whether an electron cloud event has occurred. If the ADC sampling signal corresponding to at least one strip exceeds the first set threshold value, it means that the event has occurred; when the ADC sampling signals corresponding to all strips are less than the first set threshold value, it means that the event has not occurred or the event has ended. Using the asynchronous FIFO memory, the valid data corresponding to each channel can be stored. Its logic is as follows Figure 6 As shown, taking four channels as an example, when an ADC sampling signal exceeds a first set threshold, the asynchronous FIFO memory is enabled and the corresponding ADC sampling signal data is stored as valid data for the corresponding channel. The first set threshold is adjusted and selected based on different test environments and noise factors. Its value range is 300-500, and in this embodiment, it is 400.

[0059] Step 1.2: Channel status calibration.

[0060] On the XS anode, because the signal propagation delay between channels in a single direction is very small, when an electron cloud event occurs, the signal peaks on each channel appear almost simultaneously. Therefore, when the Gaussian signal generated on a channel reaches its peak, it can be assumed that an event has occurred in that channel at that moment.

[0061] Figure 7 The channel status calibration process is demonstrated. The peak value of the valid data of each channel on the FPGA in the Y direction is found, and the peak value of the valid data of each channel is serialized to obtain the peak data corresponding to each channel. This peak data represents the actual response of each channel on the XS anode when the event occurs. In this way, the status of each channel when the event occurs can be determined.

[0062] The peak search process is as follows: First, the system reads the valid data transmitted by each channel and registers it. If the newly read valid data for a channel is greater than or equal to the current value of the channel, the valid data of the channel is updated to the newly read valid data; otherwise, the current value remains unchanged. During the entire comparison process, a counter register is continuously incremented with each comparison. When the count register value equals the total amount of valid data for the corresponding channel, the peak search for that channel is completed, and the current value is output as the peak value of the valid data for that channel and transmitted to subsequent modules.

[0063] A register is set up in the Y-direction FPGA, and the peak data for each channel is stored in this register. The register has M storage areas, and the number of storage areas is determined by the number of channels in the XS anode's Y-direction. That is, the peak value of the valid data for each channel in the XS anode's Y-direction is stored in the corresponding storage area. In this embodiment, the number of channels in the XS anode's Y-direction is 8, so the register has 8 storage areas. In this embodiment, each storage area is 12 bits in size, that is, the register stores the peak data corresponding to each channel for every 12 bits, in the order of the channels.

[0064] Step 2: cross-channel processing.

[0065] Cross-channel processing uses the peak data selected from each channel to find the effective landing point range of the electron cloud, thereby providing appropriate weights for the subsequent centroid calculation process. The algorithm uses threshold comparison to determine which channels have experienced events, discarding data generated from invalid channels where no events have occurred. The system then uses the index code obtained from the table lookup to determine the different situations of the electron cloud landing point range and selects the appropriate weights for the centroid calculation. The specific process is as follows:

[0066] Step 2.1, as Figure 8 As shown, taking 8 channels as an example, the peak data of each channel in the register is compared with the second set threshold through multiple comparators. If the peak data of the current channel exceeds the second set threshold, the corresponding comparator outputs a logic value of 1, indicating that an event has occurred in the channel corresponding to the channel, and the peak data of the channel is maintained; otherwise, the corresponding comparator outputs a logic value of 0, indicating that no event has occurred in the channel corresponding to the channel, and the peak data of the channel is discarded. This part is implemented by the channel arbitrator. The second set threshold is also adjusted and selected according to different test environments and noise and other influences. Its value range is 200-450, and 300 is taken in this embodiment.

[0067] The individual comparison results of each comparator are stored in the corresponding bit of the index_1 register, generating an 8-bit binary index code INDEX1. Since only the peak data of channels 3, 4, 5, and 6 among the eight channels exceeds the second set threshold, the obtained binary index code INDEX1 is 00111100. The 106-bit data is converted into an 8-bit signal, clearly showing the channel where the event occurred.

[0068] In step 2.2, a ROM storage unit is configured in the Y-direction FPGA. This ROM unit stores a lookup table, previously optimized through simulation calculations. The lookup table is constructed as follows: a sliding center of mass simulation model is constructed, with the center of mass fixed at a high-precision position to simulate the actual charge distribution. The weighted center of mass method is then used to calculate the error statistics for different weighting factor combinations. For each center of mass position, the weighting factor combination with the smallest error is selected and recorded to form the lookup table.

[0069] like Figure 9 As shown, the binary index code INDEX1 is input into the ROM storage unit as the address of the lookup table. After receiving the address of the binary index code INDEX1, the ROM storage unit locates the corresponding data in the lookup table through the address decoder and outputs the data stored at the corresponding address, thereby obtaining the landing point distribution index code INDEX2. The landing point distribution index code INDEX2 uses a 10-bit width to describe the landing point distribution of the charge cloud. Among them, bit9 is the flag bit for whether the event has occurred, bits 8-bit6 are the landing point range of the electron cloud, that is, the number of channels whose peak data exceeds the second set threshold, and bits 5-bit0 are the minimum channel position where the event occurred. The 10-bit width is the minimum necessary encoding length obtained by precise calculation based on the function. Each bit has a clear logical meaning (event identification, coverage range, minimum channel index, etc.), without redundancy, controlling the use of logic resources, and is suitable for FPGA real-time processing architecture.

[0070] Using the above table lookup method, the Y-direction FPGA only needs to perform a table lookup operation in one clock cycle to determine which channels have events, which greatly reduces the time required for the system to find the event channel.

[0071] Step 2.3: Determine the weights of the weighted average operation.

[0072] The weighted average operation is an important step before the centroid calculation. The selection of its weight directly affects the accuracy of the calculation result. Therefore, an effective mechanism is needed to determine the weight of the weighted average operation.

[0073] The present invention obtains the lowest boundary of the landing point range and the number of landing points by reading the landing point distribution index code INDEX2, thereby determining the specific channel location where the event occurs, and then screening out the peak data of the corresponding channel that is adapted to the current landing point distribution, and uses it as the weight for the weighted average operation in the subsequent centroid calculation of the Y-direction FPGA to ensure the efficiency and accuracy of the centroid calculation.

[0074] In this embodiment, the selection of weights is achieved through a state machine, which distinguishes and converts different states according to the landing point distribution index code INDEX2, thereby screening out appropriate channel peak data.

[0075] like Figure 10 As shown, the process of achieving precise control based on the landing point distribution index code INDEX2 is as follows: first, starting from the idle state St_idle, after receiving the trigger signal, the code of index_2 is parsed through the channel preparation state St_cha, and jumps to the corresponding processing state (non-edge area-even strip state St_even, non-edge area-odd strip state St_odd, edge area-7 strip window state St_edge1, edge area-8 strip window state St_edge2, edge area-9 strip window state St_edge3). In each state, the channel peak data corresponding to the current landing point distribution (different strip scenes) is accurately intercepted as the weight for the weighted average operation. Ultimately, a complete closed loop of "trigger-state judgment-weight selection-output" is formed, which ensures the accuracy of the weight of the weighted average operation, provides key support for the rapid and accurate calculation of the center position of the electron cloud cluster, and ensures the efficiency and accuracy of the entire data processing process.

[0076] The same method as above is used to obtain the weight of the weighted average operation in the subsequent FPGA centroid calculation in the X direction.

[0077] Step 3: Calculate the centroid.

[0078] In the process of quickly determining the center position of the electron cloud, accurate center of mass calculation plays a key role in accurate data analysis. The present invention uses the state of each channel at the time of the event as a weight and performs a weighted average operation to calculate the center position of the electron cloud. The present invention first uses a weighted average operation to calculate the center of mass coordinates x0 of the electron cloud in the X direction and the center of mass coordinates y0 of the electron cloud in the Y direction. The expressions are as follows:

[0079]

[0080] Among them, x i It is represented as the strip position in the X direction of the XS anode, corresponding to the channel number of the event under the corresponding weight, is the weight of the FPGA weighted average operation in the X direction, n is the range of values ​​for summation in the FPGA weighted average calculation in the X direction, that is, the channel range where the event occurs; i Expressed as the strip position in the Y direction of the XS anode, is the weight of the FPGA weighted average calculation in the Y direction, and m is the value range of the summation when calculating the FPGA weighted average in the Y direction.

[0081] The calculation steps above consist of two modules: the numerator and denominator calculation module and the division calculation module. The centroid calculation involves parallel calculations of the numerator and denominator, followed by the use of three dividers for division. Whenever an event occurs, the division arbiter queries the availability of each divider and calls an unused divider to reduce the system's dead time during weighted averaging. Dynamically scheduling the three dividers to complete the centroid calculation reduces the system's dead time caused by divider operations, significantly improving the system's data processing speed.

[0082] In step 4, the processing flow between the X-direction FPGA and the Y-direction FPGA differs only in that, after the X-direction FPGA obtains the X-direction center of mass coordinate x0, it is directly input into the Y-direction FPGA. This coordinate is then combined with the Y-direction center of mass coordinate y0 within the Y-direction FPGA to obtain the center position of the electron cloud. In other embodiments of the present invention, the Y-direction center of mass coordinate y0 obtained by the Y-direction FPGA can also be input into the X-direction FPGA and combined with the X-direction center of mass coordinate x0.

[0083] The above description is only used to illustrate the technical solution of the present invention, rather than to limit it. For ordinary professional and technical personnel in this field, the specific technical solutions recorded in the above embodiments can be modified, or some of the technical features therein can be replaced by equivalents. These modifications or replacements do not cause the essence of the corresponding technical solution to deviate from the scope of the technical solution protected by the present invention.

Claims

1. A method for quickly determining the center position of the electron cloud in the readout circuit of an XS anode detector, characterized in that: The following steps are involved: Step 1, single-channel processing of the ADC sampling signal; Step 1.1: When an event occurs, the X-direction FPGA in the readout circuit receives the ADC sampling signals corresponding to each X-direction strip of the XS anode in parallel, and the Y-direction FPGA receives the ADC sampling signals corresponding to each Y-direction strip of the XS anode in parallel. The X-direction FPGA and the Y-direction FPGA each compare the received ADC sampling signals with a first set threshold value, and store the ADC sampling signals that exceed the first set threshold value as valid data for the corresponding channel. Step 1.2: Find the peak value of the valid data of each channel on the X-direction FPGA and the Y-direction FPGA respectively, and serialize the peak value of the valid data of each channel to obtain the peak data corresponding to each channel to represent the status of each channel when the event occurs; Step 2: Perform cross-channel processing on the peak data of each channel; Step 2.1: The X-direction FPGA and the Y-direction FPGA respectively compare the peak data of each channel with the second set threshold value, and generate a corresponding binary index code based on the comparison results; Step 2.2: The X-direction FPGA and the Y-direction FPGA use the corresponding binary index code as the address to look up the table and generate the corresponding landing point distribution index code; Step 2.3: Based on the landing point distribution index codes obtained by the X-direction FPGA and the Y-direction FPGA, the channel peak data that matches the current landing point distribution is selected and used as the weights for the weighted averaging operations of the X-direction FPGA and the Y-direction FPGA. Step 3: Apply the weights of the weighted average calculations of the X-direction FPGA and the Y-direction FPGA to the corresponding weighted average calculations to obtain the centroid coordinates of the electron cloud in the X-direction and the Y-direction; Step 4: splice the centroid coordinates of the electron cloud in the X and Y directions to obtain the center position of the electron cloud.

2. The method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to claim 1, characterized in that: In step 1.1, asynchronous FIFO memories are set in the X-direction FPGA and the Y-direction FPGA respectively; The X-direction FPGA and the Y-direction FPGA store the ADC sampling signals exceeding the first set threshold as valid data of the corresponding channels in the corresponding asynchronous FIFO memories.

3. The method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to claim 2, characterized in that: In step 1.2, set registers in the X-direction FPGA and the Y-direction FPGA respectively; The register of the X-direction FPGA includes N storage areas, and the register of the Y-direction FPGA includes M storage areas, where N is the number of channels corresponding to the X-direction of the XS anode, and M is the number of channels corresponding to the Y-direction of the XS anode, N ≥ 6, M ≥ 6; The peak data corresponding to the N channels in the X direction of the XS anode are respectively stored in the N storage areas of the register in the X direction FPGA; The peak data corresponding to the M channels in the Y direction of the XS anode are respectively stored in the M storage areas of the register in the Y direction FPGA.

4. The method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to claim 3, characterized in that: In step 1.2, the size of each storage area in the corresponding registers of the X-direction FPGA and the Y-direction FPGA is 12 bits.

5. A method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to any one of claims 1 to 4, characterized in that: Step 2.2 is as follows: A ROM storage unit is configured in each of the X-direction FPGA and the Y-direction FPGA, and a lookup table is stored in each of the ROM storage units; The binary index codes corresponding to the X-direction FPGA and the Y-direction FPGA are input into the corresponding ROM storage unit as the address of the lookup table. The ROM storage unit locates the corresponding data in the lookup table through the address decoder and outputs the data stored at the corresponding address, thereby obtaining the landing point distribution index code.

6. The method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to claim 5, characterized in that: In step 1.2, find the peak value of valid data for each channel on the X-direction FPGA and the Y-direction FPGA respectively: The valid data transmitted by each channel is stored. If the valid data newly read by a channel is greater than or equal to the current value of the channel, the valid data of the channel is updated to the newly read valid data, otherwise the current value remains unchanged; Each time a comparison is performed, a counter register will continuously increment. When the count value of the counter register is equal to the total amount of valid data of the corresponding channel, the peak value search of the channel is completed and the current value is output as the peak value of the valid data of the channel.

7. The method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to claim 6, characterized in that: In step 1.1, the value range of the first set threshold is 300-500; In step 2.1, the second set threshold value ranges from 200 to 450.

8. The method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to claim 7, characterized in that: In step 1.1, the value range of the first set threshold is 400; In step 2.1, the value range of the second set threshold is 350.

9. The method for quickly determining the center position of the electron cloud in the readout circuit of an XS anode detector according to claim 1, characterized in that: Step 2.1 is as follows: In step a, the X-direction FPGA and the Y-direction FPGA respectively compare the peak data of each channel with a second set threshold value through a comparator; if the peak data of the current channel exceeds the second set threshold value, the comparator outputs a logic value of 1; otherwise, the comparator outputs a logic value of 0; Step b: Generate corresponding binary index codes according to the logic values ​​output by the respective comparators in the X-direction FPGA and the Y-direction FPGA.

10. The method for rapidly determining the center position of an electron cloud in a readout circuit of an XS anode detector according to claim 9, characterized in that: In step 2.3, the state machine is used to filter the channel peak data that is adapted to the current landing point distribution.

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