An industrial control system configuration cloud compiling method and system

Abstract

The application discloses an industrial control system configuration cloud compiling method and system, relates to the cross technical field of cloud computing, and comprises the following steps: carrying out deep-first traversal on a logic flow graph, counting the occurrence frequency of instruction operation codes, and calculating the information-intensive degree evaluation value of program codes; based on the information-intensive evaluation value, analyzing the distribution characteristics of the occurrence frequency of operation code types and the weight of operation codes, combining the comparison result of the instruction entropy threshold value, identifying high-frequency redundant instruction operation codes, compressing and merging the high-frequency redundant instruction operation codes, optimizing the conditional jump structure of the logic flow graph, and generating intermediate optimized code units; based on the intermediate optimized code units, carrying out topological dependence analysis and implementing local incremental compiling verification, and generating executable machine code. The application can accurately identify high-frequency redundant operation codes and carry out semantic-level compression and merging by calculating the information-intensive degree evaluation value of program codes, and can generate concise and reliable control program codes under the condition of maintaining industrial hard real-time constraints.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of cloud computing cross, and particularly relates to an industrial control system configuration cloud compiling method and system. BACKGROUND

[0002] Industrial control system configuration compiling is a core process of converting graphical and textual control logic into executable code. The conventional method relies on a localized compiling tool chain to parse the configuration engineering file, combine the target hardware instruction set for code conversion, and finally generate machine code. With the development of industrial Internet of Things, the traditional compiling process is gradually migrated to the cloud platform to realize engineering collaborative design and cross-hardware platform deployment using distributed resources, but the core still revolves around the static syntax parsing and rule-driven code generation paradigm. The existing technology has established a mature instruction set mapping mechanism and timing arrangement rule to provide basic compiling support for industrial control.

[0003] However, the existing method still has optimization bottlenecks. Due to the lack of quantitative evaluation of the instruction frequency distribution of program code and the scientific evaluation of information intensity, it is difficult to accurately identify high-frequency redundant instructions, so that invalid operations cannot be effectively compressed. In the engineering iteration scene, the incremental modification of configuration logic still needs to trigger full-amount code recompilation, and the influence domain of the change cannot be located based on the topology dependency relationship, causing resource waste. SUMMARY

[0004] In view of the above existing problems, an industrial control system configuration cloud compiling method and system are provided.

[0005] Therefore, the present application provides an industrial control system configuration cloud compiling method to solve the problem of insufficient dynamic instruction optimization precision.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides an industrial control system configuration cloud compiling method, which comprises,

[0008] The cloud end collects and parses the industrial control configuration engineering file in real time, extracts the instruction operation code, and generates program code through target hardware instruction set mapping and logical timing arrangement;

[0009] The program code is semantically parsed and data flow tracked to generate a logical flow graph;

[0010] The logical flow graph is traversed in depth-first manner, the frequency of instruction operation code is counted, and the information intensity evaluation value of the program code is calculated;

[0011] Based on the information-intensive evaluation value, the distribution characteristics of the operation code type frequency and the operation code weight are analyzed, and the high-frequency redundant instruction operation code is identified by combining the instruction entropy threshold comparison result, the high-frequency redundant instruction operation code is compressed and merged, the conditional jump structure of the logical flow graph is optimized, and the intermediate optimized code unit is generated.

[0012] Based on the intermediate optimized code unit, topological dependence analysis is carried out, and local incremental compilation verification is implemented, and executable machine code is generated.

[0013] As a preferred scheme of the industrial control system configuration cloud compiling method, wherein: the industrial control configuration engineering file includes graphical logic, textual program, hardware configuration, communication parameter, variable database and process parameter configuration file.

[0014] As a preferred scheme of the industrial control system configuration cloud compiling method, wherein: the generated program code has the following specific steps,

[0015] Based on the industrial control configuration engineering file, real-time multi-format streaming parsing and semantic deconstruction are carried out, and instruction operation code is extracted.

[0016] Based on the instruction operation code, target hardware instruction set mapping conversion and industrial control logic timing arrangement are carried out, and program code containing timing constraints is generated.

[0017] As a preferred scheme of the industrial control system configuration cloud compiling method, wherein: the program code is semantically analyzed and data flow tracking is carried out, and the logical flow graph is generated, and the specific steps are as follows,

[0018] Based on the program code containing timing constraints, control flow analysis and data flow tracking are carried out, and conditional jump structure and variable dependence chain are extracted.

[0019] The timing constraints in the program code are analyzed, the scanning period constraint value is extracted, the conditional jump structure and the variable dependence chain are combined, and the semantic structure containing timing markers is generated.

[0020] Based on the semantic structure containing timing markers, operation code to node mapping conversion and dependence relationship analysis are carried out, and the analyzed timing constraints are injected into nodes and edges, and the node set and edge set of the primary logical flow graph containing timing markers are generated.

[0021] Based on the node set and edge set of the primary logical flow graph, the directed graph topology is constructed, and the logical flow graph is generated.

[0022] As a preferred scheme of the industrial control system configuration cloud compiling method, wherein: the depth-first traversal logical flow graph is used to count the frequency of instruction operation code, and the information-intensive degree evaluation value of the program code is calculated, and the specific steps are as follows,

[0023] The logic flow graph is traversed by a depth-first traversal algorithm, and the frequency of instruction operation codes in the logic flow graph nodes is counted;

[0024] Based on the frequency of instruction operation codes in the logic flow graph nodes, the information intensity evaluation value is calculated.

[0025] As a preferred scheme of the industrial control system configuration cloud compiling method, wherein: based on the information intensity evaluation value, the high-frequency redundant instruction operation codes are compressed and merged, the conditional jump structure of the logic flow graph is optimized, and the intermediate optimized code unit is generated, and the specific steps are as follows,

[0026] Based on the information intensity evaluation value, the variable dependency chain is analyzed, when the combination characteristics of the operation code type frequency and the operation code weight are lower than the instruction entropy threshold value, the high-frequency redundant instruction operation codes are identified, and equivalent logic merging and instruction semantic dimension reduction processing are performed, and the compressed instruction set is generated;

[0027] Based on the topology relationship of the logic flow graph and the compressed instruction set, the jump order is reconstructed by branch priority scheduling and bound timing constraints, and the optimized topology graph is output;

[0028] The optimized topology graph is converted by reverse compilation, and combined with the scanning period constraint value, the intermediate optimized code unit is generated.

[0029] As a preferred scheme of the industrial control system configuration cloud compiling method, wherein: based on the intermediate optimized code unit, the topology dependency analysis is performed and the local incremental compilation verification is implemented, and the executable machine code is generated, and the specific steps are as follows,

[0030] Based on the intermediate optimized code unit, the static dependency graph is constructed, the data dependency, control dependency and interrupt dependency are extracted, and the real-time criticality and safety isolation boundary are divided, and the topology dependency partition graph is generated;

[0031] Based on the topology dependency partition graph and the intermediate optimized code unit, the compilation mode is decided according to the industrial safety partition rule, and the real-time of data dependency, control dependency and interrupt dependency is verified in the virtual PLC environment, the back-end compilation optimization is performed, and the executable machine code is generated.

[0032] In the second aspect, the application provides an industrial control system configuration cloud compiling system, which comprises a cloud file analysis module, an information intensity evaluation module, a graph optimization module and a partition compiling module,

[0033] The cloud file analysis module collects and analyzes industrial control configuration engineering files in the cloud in real time, extracts instruction operation codes, and generates program codes through target hardware instruction set mapping and logical timing arrangement.

[0034] The logic flow graph generation module performs semantic analysis and data flow tracking on the program code to generate a logic flow graph;

[0035] The information intensity evaluation module performs depth-first traversal on the logic flow graph, counts the frequency of instruction operation codes, and calculates the information intensity evaluation value of the program code;

[0036] The graph optimization module, based on the information intensity evaluation value, analyzes the frequency of operation code types and the distribution characteristics of operation code weights, and combines the instruction entropy threshold comparison results to identify high-frequency redundant instruction operation codes, compress and merge the high-frequency redundant instruction operation codes, optimize the conditional jump structure of the logic flow graph, and generate intermediate optimized code units;

[0037] The partition compilation module, based on the intermediate optimized code units, performs topological dependency analysis and implements local incremental compilation verification to generate executable machine code.

[0038] In a third aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the computer program, when executed by the processor, implements any step of the industrial control system configuration cloud compilation method according to the first aspect of the present application.

[0039] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any step of the industrial control system configuration cloud compilation method according to the first aspect of the present application.

[0040] The present application has the following advantages: by calculating the information intensity evaluation value of the program code, high-frequency redundant operation codes are accurately identified and semantically compressed and merged, and a simplified and reliable control program code is generated under the maintenance of industrial hard real-time constraints; by virtual PLC environment oriented verification of the influence of the change domain, online update without interruption and accurate compilation range reduction of the industrial configuration project are achieved. BRIEF DESCRIPTION OF DRAWINGS

[0041] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiment description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0042] Fig. 1 The flowchart of the industrial control system configuration cloud compilation method.

[0043] Fig. 2 The schematic diagram of the industrial control system configuration cloud compilation system.

[0044] Fig. 3 Flowchart for generating a logical flow graph.

[0045] Fig. 4 Flowchart for compiling verification of topology increment. DETAILED DESCRIPTION

[0046] In order to make the above objectives, features and advantages of the present application more apparent, clear and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0047] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without the specific details given herein, that the present application can be practiced with other than the described implementations, and that the present application can be practiced with or in conjunction with other systems, components, and / or methods. In other instances, well-known structures and / or operations are not shown or described in detail in order to avoid obscuring aspects of the present application.

[0048] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the present application. The "in one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments.

[0049] REFERENCE Figs. 1-4 For one embodiment of the present application, the embodiment provides an industrial control system configuration cloud compiling method, comprising the following steps:

[0050] S1, the cloud end collects and analyzes the industrial control configuration engineering file in real time, extracts the instruction operation code, and generates the program code through the target hardware instruction set mapping and logical timing arrangement;

[0051] S1.1, the industrial control configuration engineering file includes graphical logic, textual program, hardware configuration, communication parameter, variable database and process parameter configuration file;

[0052] It should be noted that the industrial control configuration engineering file contains multiple components, specifically graphical logic, textual program, hardware configuration, communication parameter, variable database, and process parameter configuration file. Graphical logic represents the visual representation of control logic, such as in the form of ladder diagram or function block diagram. Textual program involves text-based programming content, such as structured text or instruction list code. Hardware configuration determines the layout and setting of physical devices, such as the number of input-output modules being 16. Communication parameter covers the detailed specification of network communication, such as the protocol type being Modbus TCP and address allocation. Variable database records the definition and attributes of all variables, such as variable name and data type like integer or floating point. Process parameter configuration file stores specific parameter values required for process control, such as temperature setpoint being 100 degrees Celsius or pressure limit being 50 kiloPascal.

[0053] S1.2, based on the industrial control configuration engineering file, real-time multi-format streaming parsing and semantic deconstruction are performed to extract instruction operation codes;

[0054] It should be noted that the industrial control configuration engineering file contains multiple components, specifically graphical logic, textual program, hardware configuration, communication parameter, variable database, and process parameter configuration file. Graphical logic represents the visual representation of control logic, such as in the form of ladder diagram or function block diagram. Textual program involves text-based programming content, such as structured text or instruction list code. Hardware configuration determines the layout and setting of physical devices, such as the number of input-output modules being 16. Communication parameter covers the detailed specification of network communication, such as the protocol type being Modbus TCP and address allocation. Variable database records the definition and attributes of all variables, such as variable name and data type like integer or floating point. Process parameter configuration file stores specific parameter values required for process control, such as temperature setpoint being 100 degrees Celsius or pressure limit being 50 kiloPascal.

[0055] S1.3, based on the instruction operation codes, target hardware instruction set mapping conversion and industrial control logic timing arrangement are performed to generate program code containing timing constraints.

[0056] It should be noted that the instruction operation code parsed and extracted from the industrial control configuration engineering file is converted into the native instruction sequence corresponding to the target hardware architecture, for example, the output coil instruction in the ladder logic is converted into the STR instruction of the ARMv7 architecture; in the industrial control logic timing arrangement stage, the native instruction sequence is sorted according to the process flow sequence, and a synchronization point instruction is inserted at the scan cycle boundary, for example, a BARRIER instruction is implanted every 10ms cycle; according to the preset real-time requirement in the industrial control logic, the critical path is determined, for example, the interrupt service routine or the safety interlock control path is marked as the critical path, and the response delay upper limit constraint is bound for the critical path operation, for example, the interrupt processing instruction is marked with a delay ≤ 50μs; finally, a program code containing timing constraints is generated, which includes hardware native instruction sequence and time attribute label.

[0057] It should be noted that in the industrial control system, the preset of the real-time requirement is established based on the IEC 61131-3 international standard to establish a basic framework, and the real-time level division of different control tasks is clearly defined (such as setting the emergency stop interrupt as the highest priority RT1 level); secondly, the execution cycle parameters of each functional module are specifically set through the configuration software interface (for example, a 2ms cycle value is set in the motion control module attribute); at the same time, resource reservation and timing verification are carried out combined with hardware performance indicators (such as processor interrupt response time ≤ 5μs); finally, through a three-layer verification mechanism, the timing constraint compliance is verified by logic simulation test, the actual response delay is confirmed by hardware-in-the-loop test, and the safety authentication (such as TUV) is ensured to ensure that the timing parameters set in the configuration stage of the industrial control system, including the scan cycle constraint value, the path delay upper limit and the interrupt response time, meet the requirements of the industrial field, so as to form a closed-loop preset system from specification definition to engineering implementation. Timing constraints are mandatory provisions of the execution time attribute of instructions in industrial control programs, which are specifically manifested as scan cycle boundary synchronization requirements and path delay upper limits. The scan cycle boundary synchronization requirement stipulates that the key operation must be completed within a fixed time window, for example, all sensor data acquisition instructions must be executed within every 10ms cycle; the path delay upper limit constraint forces the response time of the critical control flow, for example, the total delay from triggering to executing the emergency stop signal processing instruction should not exceed 100μs.

[0058] S2, semantic analysis and data flow tracking of the program code are performed to generate a logic flow graph;

[0059] S2.1, based on the program code containing timing constraints, control flow analysis and data flow tracking are performed to extract conditional jump structures and variable dependency chains;

[0060] It should be noted that the control flow analysis refers to identifying the branch judgment nodes and loop structures in the program code, analyzing the execution path of the conditional jump instruction, such as extracting the three jump branches corresponding to the IF-THEN-ELSE statement block; at the same time, data flow tracking is performed, the read-write operation sequence of the variable in the program code is scanned, the variable dependency chain is established, such as tracking the complete transmission link of a sensor value from the input register to the operation unit to the output register, and finally extracting the conditional jump structure composed of conditional jump instructions and the variable dependency chain reflecting the variable life cycle relationship from the program code containing timing constraints.

[0061] S2.2, analyze the timing constraints in the program code, extract the scan period constraint value, combine the conditional jump structure and the variable dependency chain, and generate a semantic structure containing timing markers;

[0062] It should be noted that the timing constraint marker (such as / * TIMING_WINDOW=10ms * / ) is identified to extract the scan period constraint value, and then the branch instruction (such as the JNZ instruction of the x86 architecture) in the conditional jump structure is mapped to the timing unit boundary, and at the same time, according to the register transmission relationship in the variable dependency chain (such as the variable dependency chain 0x1A formed by MOV R1, R2→ADD R2, R3), a timing synchronization marker (such as SYNC_DATA 0xE2) is inserted at the key data intersection point; finally, a hierarchical semantic structure is generated, the top layer is the scan period constraint value (such as 200ms), the middle layer is the timing segment divided by the conditional jump structure (example: divide the PID control branch 0x71 and the alarm branch 0x72 into 5ms execution units), and the bottom layer is the instruction sequence with variable dependency markers (example: MOV R0, R1 is marked as DATAFLOW_CHAIN 0x01).

[0063] It should be noted that the key data intersection point refers to a logical node in the execution process of the industrial control program that multiple independent data streams must be synchronized. In the industrial control configuration cloud compilation process, the key data intersection point is identified through static dependency graph analysis, which is specifically manifested as the intersection position of multiple variable dependency chains in the program code. For example, the intersection of temperature sensor data and pressure sensor data at the input end of the PID control algorithm constitutes a typical key data intersection point. The determination of the key data intersection point is based on three core elements: first, the data stream must come from different source points and have independent timing characteristics, such as sensor data updated at 10ms and 5ms periods respectively; second, the data after intersection will directly affect the control logic execution, such as the logical AND operation of the emergency stop signal and the device state signal; finally, it must meet the strict time synchronization requirement, such as the synchronization deviation of multi-channel AD sampling data not exceeding 5μs.

[0064] S2.3, based on the time sequence mark containing semantic structure, the operation code to node mapping conversion and dependency analysis are carried out, and the parsed time sequence constraint is injected into the node and the edge, and the node set and the edge set of the primary logic flow graph containing the time sequence mark are generated;

[0065] It should be noted that by accurate mapping of instruction operation code to node, each instruction operation code (such as timer operation code TON 0x51) is converted into a unique logic flow graph node (such as node ID 0x205), and the operation code type and operand information (such as node 0x205 recording the timing parameter 10ms) are recorded; At the same time, the dependency relationship is deeply analyzed, and the variable dependency chain (such as the continuous data flow 0x2B from register R2 to R5) is converted into a directed edge with data flow direction mark (such as edge ID 0x302 marked as DATA_FLOW 0x2B). Subsequently, the time sequence constraint injection is carried out, the scan cycle constraint value (such as 100ms) is decomposed into node execution time slot (such as node 0x205 is allocated 2ms time slot), the time sequence mark (such as SYNC_IO 0xD1) is converted into edge constraint condition (such as edge 0x302 adds synchronous waiting constraint), and finally the generated primary logic flow graph contains: node set (example: 64 nodes with operation code attribute, time slot allocation) and edge set (example: 89 edges containing data dependency type, time sequence constraint condition), wherein each node accurately records the original operation code characteristics, and each edge completely retains the data flow and time sequence double constraint relationship.

[0066] S2.4, based on the node set and the edge set of the primary logic flow graph, the directed graph topology is constructed, and the logic flow graph atlas is generated.

[0067] It should be noted that the topological sorting of the node set of the primary logic flow graph (e.g., containing 48 nodes with opcode attributes) establishes the execution order relationship (e.g., ordering PID control node 0x301 after sensor reading node 0x205); then analyzing the dependency relationship in the edge set of the primary logic flow graph (e.g., 72 edges with data flow labels), adding path selection attributes (e.g., setting priority weight 0.8) to conditional jump edges (e.g., branch judgment edge 0x501), and adding flow control labels to data-dependent edges (e.g., register transfer edge 0x401) (e.g., setting transmission delay 5ms); and adding control labels according to industrial control specifications: conditional jump edges add path selection attributes: priority weight = base value 0.5 + execution frequency coefficient x 0.3 (example: emergency stop detection branch executes 15 / 20 scans → coefficient 0.75 → weight 0.8); data-dependent edges add flow control labels: transmission delay = base value 1ms + register bit width coefficient x 4ms (example: 32-bit register transmission → bit width coefficient 4 → delay 17ms → constraint upper limit 20ms), finally through connecting all sorted nodes and optimized edges, the complete logic flow graph is constructed, where the nodes retain the original opcode characteristics (e.g., node 0x205 retains the timer opcode TON 0x51 attribute), and the edges retain the complete timing and data constraints (e.g., edge 0x501 carries 10ms time window and DATA_FLOW 0x2B label).

[0068] S3, depth-first traversal of the logic flow graph, statistics instruction opcode frequency, calculate the information-intensive degree evaluation value of the program code;

[0069] S3.1, traverse the logic flow graph by depth-first traversal algorithm, statistics instruction opcode frequency in the logic flow graph nodes;

[0070] It should be noted that the depth-first traversal algorithm starts from the starting node (e.g., sensor reading node 0x101) and accesses each node (e.g., PID control node 0x301, motor drive node 0x402, etc.) in turn according to the connection relationship defined by the edge set (e.g., containing 89 timing constraint edges); during the traversal process, an instruction opcode frequency statistics table is maintained, and whenever a new node is accessed, the instruction opcode recorded in the node (e.g., PID control opcode 0x70 contained in node 0x301) is extracted, and the cumulative count in the frequency statistics table is performed (e.g., the number of occurrences of PID control opcode 0x70 is increased by 1); after completing the whole graph traversal, the statistics results containing all instruction opcodes and instruction opcode frequencies are output.

[0071] S3.2, based on the instruction opcode frequency in the logic flow graph nodes, calculate the information-intensive degree evaluation value, the expression is,

[0072] ;

[0073] wherein, N is the total number of nodes in the logic flow graph, O is the index variable of opcode type, O is the total number of opcode types, W is the weight value of the th opcode type, F is the frequency of the th opcode type in the logic flow graph, I is the index variable of the th node instance of the opcode type, W is the weight value of the th node instance, T is the scan period constraint value, I is the information intensity evaluation value.

[0074] It should be noted that all nodes in the logic flow graph are traversed to count the frequency of occurrence of instruction opcode types (e.g., MOV opcode occurs 15 times), and each opcode type is assigned a weight value based on instruction function criticality (such as emergency stop instruction), hardware execution overhead (such as floating point operation instruction) and safety level requirement (such as SIL3 related instruction) (e.g., MOV opcode weight is set to 1.2); for each node instance under each opcode type , the instance weight is assigned in combination with the node runtime attribute (e.g., the MOV node in the loop body is given a weight of 1.5 times); then the scan period constraint value (e.g., the standard value is 100ms) is used as a time factor for calculation; finally, the information intensity evaluation value is calculated.

[0075] It should be noted that the node runtime attribute includes timing position attribute (in loop body / interrupt service, etc.), data dependency attribute (critical path / non-critical path, etc.), safety isolation attribute (SIL3 level / regular partition, etc.) and real-time constraint attribute (≤1ms / ≤10ms response, etc.).

[0076] It should be noted that the scan period constraint value Scan period constraint value is the maximum allowed time interval for a programmable logic controller to execute all control logic completely, which is directly obtained by parsing the process requirements in the industrial control configuration engineering file. The specific determination method is as follows: first, the explicit declaration cycle parameter (for example, the 100 ms basic scan period set in the PLC configuration) is extracted from the configuration information of the configuration engineering file; when there are multiple rate tasks, the least common multiple of the cycle declared by each function block is taken as the global scan period constraint value (for example, the least common multiple of 100 ms of the motion control block cycle 20 ms and the temperature control block cycle 50 ms); for the logic block without explicit declaration cycle, the default value matched with the hardware performance of the target programmable logic controller is adopted according to the default rule of IEC 61131-3 standard (for example, 10 ms by default for small PLC). The final scan period constraint value T will be used as a key timing parameter in the subsequent information intensity evaluation and code optimization process, for example, T = 50 ms is determined in the packaging machine control program.

[0077] It should be noted that the assignment of the opcode type weight needs to be comprehensive of the function criticality level (high criticality instructions such as emergency stop ≥2.5, medium criticality such as closed-loop control 1.5≤ <2.5, low criticality such as data logging <1.5), hardware execution overhead (high overhead instructions such as floating point operations with a weight bonus of +0.8, medium overhead such as fixed point operations +0.4, low overhead such as bit operations +0), and safety level requirements (SIL3 level instructions +1.5, SIL2 level +1.0, no requirement +0), for example, the emergency stop instruction =2.5 (base) +0 (hardware) +1.5 (safety) =4.0; the node instance weight is then adjusted according to the timing position characteristics (nodes in the loop body = ×1.5, scan period start nodes ×1.2, interrupt service nodes ×2.0), data dependency strength (critical path nodes ×1.8, non-critical path ×1.0), safety isolation level (SIL3 partition nodes ×3.0, regular partition ×1.0), and real-time constraint strength (≤1 ms response nodes ×2.0, ≤10 ms response ×1.5), for example, the MOV instruction in the loop body =1.2×1.5=1.8; the industrial scene verification takes the automobile welding control program as an example: the welding gun temperature control instruction =1.8 (medium critical base) +0.4 (medium overhead) +1.0 (SIL2 level) =3.2, its temperature reading node (in the loop body + critical path) =3.2×(1.5×1.8)=8.64, the log recording node =3.2×1.0=3.2.

[0078] S4. compress and merge the high-frequency redundant instruction operation codes based on the information-intensive evaluation value, optimize the conditional jump structure of the logical flow graph, and generate an intermediate optimized code unit;

[0079] S4.1. based on the information-intensive evaluation value, analyze through the variable dependency chain, identify the high-frequency redundant instruction operation codes when the combination characteristics of the operation code type frequency and the operation code weight are lower than the instruction entropy threshold value, and perform equivalent logic merging and instruction semantic dimension reduction processing to generate a compressed instruction set;

[0080] It should be noted that the instruction entropy threshold value set according to the information-intensive evaluation value is used to screen the high-frequency redundant instruction operation codes, and the instruction entropy threshold value is defined as the critical value of the instruction distribution dispersion degree calculated based on the Shannon entropy model. Specifically, after calculating the information-intensive evaluation value, the information-intensive evaluation value is taken as 1.2 times the value of the information-intensive evaluation value (for example, when the reference entropy value is 2.3, the threshold value is 2.76). The instruction entropy threshold value is in the range of 1.5-3.0 (dimensionless). By counting the frequency of operation codes in the logical flow graph and associating the function weight assignment, when the frequency weight product of a certain operation code type is lower than the instruction entropy threshold value, the operation code is analyzed through the variable dependency chain to trace the repeated execution mode in the data flow path (such as reading and writing the same register for three times in a row). When the repetition mode exceeds the instruction entropy threshold value, it is determined as a high-frequency redundant instruction. Then, the variable dependency chain is analyzed to identify redundant instruction sequences with the same input-output relationship, such as performing AND operation on register R1 for three times in a row. Then, equivalent logic merging processing is performed to convert the redundant instruction sequence into a single composite logic instruction, such as merging three AND operations into a three-input AND instruction. At the same time, instruction semantic dimension reduction processing is performed to eliminate repeated bit operations and intermediate variable access operations. Finally, a compressed instruction set is generated that retains the original logical function but reduces the number of instructions.

[0081] S4.2. based on the topology relationship of the logical flow graph and the compressed instruction set, reconstruct the jump order through branch priority scheduling and bind the timing constraints, and output an optimized topology graph;

[0082] It should be pointed out that according to the topological connection relationship of the logic flow graph and the opcode distribution characteristics of the compressed instruction set, the execution path weight of the conditional branch node is analyzed, for example, the execution frequency proportion of the branch in the loop body reaches 60%; then the branch priority scheduling is implemented, the jump order is rearranged according to the path weight, for example, the high-frequency execution emergency stop detection branch is adjusted to the top of the judgment tree; at the same time, the scan cycle constraint value recorded in the semantic structure containing the time sequence mark is bound to the reconstructed jump path, for example, 5ms time limit slot is reserved for the motion control branch; finally, the optimized topology graph with optimized jump structure and strengthened time sequence attribute is output, which not only maintains the simplicity of the compressed instruction set, but also ensures the real-time response requirement of the industrial control logic.

[0083] It should be pointed out that the analysis of the conditional branch node first counts the historical execution times of each conditional branch node in the logic flow graph, for example, the emergency stop detection branch is executed 1200 times through the industrial controller runtime log record; then the execution frequency proportion of each branch path is calculated, the execution times of the branch node out edge are divided by the total execution times of the parent node to obtain the path weight, for example, when the total execution times of the loop body node are 2000, the execution times of a certain conditional branch are 1200, and the path weight is 60%; at the same time, combined with the real-time requirement marked in the semantic structure containing the time sequence mark, a weight correction factor is added to the branch path with strict time limit constraint, for example, a 30% weight coefficient is added to the alarm branch with 1ms response requirement; finally, the conditional branch node execution feature table containing path weight value and time criticality mark is generated, which provides quantitative basis for branch priority scheduling.

[0084] S4.3, the optimized topology graph is converted by reverse compilation, and combined with the scan cycle constraint value, an intermediate optimization code unit is generated.

[0085] It should be pointed out that the reverse compilation processing is implemented on the optimized topology graph, the directed graph structure with jump priority mark is converted into linear instruction sequence, for example, the loop structure in the optimized topology graph is converted into machine instruction with conditional jump; then the time sequence constraint parameter bound in the optimized topology graph is analyzed, the scan cycle constraint value is extracted and injected into the generated machine instruction sequence, for example, 10ms cycle synchronization mark is added to the motion control instruction block; at the same time, the correctness of the instruction conversion is verified according to the semantic rules of the compressed instruction set, to ensure that the logic function is completely consistent with the optimized topology graph; finally, the intermediate optimization code unit which not only retains the simplified jump structure of the optimized topology graph but also conforms to the specification of the target hardware instruction set is output.

[0086] S5, based on the intermediate optimization code unit, the topology dependence analysis is carried out and the local incremental compilation verification is implemented, and the executable machine code is generated.

[0087] S5.1, based on the intermediate optimization code unit, a static dependency graph is constructed, data dependency, control dependency and interrupt dependency are extracted, and are divided by real-time criticality and safety isolation boundary to generate a topological dependency partition map;

[0088] It should be noted that the instruction sequence and timing mark in the intermediate optimization code unit is parsed, and a static dependency graph structure is constructed, wherein the data dependency is established by tracking the variable read-write relationship (for example, the dependency edge formed by writing the PID operation value of the temperature sensor into the heater output register), the control dependency is determined by analyzing the dominance relationship of conditional jump instructions (for example, the execution of the subsequent device shutdown instruction is dominated by the emergency stop button state judgment instruction), and the interrupt dependency is identified according to the calling context of the interrupt service routine (for example, the variable dependency chain formed by the 5ms timer interrupt triggering the data acquisition task); then, the static dependency graph is regionally divided according to the real-time criticality index (such as marking the 1ms level critical control loop as RT1 level) and the safety isolation boundary requirement (such as dividing the safety interlocking logic into SIL2 isolation area); finally, a topological dependency partition map with clear partition attribute and dependency relationship is generated, wherein each partition node is marked with the corresponding real-time level and safety requirement, and the edge retains the original dependency type and intensity information, for example, a topological dependency partition map containing 12 functional partitions is formed in the automobile welding control program.

[0089] It should be noted that the real-time criticality is an index for quantifying the strictness of different control tasks to time constraints, which is divided into multiple levels: RT0 level represents no real-time requirement (such as log recording), RT1 level requires response time ≤1ms (such as emergency stop processing), RT2 level requires ≤10ms (such as motion control), and each level corresponds to different scheduling priority; the safety isolation boundary is a logically isolated area divided according to functional safety standards, for example, the SIL1 level general control logic and the SIL3 level safety interlocking logic are physically isolated in memory space and bus communication, and an independent watchdog timer is configured for each isolated area (such as 50ms timeout monitoring for SIL3 area), to ensure that the execution of high safety level function is not affected by low safety level function.

[0090] S5.2, based on the topological dependency partition map and the intermediate optimization code unit, the compilation mode is decided according to the industrial safety partition rule, and the real-time of data dependency, control dependency and interrupt dependency is verified in the virtual PLC environment, the back-end compilation optimization is performed, and the executable machine code is generated.

[0091] It should be noted that the real-time criticality and safety isolation boundary attribute in the analysis topology dependent partition map are parsed, the corresponding compilation mode is selected according to the industrial safety partition rule, for example, static memory allocation and instruction pipeline disable strategy are adopted for the node in RT1 level and located in SIL3 isolation area; then the intermediate optimization code unit is loaded in the virtual PLC environment, and the real-time constraint satisfaction of data dependency (such as verifying the 1ms transmission delay of sensor data to actuator output), control dependency (such as testing the 2ms shutdown of all outputs of emergency stop signal) and interrupt dependency (such as confirming the on-time triggering of 5ms timing interrupt service routine) are verified through cycle accurate simulation; finally, based on the verification result, the back-end compilation optimization is implemented, including reserving special registers for RT1 level nodes, inserting memory protection instructions for SIL3 isolation area, etc., and finally executable machine code meeting the target hardware architecture and satisfying the industrial real-time and safety requirements is generated.

[0092] It should be noted that the industrial safety partition rule is a control program function isolation specification established according to IEC 61508 and IEC 61131 standards, which specifically includes three types of mandatory requirements: memory isolation requirements stipulate that different safety level partitions must use independent address spaces (such as SIL3 area allocating 0x2000-0x3FFF dedicated memory segment), timing isolation requirements ensure that high real-time partitions are not disturbed by low priority tasks (such as RT1 level partition exclusively occupying 10% of CPU time slice), and functional safety requirements force to insert protection instructions at partition boundaries (such as adding three-mode redundant comparison instructions between SIL2 and SIL3 areas). The control program function isolation specification forms a partition template through the matrix combination of safety integrity level (SIL1-SIL4) and real-time level (RT0-RT3), for example, the safety interlock partition in the automobile welding control program must simultaneously satisfy the dual constraints of SIL3 safety level and RT1 real-time level.

[0093] The embodiment also provides an industrial control system configuration cloud compilation system, which comprises a cloud file parsing module, an information intensity evaluation module, a graph optimization module and a partition compilation module,

[0094] The cloud file parsing module collects and parses industrial control configuration engineering files in the cloud in real time, extracts instruction operation codes, and generates program codes through target hardware instruction set mapping and logical timing arrangement;

[0095] The logical flow graph generation module performs semantic analysis and data flow tracking on the program codes to generate a logical flow graph;

[0096] The information intensity evaluation module performs depth-first traversal on the logical flow graph, counts the frequency of occurrence of instruction operation codes, and calculates the information intensity evaluation value of the program codes;

[0097] The atlas optimization module compresses and merges high-frequency redundant instruction operation codes, optimizes conditional jump structures of the logical flow atlas based on information-intensive evaluation values, and generates intermediate optimized code units.

[0098] The partition compiling module performs topological dependency analysis and implements local incremental compiling verification based on the intermediate optimized code units, and generates executable machine code.

[0099] The embodiment also provides a computer device suitable for the case of the industrial control system configuration cloud compiling method, including a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the industrial control system configuration cloud compiling method proposed in the above embodiment.

[0100] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, an operator network, NFC (near field communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0101] The embodiment also provides a storage medium, which stores a computer program, and the computer program is executed by a processor to implement the cloud compiling method for implementing the industrial control system configuration as proposed in the above embodiment; the storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk, or an optical disk.

[0102] In summary, the present application is capable of accurately identifying high-frequency redundant operation codes and performing semantic-level compression and merging by calculating the information-intensive evaluation value of the program code, thereby generating a reliable and simplified control program code while maintaining the industrial hard real-time constraint condition; and the influence of the change domain is verified in a virtual PLC environment, thereby realizing the non-interrupted online update and accurate compilation range reduction of the industrial configuration engineering.

[0103] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and all of them should be covered in the scope of the claims of the present application.

Claims

1. A method for compiling configuration cloud for an industrial control system, characterized in that: Comprise: The cloud real-time acquisition and analysis of industrial control configuration engineering files, extract instruction operation code, and through the target hardware instruction set mapping and logical timing arrangement, generate program code; The semantic analysis and data flow tracking of program code, generate logical flow graph, the specific steps are as follows: Based on the program code containing timing constraints, control flow analysis and data flow tracking, extract conditional jump structure and variable dependency chain; Parse the timing constraints in the program code, extract the scan period constraint value, combine the conditional jump structure and variable dependency chain, and generate the semantic structure containing timing markers; Based on the semantic structure containing timing markers, perform operation code to node mapping conversion and dependency relationship analysis, and inject the parsed timing constraints into the nodes and edges, generate the node set and edge set of the primary logical flow graph containing timing markers; Based on the node set and edge set of the primary logical flow graph, construct the directed graph topology, generate the logical flow graph; Depth-first traversal of the logical flow graph, count the frequency of instruction operation code, calculate the information-intensive degree evaluation value of the program code; Based on the information-intensive evaluation value, analyze the frequency of operation code type and the distribution characteristics of operation code weight, and compare the results with the instruction entropy threshold value, identify high-frequency redundant instruction operation code, and optimize the conditional jump structure of the logical flow graph, generate intermediate optimized code unit, the specific steps are as follows: Based on the information-intensive evaluation value, analyze through the variable dependency chain, when the combination characteristics of operation code type frequency and operation code weight are lower than the instruction entropy threshold value, identify high-frequency redundant instruction operation code, and perform equivalent logical merging and instruction semantic dimension reduction processing, generate compressed instruction set; Based on the topology relationship of the logical flow graph and the compressed instruction set, reconstruct the jump order through branch priority scheduling and bind the timing constraints, output the optimized topology graph; Convert the optimized topology graph through reverse compilation, and generate the intermediate optimized code unit combined with the scan period constraint value; Based on the intermediate optimized code unit, perform topology dependency analysis and implement local incremental compilation verification, generate executable machine code.

2. The industrial control system configuration cloud compiling method of claim 1, wherein: The industrial control configuration engineering file includes graphical logic, textual program, hardware configuration, communication parameter, variable database and process parameter configuration file.

3. The method of claim 2, wherein the configuration cloud is a cloud-based configuration cloud. The specific steps of generating program code are as follows: Based on the industrial control configuration engineering file, real-time multi-format streaming analysis and semantic deconstruction are performed to extract instruction operation code; Based on the instruction operation code, perform target hardware instruction set mapping conversion and industrial control logic timing arrangement to generate program code containing timing constraints.

4. The industrial control system configuration cloud compiling method of claim 1, wherein: The specific steps of depth-first traversal of the logical flow graph, counting the frequency of instruction operation code, calculating the information-intensive degree evaluation value of the program code are as follows: Through the depth-first traversal algorithm, traverse the logical flow graph, and count the frequency of instruction operation code in the logical flow graph nodes; Based on the frequency of instruction operation code in the logical flow graph nodes, calculate the information-intensive degree evaluation value.

5. The industrial control system configuration cloud compilation method of claim 1, wherein: The specific steps of based on the intermediate optimized code unit, performing topology dependency analysis and implementing local incremental compilation verification, generating executable machine code are as follows: Based on the intermediate optimization code unit, a static dependency graph is constructed, data dependency, control dependency and interrupt dependency are extracted, and topological dependency partition atlas is generated by dividing through real-time criticality and safety isolation boundary; Based on the topological dependency partition atlas and the intermediate optimization code unit, the compilation mode is decided according to the industrial safety partition rule, the real-time of data dependency, control dependency and interrupt dependency is verified in the virtual PLC environment, the back-end compilation optimization is carried out, and the executable machine code is generated.

6. An industrial control system configuration cloud compiling system, which implements the industrial control system configuration cloud compiling method according to any one of claims 1-5, characterized in that: It includes a cloud file analysis module, an information intensive degree evaluation module, a graph optimization module and a partition compilation module. The cloud file analysis module collects and analyzes industrial control configuration engineering files in real time, extracts instruction operation codes, and generates program codes through target hardware instruction set mapping and logical timing arrangement. The logical flow graph generation module performs semantic analysis and data flow tracking on the program code to generate a logical flow graph. The information intensive degree evaluation module performs depth-first traversal on the logical flow graph, counts the frequency of instruction operation codes, and calculates the information intensive degree evaluation value of the program code. The graph optimization module analyzes the frequency of operation code types and the distribution characteristics of operation code weights based on the information intensive evaluation value, combines the comparison results of instruction entropy threshold, identifies high-frequency redundant instruction operation codes, compresses and merges the high-frequency redundant instruction operation codes, optimizes the conditional jump structure of the logical flow graph, and generates an intermediate optimization code unit. The partition compilation module performs topological dependency analysis and local incremental compilation verification based on the intermediate optimization code unit to generate executable machine code. 7.A computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the computer device is characterized in that: The processor executes the computer program to realize the steps of the industrial control system configuration cloud compilation method of any one of claims 1-5.

8. A computer readable storage medium having stored thereon a computer program, characterized in that: The computer program is executed by the processor to realize the steps of the industrial control system configuration cloud compilation method of any one of claims 1-5.

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