Camera master control FPGA (Field Programmable Gate Array) multi-mode on-orbit program upgrading method based on dynamic reconstruction

Abstract

The invention discloses a camera master control FPGA (Field Programmable Gate Array) multi-mode on-orbit program upgrading method based on dynamic reconstruction, relates to the technical field of camera master control processor program on-orbit upgrading, and solves the problem of upgrading of a master control processor FPGA in an existing camera master control single machine. According to the method, on-orbit program upgrading can be carried out on the camera master control main processor FPGA by adopting six modes based on a dynamic reconstruction strategy according to a stand-alone upgrading feedback result. When the DSP breaks down, on-orbit upgrading of an FPGA program can still be achieved through three modes of functions of the FPGA, when the FPGA breaks down, on-orbit upgrading of the FPGA program is achieved through one of the two upgrading modes of the DSP, in this way, even if the FPGA cannot load the program, on-orbit upgrading of the FPGA program can be achieved, and then the FPGA can recover working after the camera main control single machine is restarted. The problem that a camera master control single machine cannot meet task requirements due to upgrading failure caused by a single-mode upgrading method is avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of on-orbit upgrade of camera main control processor programs, and in particular to a method for on-orbit upgrade of camera main control processor FPGA programs in multiple modes based on a dynamic reconstruction strategy. Background Art

[0002] The camera master controller (CMC) on a satellite platform is the primary control unit for the camera payload. It is responsible for mission management and scheduling, data storage, and communication, and is a crucial component of the satellite's camera payload. Its primary functions include mission scheduling and control, parameter configuration and optimization, data processing and storage, status monitoring and fault handling, thermal management and data acquisition, and collaboration with other subsystems.

[0003] During in-orbit operation, the camera controller remains powered on at all times. Due to various factors, its processor program may require an in-orbit upgrade. For example, exposure to space particles and cosmic rays can easily cause single-event upsets, latch-ups, and breakdowns, resulting in temporary or permanent failure of electronic components. Alternatively, changes in mission requirements may necessitate an upgrade of the camera controller's program code. Alternatively, bugs may be discovered in the camera controller's program code while in orbit. However, the program upgrade method and strategy directly determine the success of the upgrade, and thus the reliability and lifespan of the camera controller. This code can be updated through in-orbit program upgrades. After the upgrade, the camera controller processor runs the new program, ensuring the normal operation of the camera controller.

[0004] Based on the above factors, the present invention proposes a multi-mode on-orbit program upgrade method for camera master control FPGA based on dynamic reconstruction. Summary of the Invention

[0005] In order to solve the problem of on-orbit upgrade of the main control processor FPGA program in the existing camera main control stand-alone machine, the present invention provides a camera main control FPGA multi-mode on-orbit program upgrade method based on dynamic reconstruction.

[0006] A multi-mode on-orbit program upgrade method for the camera master FPGA based on dynamic reconstruction is implemented as follows:

[0007] The satellite computer in the satellite platform sends the camera main control FPGA program code to the coprocessor DSP or main processor FPGA in the camera main control through the RS422 bus, and then transmits it to the refresh readback dedicated chip through the coprocessor DSP or main processor FPGA in multi-mode. The refresh readback dedicated chip burns the FPGA program code into the parallel port FLASH1 or FLASH2 connected to it, realizing on-orbit upgrade of the program code.

[0008] Furthermore, multimode transmission includes six modes, which are as follows:

[0009] Mode 1: The satellite's onboard computer sends the camera's main control FPGA program code to the coprocessor DSP in the camera's main control via the RS422 bus. The DSP stores the FPGA program code in SPI FLASH2. Once all the program code has been received, the DSP reads the FPGA program code from SPI FLASH2 and sends it to the dedicated refresh readback chip via serial port B. The dedicated refresh readback chip then burns the FPGA program code into the connected parallel port FLASH1 or FLASH2, thus enabling on-orbit program code upgrades.

[0010] Mode 2: The satellite platform's onboard computer sends the camera's main control FPGA program code via the RS422 bus to serial port A of the camera's main control coprocessor DSP. The DSP directly transparently transmits the data from serial port A to serial port B, which then sends it to the dedicated refresh readback chip. The dedicated refresh readback chip then burns the FPGA program code into the connected parallel port FLASH1 or FLASH2, thus enabling on-orbit program code upgrades.

[0011] Mode 3: The satellite computer in the satellite platform sends the camera master FPGA program code to serial port 1 of the main processor FPAG in the camera master through the RS422 bus. The FPGA then transmits the data in serial port 1 to the coprocessor DSP through the EMIF interface, and the DSP stores the FPGA program code in SPIFLASH2. When all the program codes have been received, the DSP reads the FPGA program code from SPIFLASH2 and sends it to the refresh readback dedicated chip through serial port B. The refresh readback dedicated chip burns the FPGA program code into the parallel port FLASH1 or FLASH2 connected to it, thereby realizing the on-orbit upgrade of the program code;

[0012] Mode 4: The satellite platform's onboard computer sends the camera master FPGA program code to serial port 1 of the main processor FPAG in the camera master via the RS422 bus. The FPGA stores the program code in SPI FLASH1. Once all the program code has been received, the FPGA reads the FPGA program code from SPI FLASH1 and sends it to the dedicated refresh readback chip via serial port 2. The dedicated refresh readback chip then burns the FPGA program code into the connected parallel port FLASH1 or FLASH2, thus enabling on-orbit program code upgrades.

[0013] Mode 5: The satellite computer on the satellite platform sends the camera master FPGA program code via the RS422 bus to serial port 1 of the main processor FPGA in the camera master. The FPGA directly transparently transmits the data from serial port 1 to serial port 2. Through serial port 2, it sends the data to the dedicated refresh readback chip. The dedicated refresh readback chip burns the FPGA program code into the connected parallel port FLASH1 or FLASH2, thus achieving on-orbit program code upgrades.

[0014] Mode 6: The satellite computer in the satellite platform sends the camera master FPGA program code to the main processor FPGA in the camera master through the RS422 bus. The FPGA directly connects the RX pin input from the RS422 interface circuit 1 with the TX pin output by the FPGA, and directly connects the TX pin output by the FPGA with the RX pin input from the serial port S of the refresh readback dedicated chip. That is, the satellite platform directly sends the camera master FPGA program code to the refresh readback dedicated chip via RS422 through the FPGA. The refresh readback dedicated chip burns the FPGA program code into the parallel port FLASH1 or FLASH2 connected to it, thereby realizing the on-orbit upgrade of the program code;

[0015] If the camera's main FPGA program code is successfully upgraded on-orbit, the camera will provide feedback to the satellite's onboard computer via the FPGA or DSP. Otherwise, the onboard computer will dynamically reconfigure according to the six on-orbit program upgrade strategies described above until the camera's main FPGA program is successfully upgraded.

[0016] Beneficial effects of the present invention:

[0017] The on-orbit program upgrade method described in the present invention adopts different reconstruction strategies according to different working conditions and program upgrade feedback results, and uses a coprocessor DSP or a main processor FPGA and related peripheral circuits to realize on-orbit upgrade of the main processor FPGA program code, thus solving the problem of on-orbit upgrade of the camera main control FPGA program.

[0018] The on-orbit program upgrade method described in this paper, based on a dynamic reconfiguration strategy, can employ six modes to perform on-orbit program upgrades on the main processor FPGA. This method avoids the upgrade failures caused by using a single on-orbit program upgrade method, which can result in a single camera controller being unable to meet mission requirements.

[0019] The upgrade method adopted by the present invention can utilize the functions of the FPGA itself to implement three modes of on-orbit upgrade of the FPGA program (mode four, mode five, and mode six) when the DSP fails. When the FPGA itself is used for the upgrade, the upgrade failure caused by the single-mode upgrade method is avoided, which results in the camera main control unit being unable to meet the task requirements.

[0020] The upgrade method adopted by the present invention can use DSP to adopt one of two upgrade modes (mode 1 and mode 2) to implement on-track upgrade of FPGA program when FPGA fails. In this way, even if the FPGA cannot load the program, the on-track upgrade of FPGA program can be implemented, and then the camera main control unit can be restarted to resume operation of FPGA.

[0021] The upgrade method adopted by the present invention realizes on-track upgrade of FPGA program (mode three) through the cooperation of the two processors when both FPGA and DSP functions are normal.

[0022] In the above six modes, no matter it is an FPGA failure, a DSP failure, a SPIFLASH1 failure, or a SPIFLASH2 failure, the dynamic reconstruction upgrade method in the method of the present invention can realize the on-orbit upgrade of the FPGA program, which greatly improves the reliability of the on-orbit upgrade of the camera master FPGA main processor program. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0024] Figure 1 This is a schematic diagram of the hardware structure related to the camera master FPGA multi-mode on-orbit program upgrade of the present invention;

[0025] Figure 2 This is a schematic diagram of the camera master FPGA on-orbit program upgrade mode 1 of the present invention;

[0026] Figure 3 This is a schematic diagram of the second mode of on-orbit program upgrade of the camera master FPGA according to the present invention;

[0027] Figure 4 This is a schematic diagram of the third on-orbit program upgrade mode of the camera master FPGA according to the present invention;

[0028] Figure 5 This is a schematic diagram of the fourth mode of on-orbit program upgrade of the camera master FPGA according to the present invention;

[0029] Figure 6 This is a schematic diagram of the fifth mode of on-orbit program upgrade of the camera master FPGA according to the present invention;

[0030] Figure 7 Schematic diagram of the camera master FPGA on-orbit program upgrade mode 6 according to the present invention;

[0031] Figure 8 This is a schematic diagram of the program code storage location in the camera master FPGA on-orbit program upgrade mode described in the present invention. DETAILED DESCRIPTION

[0032] Combine Figures 1 to 8 This embodiment describes a multi-mode on-orbit program upgrade method for a camera master FPGA based on dynamic reconstruction. The hardware architecture of this method is as follows: Figure 1 shown.

[0033] There are two processors in the camera main control, of which FPGA is the main processor and DSP is the coprocessor. Serial port 1 of the main processor FPGA communicates with the satellite platform via RS422 interface circuit 1 via RS422. The main processor FPGA is connected to serial port S of the refresh readback dedicated chip via serial port 2. The refresh readback dedicated chip is connected to two parallel port FLASHs (FLASH1 and FLASH2) via a 16-bit parallel port. These two parallel port FLASHs are used to store the program code of the main processor FPGA. The main processor FPGA is also connected to the refresh readback dedicated chip via an 8-bit parallel port. When the camera main control is powered on, the main processor FPGA loads the FPGA program code from a certain address in one of the two parallel port FLASHs through the refresh readback dedicated chip until the code is loaded and the FPGA is started. The main processing FPGA is also connected to SPI FLASH1 via the SPI interface for temporarily storing the FPGA program code. The main processing FPGA is also connected to the coprocessor DSP via the EMIF interface for transmitting FPGA program code or other data;

[0034] The coprocessor DSP's serial port A also communicates with the satellite platform via RS422 interface circuit 2. The coprocessor DSP also connects to serial port S of a dedicated refresh readback chip via serial port B. Furthermore, the coprocessor connects to two parallel FLASH chips via the chip's 16-bit parallel port for reading and writing FPGA program code, enabling on-orbit program upgrades. The coprocessor DSP connects to SPIFLASH2 via an SPI interface for temporary storage of FPGA program code.

[0035] In this embodiment, the specific modes of dynamically reconfigured camera master FPGA on-orbit program upgrade are as follows:

[0036] The first mode: Figure 2As shown, the satellite control computer on the satellite platform encodes the camera control FPGA program code according to the agreed communication protocol and then sends it to the camera control via the RS422 bus. The camera control coprocessor DSP receives data from RS422 interface circuit 2 via serial port A. The DSP decodes the received data according to the communication protocol and temporarily stores the decoded FPGA program code data in SPIFLASH2, which is connected to it, via the SPI interface until the satellite control computer has received all the program code from the camera control FPGA. The DSP then reads the camera control FPGA program code from SPIFLASH2 via the SPI interface, encodes it according to the fixed communication protocol, and sends it via serial port B to serial port S of the connected refresh readback chip. The refresh readback chip receives the camera control FPGA program code data via serial port S and, based on the relevant register configuration parameters, burns the camera control FPGA program code into parallel port FLASH1 or parallel port FLASH2, thus enabling on-orbit program code upgrades.

[0037] The second mode: Figure 3 As shown in the figure, the satellite platform's onboard computer encodes the camera master control FPGA program code according to a fixed communication protocol and then transmits it to the camera master control via the RS422 bus. The camera master control's coprocessor DSP receives data from RS422 interface circuit 2 via serial port A. Without decoding the received data, the DSP directly forwards it via serial port B to serial port S of a connected dedicated refresh readback chip. The dedicated refresh readback chip receives the FPGA program code data via serial port S and, based on the relevant register configuration parameters, burns the FPGA program code into parallel port FLASH1 or parallel port FLASH2, thus enabling on-orbit program code upgrades.

[0038] The third mode: Figure 4As shown, the satellite platform's onboard computer encodes the camera master control FPGA program code according to the agreed communication protocol and then transmits it to the camera master control via the RS422 bus. The camera master control's main processor FPGA receives data from RS422 interface circuit 1 via serial port 1. The main processor FPGA decodes the received data according to the communication protocol and transmits the decoded FPGA program code data to the connected coprocessor DSP via the EMIF interface. The DSP temporarily stores the received FPGA program code data in its connected SPIFLASH2 via the SPI interface until the onboard computer has transmitted the entire FPGA program code. The DSP then reads the FPGA program code from SPIFLASH2 via the SPI interface, encodes it according to a fixed communication protocol, and transmits it via serial port B to serial port S of the connected refresh readback dedicated chip. The refresh readback dedicated chip receives the FPGA program code data via serial port S and, based on the relevant register configuration parameters, burns the FPGA program code into parallel port FLASH1 or parallel port FLASH2, thus enabling on-orbit program code upgrades.

[0039] The fourth mode: Figure 5 As shown, the satellite platform's onboard computer encodes the camera master control FPGA program code according to the agreed communication protocol and then transmits it to the camera master control via the RS422 bus. The camera master control's main processor FPGA receives data from RS422 interface circuit 1 via serial port 1. The main processor FPGA decodes the received data according to the communication protocol and temporarily stores the decoded FPGA program code data in SPIFLASH1, which is connected to it, via the SPI interface until the satellite platform computer has transmitted the entire FPGA program code. The main processor FPGA then reads the FPGA program code from SPIFLASH1 via the SPI interface, encodes it according to the fixed communication protocol, and transmits it via serial port 2 to serial port S of the dedicated refresh readback chip connected to it. The dedicated refresh readback chip receives the FPGA program code data via serial port S and, based on the relevant register configuration parameters, burns the FPGA program code into parallel port FLASH1 or parallel port FLASH2, thus enabling on-orbit program code upgrades.

[0040] The fifth mode: Figure 6As shown, the satellite computer in the satellite platform encodes the camera master FPGA program code according to a fixed communication protocol and then sends it to the camera master via the RS422 bus. The main processor FPGA in the camera master receives data from RS422 interface circuit 1 via serial port 1. The main processor FPGA does not need to decode the received data and directly forwards it to serial port S of the connected refresh readback dedicated chip via serial port 2. The refresh readback dedicated chip receives the FPGA program code data via serial port S and, based on the relevant register configuration parameters, burns the FPGA program code into parallel port FLASH1 or parallel port FLASH2, thereby realizing on-orbit program code upgrades.

[0041] The sixth mode: Figure 7 As shown, the satellite platform's onboard computer encodes the camera master control FPGA program code according to a specific communication protocol and then transmits it to the camera master control via the RS422 bus. The camera master control's main processor FPGA no longer receives data from RS422 interface circuit 1 via serial port 1. Instead, the main processor FPGA's internal logic directly connects the input RX pin of RS422 interface circuit 1 to the FPGA's output TX pin, and vice versa. In other words, the satellite platform connects directly to serial port S of the refresh readback dedicated chip via RS422, via the FPGA, and transmits the camera master control FPGA program code directly to the refresh readback dedicated chip. The refresh readback dedicated chip then burns the FPGA program code into parallel port FLASH1 or FLASH2 based on the relevant register configuration parameters, thus enabling on-orbit program code upgrades.

[0042] If the camera's main FPGA program code is successfully upgraded on-orbit, the camera will provide feedback to the satellite's onboard computer via the FPGA or DSP. Otherwise, the onboard computer will dynamically reconfigure according to the six on-orbit program upgrade strategies described above until the camera's main FPGA program is successfully upgraded.

[0043] like Figure 8As shown, in this embodiment, the parallel port FLASH1 and parallel port FLASH2 are used to store FPGA program code, and the capacity of each parallel port FLASH is 256MB, which is evenly divided into two 128MB address spaces. In this way, the two parallel port FLASHes can store four copies of FPGA program code. The lower 128MB of the parallel port FLASH1 stores the FPGA program code with version number 1, and the upper 128MB stores the FPGA program code with version number 2. The lower 128MB of the parallel port FLASH2 stores the FPGA program code with version number 3, and the upper 128MB stores the FPGA program code with version number 4. To ensure the security of the program, the FPGA program version 1 and version 3 in the parallel port FLASH1 and parallel port FLASH2 are used as the original versions, and the program code cannot be upgraded. The FPGA program code in the FLASH area where version 2 and version 4 are located can be upgraded on-track, which can not only ensure the security of the original program, but also realize the on-track upgrade of the program.

[0044] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0045] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A multi-mode on-orbit program upgrade method for the camera master control FPGA based on dynamic reconstruction, characterized by: The implementation process of this method is: The satellite computer in the satellite platform sends the camera main control FPGA program code to the coprocessor DSP or main processor FPGA in the camera main control through the RS422 bus, and then transmits it to the refresh readback dedicated chip through the coprocessor DSP or main processor FPGA in multi-mode. The refresh readback dedicated chip burns the FPGA program code into the parallel port FLASH1 or FLASH2 connected to it, realizing on-orbit upgrade of the program code.

2. The method for on-orbit program upgrade of a camera master control FPGA based on dynamic reconstruction according to claim 1, characterized in that: Multi-mode delivery includes: The camera master FPGA program code is sent to the serial port A of the coprocessor DSP in the camera master through the RS422 bus. The coprocessor DSP decodes the received data and stores the decoded FPGA program code in SPIFLASH2. When all FPGA program codes are received, the coprocessor DSP reads the FPGA program code from SPI FLASH2 and encodes it, and sends it to the refresh readback dedicated chip through serial port B.

3. The method for on-orbit program upgrade of a camera master control FPGA in multiple modes based on dynamic reconstruction according to claim 1, characterized in that: Multi-mode delivery includes: The camera master FPGA program code is sent to the serial port A of the coprocessor DSP in the camera master through the RS422 bus. The coprocessor DSP directly transmits the data in serial port A to the serial port B, and sends it to the refresh readback dedicated chip through serial port B.

4. The method for on-orbit program upgrade of a camera master control FPGA in multiple modes based on dynamic reconstruction according to claim 1, characterized in that: Multi-mode delivery includes: The camera master FPGA program code is sent to serial port 1 of the main processor FPAG in the camera master through the RS422 bus. The main processor FPGA decodes the received data and transmits the decoded FPGA program code data to the coprocessor DSP through the EMIF interface. The coprocessor DSP stores the FPGA program code in SPIFLASH2. When all FPGA program codes are received, the coprocessor DSP reads the FPGA program code from SPIFLASH2 and sends it to the refresh readback dedicated chip through serial port B.

5. The method for on-orbit program upgrade of a camera master control FPGA in multiple modes based on dynamic reconstruction according to claim 1, characterized in that: Multi-mode delivery includes: The camera master FPGA program code is sent to serial port 1 of the main processor FPAG in the camera master through the RS422 bus. The main processor FPGA decodes the received data and stores the decoded FPGA program code in SPIFLASH1. When all FPGA program codes are received, the main processor FPGA reads the FPGA program code from SPI FLASH1 and sends it to the refresh readback dedicated chip through serial port 2.

6. The method for on-orbit program upgrade of a camera master control FPGA in multiple modes based on dynamic reconstruction according to claim 1, characterized in that: Multi-mode delivery includes: The camera master FPGA program code is sent to the serial port 1 of the main processor FPGA in the camera master through the RS422 bus. The main processor FPGA directly transmits the data in serial port 1 to the serial port 2, and sends it to the refresh readback dedicated chip through serial port 2.

7. The method for on-orbit program upgrade of a camera master control FPGA in multiple modes based on dynamic reconstruction according to claim 1, characterized in that: Multi-mode delivery includes: The camera master FPGA program code is sent to the main processor FPGA in the camera master through the RS422 bus. The FPGA directly connects the RX pin input from the RS422 interface circuit 1 with the TX pin output by the FPGA, and directly connects the TX pin output by the FPGA with the RX pin input from the serial port S of the refresh readback dedicated chip; that is, the satellite platform directly sends the camera master FPGA program code to the refresh readback dedicated chip through the RS422 bus through the FPGA.

8. The method for on-orbit program upgrade of a camera master control FPGA in multiple modes based on dynamic reconstruction according to claim 1, characterized in that: The camera main control includes two processors. The serial port 1 of the main processor FPGA communicates with the satellite platform via RS422 interface circuit 1. The main processor FPGA is connected to the serial port S of the refresh readback dedicated chip via serial port 2. The refresh readback dedicated chip is connected to two parallel port FLASH chips via a 16-bit parallel port. The two parallel port FLASH chips are used to store the program code of the main processor FPGA. The main processor FPGA is connected to the refresh readback dedicated chip via an 8-bit parallel port. When the camera main controller is powered on, the main processor FPGA starts loading the FPGA program code from a certain address in one of the two parallel port FLASHs by refreshing the readback dedicated chip until the code is loaded and the FPGA is started; The main processing FPGA is connected to SPI FLASH1 through the SPI interface to temporarily store the FPGA program code; The main processing FPGA is connected to the coprocessor DSP through the EMIF interface for transmitting FPGA program code or other data.

9. The method for on-orbit program upgrade of a camera master control FPGA in multiple modes based on dynamic reconstruction according to claim 1, characterized in that: The serial port A of the coprocessor DSP performs RS422 communication with the satellite platform through the RS422 interface circuit 2; the coprocessor DSP is connected to the serial port S of the refresh readback dedicated chip through the serial port B, and is connected to two parallel port FLASHs through the 16-bit parallel port of the refresh readback dedicated chip, for operating the reading and writing of FPGA program codes and realizing on-orbit program upgrades; the coprocessor DSP is connected to SPIFLASH2 through the SPI interface for temporarily storing FPGA program codes.

10. The method for multi-mode on-orbit program upgrade of camera master control FPGA based on dynamic reconstruction according to claim 1, characterized in that: Parallel FLASH1 and parallel FLASH2 are used to store FPGA program code. The capacity of each parallel FLASH is 256MB, which is evenly divided into two 128MB address spaces.

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