Cache management method, system and storage medium

Abstract

This invention relates to the field of cache technology, and particularly to a cache management method, system, and storage medium. The cache management method includes the following steps: establishing a multi-way set-associative cache, where each way in the multi-way set-associative cache is used to simultaneously store cache information and replacement information; accessing the cache directory and replacement directory of the multi-way set-associative cache in parallel; determining whether the processor's current access data results in a cache hit based on the cache information; and determining whether there are any free ways in the multi-way set-associative cache; selecting the way in the multi-way set-associative cache that needs to be replaced based on the replacement information and the determination result using a replacement algorithm; updating the cache information and replacement information of the multi-way set-associative cache based on the current access data, the hit result, the determination result, and the replacement target; and writing the replacement result back to memory. Compared with existing technologies, this invention effectively improves the cache access rate and bandwidth, and reduces hardware overhead.

Description

Technical Field

[0001] This invention relates to the field of caching technology, and in particular to a cache management method, system and storage medium. Background Technology

[0002] The rapid development of computer systems has led to a significant improvement in the performance of processors (such as central processing units, CPUs). However, the relative lag in memory technology development has resulted in a widening gap between processor cycle time and memory access latency, thus creating the "memory wall" problem. To address this issue, in addition to memory, modern processor architectures have introduced multi-level cache structures to improve memory access efficiency.

[0003] Caches are located closer to the CPU within the processor chip and offer higher read / write speeds, resulting in significantly lower CPU latency for cache access compared to main memory access. However, caches have a much higher transistor count than main memory, meaning their capacity is much smaller, and they can only store a portion of the data in main memory. Due to these storage characteristics, caches tend to store data more likely to be used by the CPU while replacing less frequently used data to improve cache hit rates. This cache management strategy is known as a cache replacement algorithm or replacement policy.

[0004] Currently, widely used replacement algorithms in the processor field include LRU (Least Recently Used) and DRRIP (Dynamic Re-Reference Interval Prediction). These algorithms determine how to replace data by recording the historical usage of the data. For different levels of cache, choosing the appropriate algorithm can significantly optimize cache performance.

[0005] In current processor designs, for common n-way set associative (n-way) cache structures, regardless of the replacement algorithm used, including LRU or DDRIP, the storage of historical information and related control logic usually exist as an independent unit. After querying the cache directory, this unit determines the data to be replaced when there is a cache miss and replacement is required, based on information such as whether there is a cache hit and whether the corresponding cache line is available, and updates the historical information.

[0006] In existing solutions, the replacement algorithm exists as an independent unit within the cache, accessing this unit to retrieve or update information only after querying the cache directory. When a cache miss occurs and replacement is required, the replacement algorithm unit must be accessed serially to obtain the information of the cache line to be replaced, resulting in a certain delay. Furthermore, the cache line to be replaced also needs to obtain its complete data address information through the next directory read operation, preventing the replacement operation from starting immediately and consuming additional cache directory access bandwidth. Simultaneously, when historical information needs to be updated, the serial approach cannot provide the latest historical information to subsequent accesses within the same group in a timely manner, requiring the introduction of a blocking mechanism to wait for information to be updated, thus reducing the cache access rate. Therefore, due to the above reasons, existing cache management methods suffer from low access rates, low access bandwidth, and high hardware overhead.

[0007] Therefore, there is an urgent need for a new cache management method, system, and storage medium to solve the above-mentioned technical problems. Summary of the Invention

[0008] This invention provides a cache management method, system, and storage medium, which aims to improve cache access speed and bandwidth while reducing hardware overhead by storing cache information and replacement information simultaneously in one channel of the multi-way grouped cache. When the processor accesses the cache, it can obtain replacement information and cache information in real time, initiate replacement behavior, and update replacement information at the same time.

[0009] In a first aspect, the present invention provides a cache management method, the cache management method comprising the following steps:

[0010] S1. Establish a multi-way grouped associative cache, wherein each way in the multi-way grouped associative cache is used to store cache information and replacement information simultaneously;

[0011] S2. The processor initiates an access request to the multi-way set-associative cache, and accesses the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain the cache information and the replacement information;

[0012] S3. Determine whether the current access data of the processor produces a cache hit based on the cache information, and obtain a hit result; and determine whether there is an empty path in the multi-way set-associative cache, and obtain a judgment result;

[0013] Based on the replacement algorithm, the path that needs to be replaced in the multi-way set-associative cache is selected according to the replacement information and the judgment result to obtain the replacement target;

[0014] S4. Update the cache information and replacement information of the multi-way group-associative cache according to the current access data, the hit result, the judgment result and the replacement target to obtain the replacement result;

[0015] S5. Write the replacement result back to the memory.

[0016] Preferably, when the hit result is a cache miss and the judgment result is that there is no free path in the multi-way set-associative cache, the cache information stored in the corresponding path in the multi-way set-associative cache is replaced with the current access data according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data.

[0017] Preferably, when the hit result is a cache miss and the judgment result is that there is an idle path in the multi-way set-associative cache, the current access data is written to the corresponding path in the multi-way set-associative cache according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data.

[0018] Preferably, when the hit result is a cache hit, the replacement information stored in the corresponding path in the multi-way group associative cache is updated according to the current access data.

[0019] Preferably, step S5 further includes the following sub-steps:

[0020] A replacement result buffer layer is established, and when the replacement result is written back to the memory, it is also stored in the replacement result buffer layer;

[0021] If the processor accesses the same group in the multiplexed set-associative cache consecutively, it directly obtains the replacement result obtained by the processor from the previous access to the multiplexed set-associative cache from the replacement result buffer layer, and updates the cache information and replacement information of the multiplexed set-associative cache according to the replacement result of the previous access.

[0022] Preferably, the replacement algorithm includes one of the following: random replacement algorithm, first-in-first-out algorithm, least recently used algorithm, and dynamic reuse interval prediction algorithm.

[0023] Secondly, the present invention also provides a cache management system, the cache management system comprising:

[0024] A cache establishment module is used to establish a multi-way set-associative cache, wherein each way in the multi-way set-associative cache is used to store cache information and replacement information simultaneously;

[0025] The access module is used to initiate an access request to the multi-way set-associative cache through the processor, and access the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain the cache information and the replacement information;

[0026] The judgment module is used to determine whether the current access data of the processor produces a cache hit based on the cache information, and obtain a hit result; and to determine whether there is an empty path in the multi-way set-associative cache, and obtain a judgment result.

[0027] Based on the replacement algorithm, the path that needs to be replaced in the multi-way set-associative cache is selected according to the replacement information and the judgment result to obtain the replacement target;

[0028] The replacement module is used to update the cache information and replacement information of the multi-way group-associative cache according to the current access data, the hit result, the judgment result and the replacement target, so as to obtain the replacement result;

[0029] The write-back module is used to write the replacement result back to the memory.

[0030] Thirdly, the present invention also provides a computer device, comprising: a memory, a processor, and a cache management program stored in the memory and executable on the processor, wherein the processor, when executing the cache management program, implements the steps of the cache management method as described in any of the above embodiments.

[0031] Fourthly, the present invention also provides a computer-readable storage medium storing a cache management program, which, when executed by a processor, implements the steps of the cache management method as described in any of the above embodiments.

[0032] Compared with existing technologies, this invention stores cache information and replacement information simultaneously in one path of the multi-way set-associative cache. When the processor accesses the cache, it can access the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain replacement information and cache information. After initiating a replacement action, the replacement information can be updated simultaneously, effectively improving the cache access rate and bandwidth, and reducing hardware overhead. At the same time, through the replacement result buffer layer, it can avoid the blocking phenomenon caused by consecutive access addresses in the same group during the processor access process, thereby improving the access efficiency in the multi-way set-associative cache under group conflict scenarios. Using appropriate memory can also reduce the hardware overhead of the cache. Attached Figure Description

[0033] The present invention will now be described in detail with reference to the accompanying drawings. The above and other aspects of the present invention will become clearer and more readily understood through the detailed description following the accompanying drawings. In the drawings:

[0034] Figure 1 This is a flowchart of the cache management method provided in an embodiment of the present invention;

[0035] Figure 2This is a schematic diagram of the structure of a multi-way set-associative cache in the cache management method provided in this embodiment of the invention. Figure 1 ;

[0036] Figure 3 This is a schematic diagram of the path group-associative cache structure of the cache management method provided in this embodiment of the invention. Figure 2 ;

[0037] Figure 4 This is a schematic diagram of the cache management system provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. Detailed Implementation

[0039] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0040] Example 1

[0041] Please refer to Figure 1 This invention provides a cache management method, which includes the following steps:

[0042] S1. Establish a multi-way group-associative cache, wherein each way in the multi-way group-associative cache is used to store cache information and replacement information simultaneously.

[0043] In this embodiment of the invention, the set-associative cache includes multiple sets, each set including multiple ways. One way of the set-associative cache simultaneously stores cache information and replacement information. The cache information includes whether a cache entry in each way is available, and the address and status information of the cache block recorded when a cache entry in each way is used. The replacement information includes the number of accesses and utilization rate of each memory path in the set-associative cache.

[0044] To better understand the data structure of a multi-way set-associative cache, please refer to [reference needed]. Figure 2 , Figure 2 This is a schematic diagram of the structure of a multi-way set-associative cache in the cache management method provided in this embodiment of the invention. Figure 1 The multi-way set-associative cache includes M sets, each set including N paths. Each path's cache entry stores both cache information and replacement information. When the processor accesses the cache, it can directly obtain the cache information and replacement information through the cache directory and replacement directory of the multi-way set-associative cache.

[0045] For reference Figure 3 , Figure 3 This is a schematic diagram of the path group-associative cache structure of the cache management method provided in this embodiment of the invention. Figure 2 The multi-way set-associative cache includes M sets, each set including N ways. Cache information and replacement information can be recorded in different memories (i.e., different cache entries / table entries of each way). Multiple cache entries of each way store part of the cache information and part of the replacement information (each way stores both cache information and replacement information).

[0046] S2. The processor initiates an access request to the multi-way set-associative cache, and accesses the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain the cache information and the replacement information.

[0047] S3. Determine whether the current access data of the processor produces a cache hit based on the cache information, and obtain a hit result; specifically, a cache hit means that the processor's access data can directly find the required valid data from the multiplexed set-associative cache.

[0048] The system then determines whether there are any free paths in the multi-way set-associative cache, obtaining a result. Specifically, the result is used to determine whether a path in the current multi-way set-associative cache needs to be replaced.

[0049] Based on the replacement algorithm, the path in the multi-way set-associative cache that needs to be replaced is selected according to the replacement information and the judgment result, thus obtaining the replacement target. Specifically, the replacement algorithm pre-calculates possible replacement strategies, and the replacement target refers to the cache block to be replaced in the corresponding path of the multi-way set-associative cache.

[0050] In this embodiment of the invention, the replacement algorithm includes one of the following: Random Replacement (RAND), First-In-First-Out (FIFO), Least Recently Used (LRU), and Dynamic Re-Reference Interval Prediction (DRRIP). It should be noted that the replacement algorithm is not limited to the aforementioned Random Replacement, FIFO, Least Recently Used, and DRRIP algorithms; other replacement algorithms are also feasible and can be set according to actual conditions.

[0051] For example, the random replacement algorithm randomly selects a replacement block from the candidate data blocks in the multi-way set-associative cache; the first-in, first-out (FIFO) algorithm prioritizes replacing the earliest entered cache block according to the order in which data entered the multi-way set-associative cache; and the least recently used (LRU) algorithm prioritizes replacing the data block in the multi-way set-associative cache that has been accessed the least in the recent period. The dynamic reuse interval prediction algorithm more accurately selects the cache block to be replaced by dynamically predicting the reuse interval of the cache block (i.e., the time interval between two consecutive accesses).

[0052] S4. Update the cache information and replacement information of the multi-way group-associative cache according to the current access data, the hit result, the judgment result and the replacement target to obtain the replacement result.

[0053] In this embodiment of the invention, when the hit result is a cache hit, the replacement information stored in the corresponding path of the multi-way set-associative cache is updated according to the current access data. The replacement algorithm does not need to select a path in the multi-way set-associative cache for replacement or store a new cache block; it only needs to update the replacement information of that path in real time according to its algorithm.

[0054] When the hit result is a cache miss and the judgment result is that there is no free path in the multi-way set-associative cache, the cache information stored in the corresponding path in the multi-way set-associative cache is replaced with the current access data according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data.

[0055] When the hit result is a cache miss and the judgment result is that there is an idle path in the multi-way set-associative cache, the current access data is written to the corresponding path in the multi-way set-associative cache according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data.

[0056] In this embodiment of the invention, the above steps S1-S4 can be completed in parallel during a single cache access of the processor to determine the hit, the replacement, and update the replacement information. This saves access bandwidth and updates the replacement information required for replacement more promptly, which helps to improve the accuracy of the replacement algorithm.

[0057] S5. Write the replacement result back to the memory.

[0058] In this embodiment of the invention, step S5 further includes the following sub-steps:

[0059] A replacement result buffer layer is established, and when the replacement result is written back to the memory, it is also stored in the replacement result buffer layer;

[0060] If the processor accesses the same group in the multiplexed set-associative cache consecutively, it directly obtains the replacement result obtained by the processor from the previous access to the multiplexed set-associative cache from the replacement result buffer layer, and updates the cache information and replacement information of the multiplexed set-associative cache according to the replacement result of the previous access.

[0061] Specifically, by using additional flag bits to record whether each cache entry in the multi-way set-associative cache is used, if the previous access occupied a certain path in the multi-way set-associative cache, the subsequent access in the same group can see the action of the previous access through the flag bits, thereby taking the impact of the previous access into account in the replacement algorithm's judgment.

[0062] Compared with existing technologies, this invention stores cache information and replacement information simultaneously in one path of the multi-way set-associative cache. When the processor accesses the cache, it can access the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain replacement information and cache information. After initiating a replacement action, the replacement information can be updated simultaneously, effectively improving the cache access rate and bandwidth, and reducing hardware overhead. At the same time, through the replacement result buffer layer, it can avoid the blocking phenomenon caused by consecutive access addresses in the same group during the processor access process, thereby improving the access efficiency in the multi-way set-associative cache under group conflict scenarios. Using appropriate memory can also reduce the hardware overhead of the cache.

[0063] Example 2

[0064] This invention also provides a cache management system, please refer to... Figure 4 , Figure 4 This is a schematic diagram of the structure of the cache management system 200 provided in an embodiment of the present invention, which includes:

[0065] 201. Cache establishment module, used to establish a multi-way set-associative cache, wherein each way in the multi-way set-associative cache is used to store cache information and replacement information simultaneously;

[0066] 202. An access module, used to initiate an access request to the multi-way set-associative cache through the processor, and access the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain the cache information and the replacement information;

[0067] 203. A judgment module, used to determine whether the current access data of the processor produces a cache hit based on the cache information, and obtain a hit result; and to determine whether there is an idle path in the multi-way set-associative cache, and obtain a judgment result;

[0068] Based on the replacement algorithm, the path that needs to be replaced in the multi-way set-associative cache is selected according to the replacement information and the judgment result to obtain the replacement target;

[0069] 204. Replacement module, used to update the cache information and replacement information of the multi-way group associative cache according to the current access data, the hit result, the judgment result and the replacement target, to obtain the replacement result;

[0070] 205. Write-back module, used to write the replacement result back to the memory.

[0071] The cache management system 200 can implement the steps in the cache management method as described in the above embodiments and achieve the same technical effect, as described in the above embodiments, and will not be repeated here.

[0072] Example 3

[0073] This invention also provides a computer device, please refer to... Figure 5 , Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a cache management program stored in the memory 302 and capable of running on the processor 301.

[0074] The processor 301 calls the cache management program stored in the memory 302 to execute the steps in the cache management method provided in this embodiment of the invention. Please refer to... Figure 1 Specifically, it includes the following steps:

[0075] S1. Establish a multi-way group-associative cache, wherein each way in the multi-way group-associative cache is used to store cache information and replacement information simultaneously.

[0076] In this embodiment of the invention, the set-associative cache includes multiple sets, each set including multiple ways. One way of the set-associative cache simultaneously stores cache information and replacement information. The cache information includes whether a cache entry in each way is available, and the address and status information of the cache block recorded when a cache entry in each way is used. The replacement information includes the number of accesses and utilization rate of each memory path in the set-associative cache.

[0077] S2. The processor initiates an access request to the multi-way set-associative cache, and accesses the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain the cache information and the replacement information.

[0078] S3. Determine whether the current access data of the processor produces a cache hit based on the cache information, and obtain a hit result; specifically, a cache hit means that the processor's access data can directly find the required valid data from the multiplexed set-associative cache.

[0079] The system then determines whether there are any free paths in the multi-way set-associative cache, obtaining a result. Specifically, the result is used to determine whether a path in the current multi-way set-associative cache needs to be replaced.

[0080] Based on the replacement algorithm, the path in the multi-way set-associative cache that needs to be replaced is selected according to the replacement information and the judgment result, thus obtaining the replacement target. Specifically, the replacement algorithm pre-calculates possible replacement strategies, and the replacement target refers to the cache block to be replaced in the corresponding path of the multi-way set-associative cache.

[0081] In this embodiment of the invention, the replacement algorithm includes one of the following: Random Replacement (RAND), First-In-First-Out (FIFO), Least Recently Used (LRU), and Dynamic Re-Reference Interval Prediction (DRRIP).

[0082] For example, the random replacement algorithm randomly selects a replacement block from the candidate data blocks in the multi-way set-associative cache; the first-in, first-out (FIFO) algorithm prioritizes replacing the earliest entered cache block according to the order in which data entered the multi-way set-associative cache; and the least recently used (LRU) algorithm prioritizes replacing the data block in the multi-way set-associative cache that has been accessed the least in the recent period. The dynamic reuse interval prediction algorithm more accurately selects the cache block to be replaced by dynamically predicting the reuse interval of the cache block (i.e., the time interval between two consecutive accesses).

[0083] S4. Update the cache information and replacement information of the multi-way group-associative cache according to the current access data, the hit result, the judgment result and the replacement target to obtain the replacement result.

[0084] In this embodiment of the invention, when the hit result is a cache hit, the replacement information stored in the corresponding path of the multi-way set-associative cache is updated according to the current access data. The replacement algorithm does not need to select a path in the multi-way set-associative cache for replacement or store a new cache block; it only needs to update the replacement information of that path in real time according to its algorithm.

[0085] When the hit result is a cache miss and the judgment result is that there is no free path in the multi-way set-associative cache, the cache information stored in the corresponding path in the multi-way set-associative cache is replaced with the current access data according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data.

[0086] When the hit result is a cache miss and the judgment result is that there is an idle path in the multi-way set-associative cache, the current access data is written to the corresponding path in the multi-way set-associative cache according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data.

[0087] In this embodiment of the invention, the above steps S1-S4 can be completed in parallel during a single cache access of the processor to determine the hit, the replacement, and update the replacement information. This saves access bandwidth and updates the replacement information required for replacement more promptly, which helps to improve the accuracy of the replacement algorithm.

[0088] S5. Write the replacement result back to the memory.

[0089] In this embodiment of the invention, step S5 further includes the following sub-steps:

[0090] A replacement result buffer layer is established, and when the replacement result is written back to the memory, it is also stored in the replacement result buffer layer;

[0091] If the processor accesses the same group in the multiplexed set-associative cache consecutively, it directly obtains the replacement result obtained by the processor from the previous access to the multiplexed set-associative cache from the replacement result buffer layer, and updates the cache information and replacement information of the multiplexed set-associative cache according to the replacement result of the previous access.

[0092] Specifically, by using additional flag bits to record whether each cache entry in the multi-way set-associative cache is used, if the previous access occupied a certain path in the multi-way set-associative cache, the subsequent access in the same group can see the action of the previous access through the flag bits, thereby taking the impact of the previous access into account in the replacement algorithm's judgment.

[0093] The computer device 300 provided in this embodiment of the invention can implement the steps in the method as described in the above embodiments and can achieve the same technical effect. Refer to the description in the above embodiments, which will not be repeated here.

[0094] Example 4

[0095] This invention also provides a computer-readable storage medium storing a cache management program. When the cache management program is executed by a processor, it implements the various processes and steps in the cache management method provided in this invention and achieves the same technical effect. To avoid repetition, it will not be described again here.

[0096] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by hardware related to computer programs or instructions. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0097] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0098] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of the present invention.

[0099] The embodiments of the present invention have been described above with reference to the accompanying drawings. The disclosed embodiments are merely preferred embodiments of the present invention. However, the present invention is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many equivalent changes in form without departing from the spirit and scope of the claims of the present invention, and all such changes are within the protection scope of the present invention.

Claims

1. A cache management method, characterized in that, The cache management method includes the following steps: S1. Establish a multi-way grouped associative cache, wherein each way in the multi-way grouped associative cache is used to store cache information and replacement information simultaneously; S2. The processor initiates an access request to the multi-way set-associative cache, and accesses the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain the cache information and the replacement information; S3. Determine whether the current access data of the processor produces a cache hit based on the cache information, and obtain a hit result; and determine whether there is an empty path in the multi-way set-associative cache, and obtain a judgment result; Based on the replacement algorithm, the path that needs to be replaced in the multi-way set-associative cache is selected according to the replacement information and the judgment result to obtain the replacement target; S4. Update the cache information and replacement information of the multi-way group-associative cache according to the current access data, the hit result, the judgment result and the replacement target to obtain the replacement result; S5. Write the replacement result back to the memory; When the hit result is a cache miss and the judgment result is that there is no free path in the multi-way set-associative cache, the cache information stored in the corresponding path in the multi-way set-associative cache is replaced with the current access data according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data. When the hit result is a cache miss and the judgment result is that there is an idle path in the multi-way set-associative cache, the current access data is written to the corresponding path in the multi-way set-associative cache according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data.

2. The cache management method as described in claim 1, characterized in that, When the hit result is a cache hit, the replacement information stored in the corresponding path in the multi-way group associative cache is updated according to the current access data.

3. The cache management method as described in claim 1, characterized in that, Step S5 also includes the following sub-steps: A replacement result buffer layer is established, and when the replacement result is written back to the memory, it is also stored in the replacement result buffer layer; If the processor accesses the same group in the multiplexed set-associative cache consecutively, it directly obtains the replacement result obtained by the processor from the previous access to the multiplexed set-associative cache from the replacement result buffer layer, and updates the cache information and replacement information of the multiplexed set-associative cache according to the replacement result of the previous access.

4. The cache management method as described in claim 1, characterized in that, The replacement algorithm includes one of the following: random replacement algorithm, first-in-first-out algorithm, least recently used algorithm, and dynamic reuse interval prediction algorithm.

5. A cache management system, characterized in that, The cache management system includes: A cache establishment module is used to establish a multi-way set-associative cache, wherein each way in the multi-way set-associative cache is used to store cache information and replacement information simultaneously; The access module is used to initiate an access request to the multi-way set-associative cache through the processor, and access the cache directory and replacement directory of the multi-way set-associative cache in parallel to obtain the cache information and the replacement information; The judgment module is used to determine whether the current access data of the processor produces a cache hit based on the cache information, and obtain a hit result; and to determine whether there is an empty path in the multi-way set-associative cache, and obtain a judgment result. Based on the replacement algorithm, the path that needs to be replaced in the multi-way set-associative cache is selected according to the replacement information and the judgment result to obtain the replacement target; The replacement module is used to update the cache information and replacement information of the multi-way group-associative cache according to the current access data, the hit result, the judgment result and the replacement target, so as to obtain the replacement result; When the hit result is a cache miss and the judgment result is that there is no free path in the multi-way set-associative cache, the cache information stored in the corresponding path in the multi-way set-associative cache is replaced with the current access data according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data. When the hit result is a cache miss and the judgment result is that there is an idle path in the multi-way set-associative cache, the current access data is written to the corresponding path in the multi-way set-associative cache according to the replacement target, and the replacement information stored in the corresponding path in the multi-way set-associative cache is updated according to the current access data. The write-back module is used to write the replacement result back to the memory.

6. A computer device, characterized in that, include: A memory, a processor, and a cache management program stored on the memory and executable on the processor, wherein the processor, when executing the cache management program, implements the steps of the cache management method as described in any one of claims 1-4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a cache management program, which, when executed by a processor, implements the steps of the cache management method as described in any one of claims 1-4.

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