A chip that saves bus traces

Abstract

This invention discloses a chip that saves bus traces, including a master hard core module and at least two slave hard core modules. The master hard core module includes a chip bus master device, and the slave hard core modules include an instruction conversion unit, a data synchronization unit, and registers. The chip bus master device generates JTAG instructions and sends the clock signal, TMS signal, and TDI signal contained in the JTAG instructions to each instruction conversion unit via the TCK signal line, TMS signal line, and TDI signal line, respectively. The instruction conversion unit converts the TDI signal into an APB operation instruction and sends it to the data synchronization unit. Driven by the clock signal, the output data based on the TMS signal and TDI signal is obtained and sent to the chip bus master device via the TDO signal line. The data synchronization unit performs timing synchronization of the APB operation instructions and sends them to the registers for configuration. The chip bus master device selects each output data and outputs it to the APB. Applying this invention can achieve low power consumption.

Description

Technical Field

[0001] This invention relates to the field of chip bus technology, and more specifically, to a chip that saves bus traces. Background Technology

[0002] Highly integrated SoC (System on Chip) chips are the brains of all kinds of smart devices, from smartphones and wearable devices to smart medical devices and self-driving cars.

[0003] The chip bus of a SoC chip refers to the architecture and protocol used in integrated circuit design to transmit data and control signals between different functional modules or IP (Intellectual Property) cores. It is the infrastructure for internal chip communication, allowing data, instructions and control signals to be transmitted efficiently and orderly between various modules, and is a key component for realizing chip functions.

[0004] Harden refers to a highly integrated component within a chip, used to perform specific functions such as encryption and graphics processing. These components are typically independent, pre-verified modules in chip design, and a chip can include multiple harden modules.

[0005] When a harden needs to communicate with other hardens, it faces the problem of increased chip area due to bus routing, specifically manifested as follows:

[0006] Current chip designs often employ AMBA (Advanced Microcontroller Bus Architecture) buses for communication between different handsets, using APB (Advanced Peripheral Bus) buses as an example. Figure 1 As shown, Figure 1 This is a schematic diagram of a chip that uses the APB bus for communication between different hardcores. In hardcore module 1, S1 and S2 transmit data to downstream hardcore module 2 for register A configuration and hardcore module 3 for register B configuration via APB bus signal lines 1 and 2, respectively. Each APB bus signal line includes 32 address (addr) signal lines, 64 data signal lines, and 4 command (cmd) signal lines. Therefore, at least one hundred signal lines are needed between different hardcores, and other buses besides the APB bus require even more signal lines. S1-S5 are the bus configuration information sending terminals.

[0007] The distance between different hardens may be large, and the bus traces across hardens need to be reserved in advance, which increases the complexity of chip layout and trace length, occupies more chip area, and further leads to high chip power consumption. Summary of the Invention

[0008] This invention provides a chip that saves bus traces and achieves low power consumption. The specific technical solution is as follows.

[0009] In a first aspect, the present invention provides a chip that saves bus routing, including a master hard core module and at least two slave hard core modules. The master hard core module includes a chip bus master device, and the slave hard core modules include an instruction conversion unit, a data synchronization unit, and a register. The chip bus master device is connected to each instruction conversion unit through multiple signal lines of the JTAG interface organized by the Joint Test Behavior Organization. The multiple signal lines include at least a test clock TCK signal line, a test data input TDI signal line, a test mode selection TMS signal line, and a test data output TDO signal line.

[0010] The chip bus master device is used to receive bus configuration information sent via the Advanced Peripheral Interface (APB), generate JTAG control signals based on the bus configuration information, generate JTAG instructions based on the JTAG control signals, send clock signals contained in the JTAG instructions to each instruction conversion unit via the TCK signal line, send TMS signals contained in the JTAG instructions to each instruction conversion unit via the TMS signal line, and send TDI signals contained in the JTAG instructions to each instruction conversion unit via the TDI signal line. The clock signal is used to synchronize the timing of the JTAG instructions with the bus configuration information.

[0011] The instruction conversion unit is used to receive the TDI signal, convert the TDI signal into an APB operation instruction and send it to the corresponding data synchronization unit, and, driven by the clock signal, obtain the output data after register configuration based on the TMS signal and the TDI signal, and send the output data to the chip bus master device through the TDO signal line.

[0012] The data synchronization unit is used to receive the APB operation instruction and synchronize the timing of the APB operation instruction and the JTAG instruction, and send the synchronized APB operation instruction to the corresponding register for configuration.

[0013] The chip bus master device is also used to select the received output data and output the selected output data to the APB.

[0014] Optionally, the chip bus master device includes an APB master device, an APB slave device, a JTAG instruction generator, and a Test Access Port (TAP) controller.

[0015] The APB master device is used to receive bus configuration information sent via the Advanced Peripheral Interface (APB) and send it to the APB slave device.

[0016] The APB slave device is used to generate JTAG control signals based on the bus configuration information and send them to the JTAG instruction generator;

[0017] The JTAG command generator is used to generate JTAG commands based on the JTAG control signals and send them to the TAP controller.

[0018] The TAP controller is configured to send the clock signal contained in the JTAG instruction to each instruction conversion unit via the TCK signal line, send the TMS signal contained in the JTAG instruction to each instruction conversion unit via the TMS signal line, and send the TDI signal contained in the JTAG instruction to each instruction conversion unit via the TDI signal line.

[0019] Optionally, the JTAG instruction generator is specifically used for:

[0020] The data contained in the JTAG control signal is processed from parallel to serial to generate JTAG instructions.

[0021] Optionally, the data format of the TDI signal includes enabling control APB slave device, read / write operation attributes, register address, and read / write data field;

[0022] The APB slave device enable control is used to activate the APB slave device enable signal and control the switching state of the data channel. The read / write operation attribute is used to specify the current operation type. The register address is used to point to the accessed register address. The read / write data field contains configuration data or read results.

[0023] Optionally, the instruction conversion unit is specifically used for:

[0024] The data contained in the TDI signal is parsed and processed from serial to parallel to generate APB operation instructions.

[0025] Optionally, the bus configuration information is read / write request information, and the APB operation instruction includes at least read / write operation information, accessed register address information, and read / write data information.

[0026] Optionally, the register includes a data register;

[0027] The instruction conversion unit is specifically used for:

[0028] Driven by the clock signal, the TAP controller is controlled by the TMS signal to enter the shift data register SDR state. At the rising edge of each clock signal cycle, the data contained in the TDI signal is shifted into the data register to obtain the value of the data register, and the value of the data register is sent to the chip bus master device through the TDO signal line.

[0029] Optionally, the instruction conversion unit is specifically used for:

[0030] Driven by the clock signal, the TAP controller is controlled by the TMS signal to enter the update data register UDR state, update the value of the data register to the pin of the chip, and send the updated value to the chip bus master device through the TDO signal line.

[0031] Optionally, the chip bus master device is specifically used for:

[0032] The received output data is selected by a multiplexer, and the selected output data is then output to the APB.

[0033] Optionally, the multiple signal lines may further include a test reset input TRST signal line, which is used to reset the TAP controller.

[0034] As described above, the present invention provides a chip for saving bus traces, comprising a master hard core module and at least two slave hard core modules. The master hard core module includes a chip bus master device, and the slave hard core modules include an instruction conversion unit, a data synchronization unit, and registers. The chip bus master device connects multiple signal lines of the JTAG interface to each instruction conversion unit through a joint test behavior organization. These multiple signal lines include at least a test clock (TCK) signal line, a test data input (TDI) signal line, a test mode selection (TMS) signal line, and a test data output (TDO) signal line. The chip bus master device receives bus configuration information sent via the Advanced Peripheral Interface (APB), generates JTAG control signals based on the bus configuration information, generates JTAG instructions based on the JTAG control signals, sends the clock signal contained in the JTAG instructions to each instruction conversion unit via the TCK signal line, and sends the JTAG instructions via the TMS signal line. The system includes TMS signals sent to each instruction conversion unit, and TDI signals sent to each instruction conversion unit via the TDI signal line for JTAG instructions. A clock signal is used to synchronize the timing of JTAG instructions with bus configuration information. The instruction conversion unit receives the TDI signal, converts it into an APB operation instruction, and sends it to the corresponding data synchronization unit. Driven by the clock signal, it obtains the output data after register configuration based on the TMS and TDI signals and sends the output data to the chip bus master device via the TDO signal line. The data synchronization unit receives the APB operation instruction, synchronizes the timing of the APB operation instruction and JTAG instructions, and sends the synchronized APB operation instruction to the corresponding register for configuration. The chip bus master device also selects the received output data and outputs the selected output data to the APB. Therefore, by connecting the chip bus master device and each instruction conversion unit via the TCK, TDI, TMS, and TDO signal lines of the JTAG interface, the bus configuration information sent by the APB is converted into JTAG instructions and output to each instruction conversion unit. The instruction conversion unit then converts these instructions into APB operation instructions, and the data synchronization unit performs timing synchronization, thereby configuring the registers. After configuration, the output data is output to the APB via the chip bus master device through the instruction conversion unit. This enables the processing of bus signals between the master hard core module and the slave hard core module. Compared to existing designs with at least one hundred signal lines, this invention only includes TCK, TDI, TMS, and TDO signal lines, significantly reducing the number of bus traces, lowering design complexity, achieving more efficient chip design, and reducing chip power consumption, thus achieving low power consumption.

[0035] The innovative aspects of this invention include:

[0036] 1. By connecting the chip bus master device and each instruction conversion unit via the TCK, TDI, TMS, and TDO signal lines of the JTAG interface, the bus configuration information sent by the APB is converted into JTAG instructions and output to each instruction conversion unit. The instruction conversion unit then converts these instructions into APB operation instructions, and the data synchronization unit performs timing synchronization to configure the registers. After configuration, the output data is output to the APB via the chip bus master device through the instruction conversion unit. This enables the processing of bus signals between the master hard core module and the slave hard core module. Compared to existing systems with at least one hundred signal lines, this invention only includes TCK, TDI, TMS, and TDO signal lines, significantly reducing the number of bus traces, lowering design complexity, enabling more efficient chip design, and reducing chip power consumption to achieve low power consumption.

[0037] 2. By converting the data contained in the JTAG control signal from parallel to serial processing, the pin occupancy can be significantly reduced, thereby reducing the chip's power consumption and achieving the goal of low chip power consumption.

[0038] 3. By setting the TRST signal line to reset the TAP controller, there are now five signal lines between the master hard core module and the slave hard core module. Compared to the existing at least one hundred signal lines, the number of bus lines is greatly reduced, which reduces the design complexity, enables more efficient chip design, and also reduces chip power consumption.

[0039] 4. By parsing the data contained in the TDI signal and performing serial-to-parallel conversion processing, APB operation instructions are generated to convert the serial data into parallel data corresponding to the APB bus protocol, thereby configuring the registers.

[0040] 5. By setting the bus configuration information to read / write request information, the master hard core module can configure read / write access to registers in the slave hard core module via the JTAG interface.

[0041] 6. The multiplexer selects the received output data and outputs the selected output data to the APB, which serves as a bus arbitration function to avoid data collisions when transmitted to the APB.

[0042] 7. Driven by the clock signal, the TAP controller is controlled to enter the SDR state through the TMS signal. At the rising edge of each clock signal cycle, the data contained in the TDI signal is shifted into the data register to obtain the value of the data register, thereby realizing the configuration of the register.

[0043] 8. Driven by the clock signal, the TAP controller is controlled to enter the UDR state through the TMS signal, the value of the data register is updated to the chip pin, and the updated value is sent to the chip bus master device through the TDO signal line, thereby configuring the chip parameters.

[0044] Of course, implementing any product or method of the present invention does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are merely some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without any creative effort.

[0046] Figure 1 A schematic diagram of the structure of a chip that uses the APB bus to communicate between different hardware.

[0047] Figure 2 A schematic diagram of a chip structure for saving bus traces provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of another structure of a chip that saves bus traces, provided in an embodiment of the present invention.

[0049] Figures 2-3 The system consists of 1 main hard core module, 11 chip bus master device, 2 slave hard core modules, 21 instruction conversion unit, 22 data synchronization unit, and 23 registers. Detailed Implementation

[0050] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0051] It should be noted that the terms "comprising" and "having," and any variations thereof, in the embodiments and drawings of this invention are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the steps or units listed, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0052] This invention discloses a chip that saves bus traces and achieves low power consumption. The embodiments of this invention are described in detail below.

[0053] Figure 2 This is a schematic diagram of a chip structure that saves bus traces according to an embodiment of the present invention. See also... Figure 2 The present invention provides a chip that saves bus routing, including a master hard core module 1 and at least two slave hard core modules 2. The master hard core module 1 includes a chip bus master device 11, and the slave hard core modules 2 include an instruction conversion unit 21, a data synchronization unit 22, and a register 23. The hard core module can be replaced by harden, the chip bus master device can be replaced by Chip_bus_master, the instruction conversion unit can be replaced by dr_dec_intf, the data synchronization unit can be replaced by dr2apb, and the register can be replaced by reg.

[0054] Specifically, the chip bus master device 11 is used to convert the bus configuration information sent by the bus configuration information sender via APB (Advanced Peripheral Bus) into JTAG (Joint Test Action Group) instructions, so as to configure the registers through the JTAG interface.

[0055] The instruction conversion unit 21 is used to convert JTAG instructions into APB operation instructions, realize the serial-to-parallel conversion of data, and send the output data after register configuration to the chip bus master device 11.

[0056] The data synchronization unit 22 is used to handle data synchronization between APB operation instructions and JTAG instructions, ensuring that data can be correctly converted into APB timing output to registers, thereby configuring the registers.

[0057] See also Figure 2 The chip bus master device 11 is connected to each instruction conversion unit 21 via multiple signal lines of the JTAG interface. These signal lines include at least the TCK (Test Clock) signal line, the TDI (Test Data Input) signal line, the TMS (Test Mode Select) signal line, and the TDO (Test Data Output) signal line. Figure 2 Only one line is used to represent it; four signal lines are not shown.

[0058] The TCK signal line provides the clock signal for JTAG operations. The TCK signal is responsible for timing control, ensuring the correct movement of the JTAG port state and the synchronous transmission of data. The TMS signal line controls the JTAG port's state machine. At each rising edge of the TCK clock, the value of TMS determines the state of the port state machine at the next moment. The TDI signal line is used for serial input of test data. Corresponding to TDI, TDO is the test data output signal line, used for serial output of data from the JTAG port. When a read operation is performed, data retrieved from the device's internal registers is transmitted back via the TDO signal line. The output of TDO data also depends on the TCK clock signal.

[0059] In this embodiment of the invention, in order to configure the registers, the chip bus master device 11 receives the bus configuration information sent by the bus configuration information sender via APB, generates a Joint Test Behavior Organization (JTAG) control signal based on the bus configuration information, generates a JTAG instruction based on the JTAG control signal, and sends the clock signal contained in the JTAG instruction to each instruction conversion unit via the TCK signal line, sends the TMS signal contained in the JTAG instruction to each instruction conversion unit via the TMS signal line, and sends the TDI signal contained in the JTAG instruction to each instruction conversion unit 21 via the TDI signal line. The clock signal is used to synchronize the timing of the JTAG instruction and the bus configuration information.

[0060] Specifically, the chip bus master device 11 includes an APB master device, an APB slave device, a JTAG instruction generator, and a TAP (Test Access Port) controller. The APB master device, APB slave device, JTAG instruction generator, and TAP controller constitute an Advanced Peripheral Interface (API) converter for the chip bus module, such as... Figure 3 As shown. Figure 3 This is a schematic diagram of another structure of a chip that saves bus traces, provided in an embodiment of the present invention.

[0061] The APB master device is used to receive bus configuration information sent via the Advanced Peripheral Interface (APB) and send it to the APB slave device.

[0062] APB slave devices are used to generate JTAG control signals based on bus configuration information and send them to the JTAG command generator.

[0063] The JTAG instruction generator generates JTAG instructions based on JTAG control signals and sends them to the TAP controller. The TAP controller then passes the JTAG instructions to the internal logic circuitry of the chip. These JTAG instructions control the TAP controller to perform operations such as data transmission and status reading. JTAG instructions can include at least a clock signal, a TMS signal, a TDI signal, a Shift-dr instruction, and an Update-dr instruction. Figure 3 In this context, Si is the TDI signal, Clockdr is the clock signal, Shift-dr is the Shift-dr instruction, and Update-dr is the Update-dr instruction.

[0064] Specifically, the TAP controller is used to send the clock signal contained in the JTAG instruction to each instruction conversion unit via the TCK signal line, send the TMS signal contained in the JTAG instruction to each instruction conversion unit via the TMS signal line, and send the TDI signal contained in the JTAG instruction to each instruction conversion unit 21 via the TDI signal line.

[0065] The JTAG command generator is specifically used for:

[0066] The data contained in the JTAG control signals is processed from parallel to serial to generate JTAG instructions.

[0067] Specifically, the data contained in the JTAG control signals is converted into serial data through a shift register group to generate JTAG instructions.

[0068] Therefore, by performing parallel-to-serial processing on the data contained in the JTAG control signal, pin occupancy can be significantly reduced, thereby reducing chip power consumption and achieving the goal of low chip power consumption.

[0069] See also Figure 3 The data format of the TDI signal includes enabling control of the APB slave device, read / write operation attributes, register address, and read / write data fields.

[0070] In this context, the enable signal for the APB slave device can be replaced with "en" to activate the APB slave device and control the on / off state of the data channel; the read / write operation attribute can be replaced with "w / r" to specify whether the current operation type is a read or write operation, such as... Figure 3 The read / write operation attribute is `Write_en`, which indicates a write operation. The register address can be replaced with `addr` to point to the address of the accessed register. The read / write data field can be replaced with `data`, which can include configuration data or read results. For example, the register address can be a 32-bit `addr`, the read / write data field can be a 32-bit `data`, and `sel` is the enable signal.

[0071] The TDI signal data format is achieved by serial input driven by the TCK clock signal, processed by the TAP controller state machine, and finally interacting with the accessed register through the boundary scan chain. The specific transmission timing is as follows: first, the opcode (including en / w / r) is sent, then addr is sent, and finally the data field is transmitted. The entire process is controlled by the TMS signal state machine.

[0072] In one implementation, the multiple signal lines also include a TRST (Test Reset Input) signal line, which is used to reset the TAP controller.

[0073] Therefore, by setting the TRST signal line to reset the TAP controller, there are five signal lines between the master hard core module 1 and the slave hard core module 2. Compared with the existing at least one hundred signal lines, the number of bus lines is greatly reduced, the design complexity is reduced, and a more efficient chip design is achieved. At the same time, the chip power consumption can also be reduced.

[0074] See also Figure 2 and Figure 3 The instruction conversion unit 21 is used to receive the TDI signal, convert the TDI signal into an APB operation instruction, and send it to the corresponding data synchronization unit 22.

[0075] The instruction conversion unit 21 is specifically used for:

[0076] The data contained in the TDI signal is parsed and processed from serial to parallel to generate APB operation instructions.

[0077] In other words, APB operation instructions are parallel data.

[0078] Therefore, by parsing the data contained in the TDI signal and performing serial-to-parallel processing, APB operation instructions are generated to convert the serial data into parallel data corresponding to the APB bus protocol, thereby configuring the registers.

[0079] See also Figure 2 and Figure 3 The data synchronization unit 22 is used to receive APB operation instructions and synchronize the timing of APB operation instructions and JTAG instructions, and send the synchronized APB operation instructions to the corresponding register 23 for configuration. The purpose of synchronizing the timing of APB operation instructions and JTAG instructions is to ensure that the data can be correctly converted into APB timing for output.

[0080] The bus configuration information can be read / write request information, and the APB operation instructions include at least read / write operation information, accessed register address information, and read / write data information.

[0081] Therefore, by setting the bus configuration information to read / write request information, the master hard core module 1 can perform read / write configuration of the registers in the slave hard core module 2 through the JTAG interface.

[0082] After register 23 is configured, instruction conversion unit 21, driven by clock signal, obtains the output data after register configuration based on TMS and TDI signals, and sends the output data to chip bus master device 11 through TDO signal line. Figure 3 In this context, So represents the output data.

[0083] The chip bus master device 11 is also used to select the received output data and output the selected output data to the APB.

[0084] Among them, chip bus master device 11 is specifically used for:

[0085] The received output data is selected by a multiplexer, and the selected output data is then output to the APB.

[0086] Therefore, the multiplexer selects the received output data and outputs the selected output data to the APB, which serves as a bus arbitration function to avoid data collisions when transmitted to the APB.

[0087] The instruction conversion unit 21 can obtain the output data after register configuration based on the TMS signal and TDI signal under the drive of the clock signal in a variety of ways, including but not limited to the following two methods:

[0088] The first type:

[0089] The registers include a data register and an instruction conversion unit 21, which are specifically used for:

[0090] Driven by the clock signal, the TAP controller is controlled by the TMS signal to enter the SDR (Shift Data Register) state. At the rising edge of each clock signal cycle, the data contained in the TDI signal is shifted into the data register to obtain the value of the data register, and the value of the data register is sent to the chip bus master device 11 through the TDO signal line.

[0091] The TAP controller can switch states via TCK and TMS signals. Specifically, under the drive of the clock signal, the instruction conversion unit 21 controls the TAP controller to enter different states via the TMS signal. The signal-controlled states include at least the SDR state and the UDR state. The SDR state is the Shift-DR state, and the UDR state is the Update-DR state.

[0092] The registers include a data register and an instruction register. The TAP controller is used to perform serial data input to the instruction register and data register. Both the Shift-DR and Update-DR states are used to operate on the data register.

[0093] Specifically, driven by the clock signal, the TAP controller is controlled to enter the SDR state through the TMS signal. At the rising edge of each clock signal cycle, the data contained in the TDI signal is shifted into the data register to obtain the value of the data register, thereby realizing the configuration of the register. The value of the data register is sent to the chip bus master device 11 through the TDO signal line. At this time, the output data is the value of the data register.

[0094] The second type: Based on the first type, the instruction conversion unit 21 is specifically used for:

[0095] Driven by the clock signal, the TAP controller is controlled by the TMS signal to enter the UDR (Update Data Register) state, update the value of the data register to the chip pin, and send the updated value to the chip bus master device 11 through the TDO signal line, thereby configuring the chip parameters. At this time, the output data is the updated value.

[0096] As described above, the present invention provides a chip for saving bus traces, comprising a master hard core module 1 and at least two slave hard core modules 2. The master hard core module 1 includes a chip bus master device 11, and the slave hard core modules 2 include an instruction conversion unit 21, a data synchronization unit 22, and a register 23. The chip bus master device 11 is connected to each instruction conversion unit 21 via multiple signal lines of the JTAG interface organized by the Joint Test Behavior Organization. These multiple signal lines include at least a test clock (TCK) signal line, a test data input (TDI) signal line, a test mode selection (TMS) signal line, and a test data output (TDO) signal line. The chip bus master device 11 is used to receive bus configuration information sent via the Advanced Peripheral Interface (APB), generate JTAG control signals based on the bus configuration information, generate JTAG instructions based on the JTAG control signals, send the clock signal contained in the JTAG instructions to each instruction conversion unit via the TCK signal line, and send the JTAG instructions via the TMS signal line. The instructions include TMS signals sent to each instruction conversion unit, and the JTAG instructions include TDI signals sent to each instruction conversion unit 21 via the TDI signal line. The clock signal is used to synchronize the timing of the JTAG instructions with the bus configuration information. The instruction conversion unit 21 receives the TDI signal, converts it into an APB operation instruction, and sends it to the corresponding data synchronization unit 22. Driven by the clock signal, it obtains the output data after register configuration based on the TMS and TDI signals and sends the output data to the chip bus master device 11 via the TDO signal line. The data synchronization unit 22 receives the APB operation instruction, synchronizes the timing of the APB operation instruction and the JTAG instruction, and sends the synchronized APB operation instruction to the corresponding register 23 for configuration. The chip bus master device 11 also selects the received output data and outputs the selected output data to the APB. Therefore, by connecting the chip bus master device and each instruction conversion unit via the TCK, TDI, TMS, and TDO signal lines of the JTAG interface, the bus configuration information sent by the APB is converted into JTAG instructions and output to each instruction conversion unit. The instruction conversion unit then converts these instructions into APB operation instructions, and the data synchronization unit performs timing synchronization, thereby configuring the registers. After configuration, the output data is output to the APB via the chip bus master device through the instruction conversion unit. This enables the processing of bus signals between the master hard core module and the slave hard core module. Compared to existing designs with at least one hundred signal lines, this invention only includes TCK, TDI, TMS, and TDO signal lines, significantly reducing the number of bus traces, lowering design complexity, achieving more efficient chip design, and reducing chip power consumption, thus achieving low power consumption.

[0097] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of one embodiment, and the modules or processes shown in the drawings are not necessarily essential for implementing the present invention.

[0098] Those skilled in the art will understand that the modules in the apparatus of the embodiments can be distributed in the apparatus of the embodiments as described in the embodiments, or they can be located in one or more devices different from this embodiment with corresponding changes. The modules of the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0099] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip that saves bus traces, characterized in that, It includes a master hard core module and at least two slave hard core modules. The master hard core module includes a chip bus master device, and the slave hard core modules include an instruction conversion unit, a data synchronization unit, and registers. The chip bus master device is connected to each instruction conversion unit through multiple signal lines of the JTAG interface of the Joint Test Behavior Organization. The multiple signal lines include at least a test clock TCK signal line, a test data input TDI signal line, a test mode selection TMS signal line, and a test data output TDO signal line. The chip bus master device is used to receive bus configuration information sent via the Advanced Peripheral Interface (APB), generate JTAG control signals based on the bus configuration information, generate JTAG instructions based on the JTAG control signals, send clock signals contained in the JTAG instructions to each instruction conversion unit via the TCK signal line, send TMS signals contained in the JTAG instructions to each instruction conversion unit via the TMS signal line, and send TDI signals contained in the JTAG instructions to each instruction conversion unit via the TDI signal line. The clock signal is used to synchronize the timing of the JTAG instructions with the bus configuration information. The instruction conversion unit is used to receive the TDI signal, convert the TDI signal into an APB operation instruction and send it to the corresponding data synchronization unit, and, driven by the clock signal, obtain the output data after register configuration based on the TMS signal and the TDI signal, and send the output data to the chip bus master device through the TDO signal line. The data synchronization unit is used to receive the APB operation instruction and synchronize the timing of the APB operation instruction and the JTAG instruction, and send the synchronized APB operation instruction to the corresponding register for configuration. The chip bus master device is also used to select the received output data and output the selected output data to the APB; The chip bus master device includes an APB master device, an APB slave device, a JTAG instruction generator, and a test access port (TAP) controller. The APB master device is used to receive bus configuration information sent via the Advanced Peripheral Interface (APB) and send it to the APB slave device. The APB slave device is used to generate JTAG control signals based on the bus configuration information and send them to the JTAG instruction generator; The JTAG command generator is used to generate JTAG commands based on the JTAG control signals and send them to the TAP controller. The TAP controller is configured to send the clock signal contained in the JTAG instruction to each instruction conversion unit via the TCK signal line, send the TMS signal contained in the JTAG instruction to each instruction conversion unit via the TMS signal line, and send the TDI signal contained in the JTAG instruction to each instruction conversion unit via the TDI signal line.

2. The chip for saving bus traces as described in claim 1, characterized in that, The JTAG command generator is specifically used for: The data contained in the JTAG control signal is processed from parallel to serial to generate JTAG instructions.

3. The chip for saving bus traces as described in claim 1, characterized in that, The data format of the TDI signal includes enabling control APB slave device, read / write operation attributes, register address, and read / write data field; The APB slave device enable control is used to activate the APB slave device enable signal and control the switching state of the data channel. The read / write operation attribute is used to specify the current operation type. The register address is used to point to the accessed register address. The read / write data field contains configuration data or read results.

4. The chip for saving bus traces as described in claim 1, characterized in that, The instruction conversion unit is specifically used for: The data contained in the TDI signal is parsed and processed from serial to parallel to generate APB operation instructions.

5. The chip for saving bus traces as described in claim 1, characterized in that, The bus configuration information is read / write request information, and the APB operation instruction includes at least read / write operation information, accessed register address information, and read / write data information.

6. The chip for saving bus traces as described in claim 1, characterized in that, The register includes a data register; The instruction conversion unit is specifically used for: Driven by the clock signal, the TAP controller is controlled by the TMS signal to enter the shift data register SDR state. At the rising edge of each clock signal cycle, the data contained in the TDI signal is shifted into the data register to obtain the value of the data register, and the value of the data register is sent to the chip bus master device through the TDO signal line.

7. The chip for saving bus traces as described in claim 6, characterized in that, The instruction conversion unit is specifically used for: Driven by the clock signal, the TAP controller is controlled by the TMS signal to enter the update data register UDR state, update the value of the data register to the pin of the chip, and send the updated value to the chip bus master device through the TDO signal line.

8. The chip for saving bus traces as described in claim 1, characterized in that, The chip bus master device is specifically used for: The received output data is selected by a multiplexer, and the selected output data is then output to the APB.

9. The chip for saving bus traces as described in claim 1, characterized in that, The multiple signal lines also include a test reset input TRST signal line, which is used to reset the TAP controller.

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