Low-voltage cabinet overload early warning method and device based on current harmonic recognition

Abstract

The invention provides a low-voltage cabinet overload early warning method and device based on current harmonic recognition, and relates to the technical field of power supply, and the method comprises the steps: carrying out the current double-side real-time monitoring of a low-voltage cabinet, and generating an input side current harmonic feature vector and N output branch current harmonic feature vectors; performing overload main cause positioning analysis, and outputting real-time overload early warning; if the main factor is the input side overload main factor, branch overload contribution degree quantification is carried out, and N overload risk weight factors are output; global collaborative load reduction of the N output side devices is carried out; and if the main factor is the output side overload main factor, analyzing and generating an output side load reduction strategy based on harmonic-load coupling disturbance characteristics of the real-time main factor branch equipment on N-1 output side equipment after isolation. The technical problem that the load adjustment of the whole system is unbalanced due to the fact that the load adjustment method mostly depends on manual judgment and lacks dynamic adjustment and optimization of the whole load condition of the power supply system in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of power supply, and in particular to a low-voltage cabinet overload early warning method and device based on current harmonic identification. Background Art

[0002] In power supply systems, low-voltage cabinets, as crucial electrical equipment, are responsible for distributing power to various branches and devices. As load increases, overload becomes a significant factor affecting the stability and safety of low-voltage cabinets and their associated equipment. Overload not only directly damages equipment but can also trigger cascading failures in the power system. Therefore, overload warning is a critical step in ensuring the reliable operation of power systems. However, current overload warning systems mostly rely on manual judgment and traditional load adjustment methods, lacking dynamic adjustment and optimization of the system's overall load, and failing to achieve global load coordination and load reduction. This not only leads to overlooked overload issues on certain devices, but can also lead to unbalanced load regulation across the entire system, potentially damaging equipment or causing system instability. Summary of the Invention

[0003] This application provides a low-voltage cabinet overload warning method and device based on current harmonic identification, aiming to solve the technical problem that most of the existing load adjustment methods rely on manual judgment, lack dynamic adjustment and optimization of the overall load conditions of the power supply system, and lead to unbalanced load adjustment of the overall system.

[0004] The first aspect disclosed in the present application provides a low-voltage cabinet overload warning method based on current harmonic identification, the method comprising: performing real-time monitoring of the current on both sides of the low-voltage cabinet to generate an input side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output side devices; performing overload main cause location analysis based on the input side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, and outputting a real-time overload warning; if the real-time overload warning is the main cause of input side overload, then quantifying the branch overload contribution based on the N output branch current harmonic characteristic vectors, and outputting N overload risk weight factors; performing global coordinated load reduction of the N output side devices based on the N overload risk weight factors; if the real-time overload warning is the main cause of output side overload, then analyzing and generating an output side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the output side overload main cause on N-1 output side devices after isolation.

[0005] The second aspect disclosed in the present application provides a low-voltage cabinet overload warning device based on current harmonic identification, which is used in the above-mentioned low-voltage cabinet overload warning method based on current harmonic identification. The device includes: a real-time monitoring module for performing real-time monitoring of the current on both sides of the low-voltage cabinet, generating an input side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output side devices; a positioning analysis module for performing overload main cause positioning analysis based on the input side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, and outputting real-time overload warning. a contribution quantification module for quantifying branch overload contributions based on the N output branch current harmonic characteristic vectors, and outputting N overload risk weight factors, if the real-time overload warning is the main cause of input-side overload; a global coordinated load reduction module for performing global coordinated load reduction of the N output-side devices according to the N overload risk weight factors; a load reduction strategy generation module for analyzing and generating an output-side load reduction strategy, if the real-time overload warning is the main cause of output-side overload, based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of output-side overload on N-1 output-side devices after isolation.

[0006] One or more technical solutions provided in this application have at least the following beneficial effects:

[0007] By performing real-time current monitoring on both sides of the input and output branches of the low-voltage cabinet, the current harmonic characteristic information of the input side and each output branch can be accurately captured. The generated current harmonic characteristic vector can reflect the frequency characteristics and harmonic distribution of the current waveform in detail, providing accurate input for subsequent overload analysis and early warning. Based on the current harmonic characteristic vectors of the input and output branches, the main cause of overload location analysis is performed. By comparing the current characteristics, it can be accurately determined whether the source of the overload is from the input side or the output side. This main cause location analysis can provide real-time overload early warning, quickly respond to the overload problem of the system, and help to take measures in advance to avoid system damage caused by overload. In the case where the input side overload is the main cause, the overload contribution of the branch is quantified based on the current harmonic characteristic vector of each output branch. By calculating the overload risk weight factor of each branch, the risk of overload of each output branch is quantified. The impact of the branch on the overall overload of the system can be accurately identified, so as to accurately identify which branches contribute more to the overload and give priority to overload relief, thereby improving the system's load management and response capabilities; based on the overload risk weight factor, global coordinated load reduction is performed on N output devices, which can ensure that each branch is coordinated during load reduction, avoid excessive load reduction on a branch and excessive load on other branches, thereby achieving load balancing; when the output side overload is the main cause, based on the real-time overload situation of the main branch device, its impact on other branches is analyzed, especially its harmonic-load coupling effect. Through the simulation of harmonic coupling, the output side load reduction strategy is generated to ensure that the load reduction operation of the output device not only reduces the load of the main branch, but also avoids overload of other branches due to harmonic coupling, achieving more accurate and scientific load regulation, and improving the stability and safety of the power supply system.

[0008] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A flow chart of a low-voltage cabinet overload warning method based on current harmonic identification provided in an embodiment of the present application.

[0010] Figure 2 A schematic structural diagram of a low-voltage cabinet overload warning device based on current harmonic identification provided in an embodiment of the present application.

[0011] Explanation of the reference numerals: real-time monitoring module 10 , positioning analysis module 20 , contribution quantification module 30 , global coordinated load reduction module 40 , load reduction strategy generation module 50 . DETAILED DESCRIPTION

[0012] The embodiments of the present application provide a low-voltage cabinet overload warning method and device based on current harmonic identification, which solves the technical problem that most load adjustment methods in the existing technology rely on manual judgment, lack dynamic adjustment and optimization of the overall load conditions of the power supply system, and lead to unbalanced load adjustment of the overall system.

[0013] After introducing the basic principles of this application, various non-limiting embodiments of this application will be specifically described below in conjunction with the accompanying drawings. It should be understood that the specific embodiments described here are only used to explain this application and are not used to limit this application.

[0014] Example 1, as Figure 1 As shown, an embodiment of the present application provides a low-voltage cabinet overload warning method based on current harmonic identification, the method comprising:

[0015] Perform real-time monitoring of current on both sides of the low-voltage cabinet to generate an input-side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output-side devices.

[0016] Real-time current monitoring is performed on the input and output branches of the low-voltage cabinet. The input refers to the current flowing through the cabinet's main power supply, while the output branches refer to the various output devices connected to the cabinet. Hall effect current sensors can be installed to monitor current flow, enabling real-time current data acquisition for each branch. These sensors, deployed on the input busbar and each output branch, capture current waveform data at a predefined sampling rate (e.g., 1000 samples per second). This collected data is then processed through grayscale mapping, which converts the amplitude variations of the waveform signal into varying grayscale values, forming a graphical representation of the current waveform. Feature extraction is then performed on this grayscale image, for example, using a time-series spectral feature extraction method to extract instantaneous harmonic feature vectors. These feature vectors represent the intensity, phase, and other information of each frequency component in the current waveform. The same current data acquisition, grayscale mapping, and spectral feature extraction procedures are repeated for the input busbar and each output branch, ultimately yielding the input current harmonic feature vector and the N output branch current harmonic feature vectors. The N output branch current harmonic characteristic vectors correspond to N output-side devices, and each output-side device corresponds to an output branch.

[0017] Based on the input side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, an overload main cause location analysis is performed to output a real-time overload warning.

[0018] Based on the input-side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, an overload cause location analysis is performed. The goal is to identify the primary source of the overload, which can be a current problem on the input side or a current problem in the output branch equipment. Specifically, the input and output current harmonic characteristic vectors are compared with historical overload current records. The historical records contain current characteristic data of past overloads. This comparison can identify the similarity between the current characteristics and the historical overload characteristics. Based on this similarity, the overload risk probability vectors for the input side and output branches are output—that is, the probability of an overload on the input side and each output branch equipment. The input-side current characteristic vector is compared with a multi-level overload characteristic template to calculate the input-side overload risk probability vector. This process uses a dynamic weighting method to assess whether there is an overload risk on the input side. Simultaneously, a similar analysis is performed on each output branch to calculate the overload risk of each branch.

[0019] If the current characteristics of the input side are highly similar to the historical overload characteristics, and the overload risk on the input side exceeds the preset threshold, the input side is determined to be the main cause of the overload, and a real-time overload warning is output; if the current characteristics of the output branch are compared with the historical overload characteristics and a higher overload risk is identified, the output side is determined to be the main cause of the overload, and a real-time overload warning is output for the corresponding branch.

[0020] If the real-time overload warning is the main cause of input side overload, the branch overload contribution is quantified based on the N output branch current harmonic characteristic vectors, and N overload risk weight factors are output.

[0021] In the case of input-side overload as the main cause, the branch overload contribution is quantified based on the N output branch current harmonic characteristic vectors, and the overload risk weight factor of each branch is output. The purpose is to quantify the contribution of each output branch to the overall overload and provide data support for subsequent load reduction decisions. Specifically, the current harmonic characteristic vector of each output branch is compared with the input-side current characteristic vector to evaluate the overload contribution of each branch. A measurement method similar to weighted similarity is used to calculate the similarity between the current harmonic characteristic vector of each output branch and the input-side current harmonic characteristic vector. The higher the similarity, the greater the contribution of the branch to the input-side overload. The contribution of each branch is converted into an overload risk weight factor. A branch with a high overload risk weight factor indicates that it occupies a large proportion of the overall system overload and needs to be given priority for load reduction operations.

[0022] Global coordinated load reduction of the N output-side devices is performed based on the N overload risk weight factors.

[0023] Based on N overload risk weight factors, global coordinated load reduction is performed, that is, the load is coordinated and adjusted among multiple output branches to avoid overload of a single branch causing overall instability of the system. Specifically, according to the N overload risk weight factors, the priority of the overloaded branches is first sorted. The branch with a larger weight factor has a higher priority because it contributes more to the overload and needs to be unloaded first. After sorting, the load switching or removal is automatically implemented according to the priority and risk factor of each overloaded branch. For example, if the overload risk factor of a branch is very high and the branch is critical to the stability of the system, partial load removal is adopted, or even the branch is completely disconnected to reduce the overload pressure. The load reduction operation is coordinated, that is, the load adjustment between each output side device needs to be balanced to avoid overloading other branches. Load reduction is not just for a single branch, but adjusts the load conditions of each branch through global optimization, ultimately achieving the purpose of reducing the overall overload risk.

[0024] If the real-time overload warning is the main cause of output side overload, the output side load reduction strategy is analyzed and generated based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output side overload on N-1 output side devices after isolation.

[0025] If the real-time overload warning indicates the main cause of the output-side overload, the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output-side overload are analyzed, and a targeted load reduction strategy is formulated. Specifically, for the real-time main cause branch device corresponding to the main cause of the output-side overload, the impact of the device after isolation is analyzed, that is, after the device is disconnected, the harmonic-load coupling characteristics of the remaining N-1 output-side devices are analyzed. The harmonic-load coupling disturbance characteristic analysis can be implemented through a simulation model to simulate the impact of the load disturbance after branch isolation on other devices. This analysis helps to clarify which branch overload will cause the greatest interference to other branches, thereby affecting the stability of the overall system. Based on the harmonic-load disturbance characteristics, an output-side load reduction strategy is generated, with the goal of reducing the load of the affected branches in the system to ensure system stability. For example, based on the load coupling relationship between the branches, the branches that are most affected by the interference are preferentially adjusted to ensure that the overall system returns to a normal load state with minimal interference.

[0026] Furthermore, the method further comprises:

[0027] The Hall current sensor installed on the busbar on the input side of the low-voltage cabinet collects the original current waveform data on the input side at a predefined sampling rate and outputs a time-series current waveform sequence; the time-series current waveform sequence is processed by grayscale mapping to output a waveform grayscale image; a preset sliding window is used to segment the waveform grayscale image into multiple segmented waveform images, wherein the overlap of adjacent time-series segmented waveform images is greater than 75%; time-series spectrum features are extracted from the multiple segmented waveform images to output multiple instantaneous harmonic feature vectors; the input side current harmonic feature vector is output by performing sliding weighted fusion on the multiple instantaneous harmonic feature vectors.

[0028] A Hall-effect current sensor is installed on the busbar on the input side of the low-voltage cabinet to collect input current data. This sensor senses current in real time and converts it into a voltage signal for monitoring the current waveform. To obtain sufficient current waveform information, a predefined sampling rate is set for the Hall-effect current sensor, for example, 1000 samples per second, to ensure that details of the current waveform are captured. This high sampling rate helps accurately capture rapid current changes, thereby improving the accuracy of subsequent data processing. The Hall-effect current sensor collects raw current waveform data at the predefined sampling rate. The raw current waveform data is arranged chronologically to form a time-series current waveform sequence.

[0029] Grayscale mapping is the process of converting time-series current waveform data into a grayscale image. Since current waveform data is usually a continuous numerical signal, grayscale mapping can convert these numerical signals into image data, making the change information in the signal easier to capture and analyze. Through grayscale mapping processing, the amplitude value (or certain frequency characteristics) of the time-series current waveform is converted into a grayscale level, and a waveform grayscale image is output. In the waveform grayscale image, the change of the current signal is represented by different grayscale values. The higher the grayscale value, the greater the amplitude of the current signal, and vice versa.

[0030] A preset sliding window is used to segment the waveform grayscale image. For example, the width of the preset sliding window is set to a time span of 200ms, which means that each window covers the current waveform data within 200ms and slides across the entire time-series image to segment different waveform segments. Each preset sliding window extracts a portion of the image, namely the current waveform of a 200ms time-series segment. In this way, the entire time-series current waveform sequence is segmented into multiple segmented waveform images, each of which contains current waveform data within 200ms. Among the multiple segmented waveform images, there is an overlap of more than 75% between the segmented waveform images of adjacent time series. That is, when processing each new sliding window, the last part of the previous window will overlap with the beginning part of the current window. This overlap can maintain temporal continuity, ensure the coherence of the time-series information, and avoid information loss.

[0031] The time-series spectrum characteristics can reveal the information of the current waveform at different frequencies, which is used to identify the changing patterns of the current and its harmonic characteristics, and perform time-frequency analysis on multiple segmented waveform images. For example, the Fourier transform method is used to convert the time domain signal into the frequency domain signal to obtain the frequency distribution and amplitude information, and the instantaneous harmonic feature vector is obtained. The instantaneous harmonic feature vector describes the frequency characteristics in the current waveform of this time segment, including the amplitude, frequency, and phase of the harmonics, which can reflect the harmonic properties of this current segment.

[0032] Since each instantaneous harmonic eigenvector reflects the current waveform characteristics of the corresponding time segment, in order to obtain the comprehensive characteristics of the entire input-side current waveform, these instantaneous eigenvectors need to be fused. Sliding weighted fusion is achieved by weighted averaging multiple instantaneous harmonic eigenvectors. The weights can be dynamically adjusted according to the changes in the time step to smooth and emphasize the changes in a short period of time. Through sliding weighted fusion, a smooth input-side current harmonic eigenvector that can represent the entire time process is obtained. This input-side current harmonic eigenvector integrates the spectral information of the entire current waveform and can more comprehensively reflect the changing characteristics of the current.

[0033] Furthermore, based on the input-side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, an overload main cause location analysis is performed to output a real-time overload warning. The method includes:

[0034] Locally call historical overload current records, and perform fault feature vector fitting based on the historical overload current records to output a multi-level overload feature vector template; calculate the time-varying weighted similarity between the input side current harmonic feature vector and the multi-level overload feature vector template, and output the input side multi-level overload risk probability vector; preset a dynamic diagnosis threshold matrix, and obtain the input side overload analysis result by comparing the dynamic diagnosis threshold matrix with the input side multi-level overload risk probability vector; by analogy, perform synchronous overload main cause location analysis on the N output branch current harmonic feature vectors to produce N output branch overload analysis results, wherein the input side overload analysis result and the N output branch overload analysis results constitute the real-time overload warning.

[0035] Historical overload current records are locally retrieved and stored in a local database. These records contain current characteristic data under different overload scenarios, including the current waveform, the time of occurrence, duration, and amplitude of each overload event. This data can be used to understand the changing patterns and characteristics of current under overload conditions. Fault feature vector fitting is performed based on historical overload current records. This means that by analyzing historical overload current records, typical overload characteristics such as the characteristic frequency, amplitude variation, and nonlinear characteristics of the current waveform are extracted. Multi-level overload feature vector templates are then established based on the historical data. Each overload feature vector template represents a specific overload mode, such as mild overload, moderate overload, or severe overload.

[0036] The input current harmonic feature vector is compared with the multi-level overload feature vector template, and their similarity is calculated. This similarity calculation considers not only static feature comparison but also the dynamic changes between real-time and historical data, ensuring timely identification of the evolution of overload risks. Time-varying weighting allows for dynamic weight adjustment when comparing the real-time current features (i.e., the input current harmonic feature vector) with the historical overload data template, prioritizing recent changes over long-term historical trends. This means that more weight is assigned to similarities at recent moments, while less weight is assigned to historical records further away from the current moment. For example, a weighted sliding window approach is used to assign higher weights to more recent historical data. By calculating the time-varying weighted similarity between the input current harmonic feature vector and the multi-level overload feature template, an input multi-level overload risk probability vector is obtained. This vector represents the degree of match between the current input current and different overload states. Each element represents the probability that the input current waveform belongs to a specific overload level in the current system state. For example, if the input current has a high similarity to the severe overload template, the probability of severe overload risk is high.

[0037] The dynamic diagnosis threshold matrix provides a benchmark for the system, which is used to compare with the multi-level overload risk probability vector on the input side to determine whether the current state has reached the overload warning threshold. The elements of the matrix contain the risk probability thresholds corresponding to each overload level. These thresholds are dynamically adjusted according to the actual operating conditions of the power system. For example, during peak load periods, the overload tolerance needs to be reduced, and the thresholds will be lowered accordingly. The multi-level overload risk probability vector on the input side is compared with the preset dynamic diagnosis threshold matrix. If the risk probability of a certain overload level on the input side exceeds the corresponding threshold, the overload risk at that level is considered to be established. The comparison results form the input side overload analysis result, indicating the current overload risk level on the input side.

[0038] For each output branch, an overload main cause location analysis is performed. By analyzing the current characteristics of each branch, the branches that may be the main causes of the overload are identified, and the corresponding output branch overload analysis results are generated. Similar to the overload analysis on the input side, the overload analysis of the output branch is also compared with the historical overload feature template based on its current characteristics, and the similarity with the historical overload pattern is calculated. Then, by comparing with the dynamic diagnosis threshold matrix, the overload risk level of each output branch is determined. For each output branch, the corresponding output branch overload analysis result is generated, indicating whether the branch is overloaded and the severity of its overload risk.

[0039] Furthermore, if the real-time overload warning is the main cause of input-side overload, the branch overload contribution is quantified based on the N output branch current harmonic characteristic vectors, and N overload risk weight factors are output. The method includes:

[0040] When the overload analysis results of the N output branches all indicate no overload risk, and the input side overload analysis result indicates input side overload, the real-time overload warning is determined to be the main cause of input side overload; in the risk scenario where the real-time overload warning is the main cause of input side overload, the N output side overload risk probability distributions of the N output branch current harmonic characteristic vectors are called; the branch overload contribution is quantified based on the N output side overload risk probability distributions, and the N overload risk weight factors are output.

[0041] If the overload analysis results for all N output branches indicate no overload risk, this means the current waveform of each output branch has not reached the overload threshold and no overload signs have been detected. At the same time, the input-side overload analysis results indicate an input-side overload, meaning the current waveform has exceeded the preset overload threshold, indicating an abnormal input current and an overload risk. If both of these conditions are met simultaneously—no output branch overload but an input overload—then the input-side overload is determined to be the primary cause. This determination indicates that the overload problem originates on the input side, not a specific output branch.

[0042] In risk scenarios where input-side overload is determined to be the primary cause, it is necessary to further clarify the overload risk status of each output branch and use the N output-side overload risk probability distributions of the N output branch current harmonic characteristic vectors. The output-side overload risk probability distribution provides information about the overload probability of each branch. For example, some branches have a higher overload risk probability, and these branches need to be given priority when reducing load.

[0043] Based on the overload risk probability distribution on the output side, the branch overload contribution is quantified. The purpose is to determine the contribution of each output branch to the overall overload risk, that is, which branches' overload is more likely to affect the overall system. Specifically, by weighted calculation of the overload risk probability distribution of each branch, the overload risk weight factor of each branch is obtained. The overload risk weight factor reflects the contribution of the branch to the overall overload of the system. For example, if the overload risk probability of a branch is higher, its risk weight factor will also be larger, indicating that the branch contributes more to the overload event and load reduction or load optimization is required as a priority.

[0044] Furthermore, the method of performing global coordinated load reduction of the N output-side devices according to the N overload risk weight factors includes:

[0045] In a risk scenario where the real-time overload warning is the main cause of input-side overload, the input-side overload level is extracted from the input-side overload analysis result; an overload adjustment scale is obtained by matching the input-side overload level in a dynamic load reduction coefficient mapping table; N collaborative load reduction instruction vectors are calculated and output based on the overload adjustment scale and N overload risk weight factors; the N collaborative load reduction instruction vectors are used to drive the N output-side devices, and a gradient load reduction operation is used to perform global collaborative load reduction.

[0046] When the real-time overload warning is the main cause of input-side overload, the input-side overload level is extracted from the input-side overload analysis results. The input-side overload level indicates the severity of the overload on the input side and is usually divided into different levels such as mild, moderate, and severe. The level is determined based on the similarity between the input-side current waveform and the overload feature template, the comparison with historical data, and the comparison results of the threshold matrix.

[0047] The dynamic load reduction factor mapping table maps the relationship between different overload levels and load reduction adjustment scales. For example, when the input overload level is mild, the load reduction factor is small, requiring only a small load adjustment. When the overload level is severe, the load reduction factor is large, requiring large-scale load reduction across multiple devices or branches. Based on the input overload level, the corresponding overload adjustment scale is searched from the dynamic load reduction factor mapping table. The overload adjustment scale can be understood as a control parameter that indicates the strength of the system's response to input overloads. A larger overload adjustment scale requires a larger load adjustment to alleviate overload pressure.

[0048] Based on the product of the overload adjustment scale and N overload risk weight factors, N collaborative load reduction instruction vectors are calculated and output. Specifically, output branches with larger overload risk weights need to receive stronger load reduction instructions to reduce the overall system overload. The collaborative load reduction instruction vector indicates the load size that needs to be reduced for each output branch. The purpose of the collaborative load reduction instruction is to enable the entire system to smoothly reduce the load and avoid system overload.

[0049] Gradient load shedding is a method of gradually adjusting the load. Based on the calculated N coordinated load shedding instruction vectors, the load of each output branch is gradually adjusted, and the device load is gradually reduced according to the preset gradient to smoothly achieve global load shedding. The gradient load shedding operation helps to avoid sudden load switching that causes system instability, ensures that the load of each branch is reduced as needed, and avoids excessive pressure on the equipment. Each output-side device is driven according to the calculated coordinated load shedding instruction vector, including: for devices with larger loads, its current output is reduced; for devices with lighter loads, the load is moderately reduced to ensure balanced load distribution. The load shedding operation process will be carried out in a gradient distribution manner, gradually reducing the overload pressure and ensuring the smooth operation of the system. Ultimately, all N output-side devices will adjust their loads according to their respective load shedding instructions to complete global coordinated load shedding. The load of the entire system will be effectively controlled, the overload phenomenon will be alleviated, and further damage to the system will be avoided.

[0050] Furthermore, when the input side overload analysis result indicates no overload risk, and the first output branch overload analysis result among the N output branch overload analysis results indicates output side overload, the real-time overload warning is determined to be the main cause of output side overload.

[0051] When the input side overload analysis result indicates no overload risk, that is, the current on the input side does not exceed the overload threshold, the overload analysis of the output branch is continued, and the overload analysis results of N output branches are checked. If the first output branch overload analysis result indicates output side overload, the first output branch overload analysis result refers to any output branch, and the output branch has the highest overload level. This indicates that the overload of the output branch is the root cause of the system overload, rather than the current problem on the input side. In this case, the real-time overload warning is determined to be the main cause of the output side overload, and the output side overload problem is centrally addressed.

[0052] Furthermore, if the real-time overload warning is the main cause of the output side overload, an output side load reduction strategy is analyzed and generated based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output side overload on N-1 output side devices after isolation. The method includes:

[0053] In a risk scenario where the real-time overload warning is the main cause of output side overload, the real-time main cause branch device corresponding to the first output branch overload analysis result is located; the first output side overload level is extracted from the first output branch overload analysis result; if the first output side overload level is lower than the preset emergency cut-off threshold, the output isolation instruction executes the electrical isolation of the real-time main cause branch device; and the output side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output side devices after the real-time main cause branch device is cut off.

[0054] When the real-time overload warning is the main cause of output-side overload, the specific real-time main cause branch device is located based on the overload analysis results of the first output branch. If the overload analysis results of a certain output branch indicate that it is the main source of overload, that is, the current of the branch exceeds the overload threshold and has a significant impact on the overall stability of the system, then the branch is the real-time main cause branch device.

[0055] Based on the overload analysis results of the first output branch, the real-time overload level of the first output side of the main branch equipment is extracted. The overload level is determined based on the similarity between the current waveform and the historical data template, or by comparison with the preset overload threshold, including mild, moderate, severe and other classifications, indicating the degree of overload of the branch.

[0056] The emergency disconnection threshold is pre-set according to specific needs. The overload level of the first output side is compared with the preset emergency disconnection threshold. If the overload level of the branch is lower than the preset threshold, it indicates that the overload is relatively light, and there is no need to disconnect the branch immediately. In this case, an isolation instruction is output. The isolation instruction requires electrical isolation of the real-time main branch equipment to prevent the branch from continuing to affect other branches and avoid the overload problem from spreading to the entire system. Isolation can be achieved by disconnecting the circuit, cutting off the power supply or other similar means to ensure that the loads of the main branch and other branches do not interfere with each other.

[0057] After the real-time main branch device is isolated, the remaining N-1 output-side devices are simulated and analyzed to evaluate their operating status after the main branch is removed, including analyzing the behavior of these remaining branches under harmonic-load coupling disturbances. Specifically, the simulation process simulates the load changes and current distribution after the main branch is isolated, and checks whether other devices are affected or need further adjustment. Based on the simulation results, an output-side load reduction strategy is generated for the N-1 output-side devices, including: allocating load reduction tasks according to the overload risk and remaining load of the equipment, adjusting the load of each output branch, reducing the burden on other parts of the system, and ensuring that the entire system returns to a safe operating state. In this process, priority is given to reducing the load of those devices that are more affected by the harmonic-load coupling disturbance to avoid overload and ensure system stability.

[0058] Furthermore, the output-side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output-side devices after the real-time main branch device is removed. The method includes:

[0059] Construct a branch topology network of the N-1 output-side devices; after calculating the branch harmonic transfer matrix based on the branch topology network, mark the harmonic strong coupling branch pairs based on the branch harmonic transfer matrix; use the harmonic strong coupling branch pairs as harmonic constraints, perform load priority allocation for the N-1 output-side devices, and obtain the output-side load reduction strategy.

[0060] A branch topology network describes the electrical connections between N-1 output devices. By establishing this network, the interactions and influences between each branch and other branches can be clearly identified, particularly the coupling between harmonics and loads. By obtaining connection information for each output device, such as current flow direction, connection points, and power flow, a branch topology network of N-1 output devices is constructed. In this network, each output device is represented as a node, connected by edges. Edge weights represent the impedance of current transmission, harmonic coupling, or other influencing factors.

[0061] The branch harmonic transfer matrix is ​​a matrix used to describe the mutual transmission of harmonic signals between branches. It performs harmonic analysis on each branch and calculates the harmonic influence between different branches. Specifically, it performs spectral analysis on the current waveform of each branch, extracts the harmonic components, and calculates the propagation characteristics of these harmonic components between different branches. Based on these analyses, a branch harmonic transfer matrix is ​​constructed, in which each element represents the influence of the harmonic component of one branch on another branch. Specifically, the value in the matrix can represent the coupling strength of the harmonic of one branch on another branch.

[0062] Based on the calculated branch harmonic transfer matrix, we can identify pairs of branches with strong harmonic coupling. In the electrical system, when one branch is overloaded or abnormal, the load or current of the other branch may also be affected. By setting a threshold, we can mark branch pairs with high harmonic coupling intensity, namely, strong harmonic coupling branch pairs. These branch pairs require special attention during load reduction because their load changes may cause significant disturbances to other branches.

[0063] Based on the pairs of strongly coupled harmonic branches, a load priority is assigned to each output branch to determine which branches should be given priority for load reduction and which branches can continue to carry a larger load during the system load reduction process. Specifically, if the harmonic coupling strength of two branches is large and one of the branches needs to be reduced, the load of the other branch also needs to be adjusted accordingly. This is because harmonic coupling may cause abnormal fluctuations in the load, and it is necessary to ensure that these strongly coupled branches can handle overload problems together. On this basis, branches with stronger load capacity and lower overload risk are given lower priority, and branches with weaker load capacity and higher overload risk are given higher priority. Based on the load priority allocation, an output-side load reduction strategy is generated. This strategy indicates the amount of load that each output branch should reduce during the load reduction process and ensures the stability of the system.

[0064] Furthermore, if the first output side overload level is higher than the emergency removal threshold, the harmonic-load coupling disturbance characteristics of the N output side devices are simulated to generate the output side load reduction strategy.

[0065] If the overload level on the first output side is higher than the emergency cut-off threshold, that is, the overload is serious, the harmonic-load coupling disturbance characteristics of the N output-side devices are simulated. Specifically, the simulation process simulates the harmonic interaction between the N output-side devices, that is, the overload of a branch may interfere with other devices through harmonics, causing their load changes and even causing further overload problems. The simulation simulates these harmonic-load coupling effects, including: the current change of the overloaded branch may cause the change of the harmonic frequency component, and these changes are transmitted to other branches through the electrical connections within the system. The simulation process evaluates whether the load of other devices will be affected after the main branch is cut off or the load is reduced, and whether corresponding adjustments are required. Based on the simulation results, an output-side load reduction strategy is generated. For example, a load reduction priority is assigned to each branch based on the overload risk, load capacity, and harmonic coupling level of each branch, with priority given to reducing the load of equipment with strong harmonic coupling and heavy loads. The amount of load reduction required for each branch is determined based on the harmonic-load disturbance characteristics to ensure that the overall system can restore stability. Combined with the coupling effects between branches, the load reduction operations are ensured to be coordinated and consistent to prevent load reduction on one branch from exacerbating the load pressure on other branches.

[0066] In summary, the low-voltage cabinet overload warning method based on current harmonic identification provided by the embodiment of the present application has the following technical effects:

[0067] By performing real-time current monitoring on both sides of the input and output branches of the low-voltage cabinet, the current harmonic characteristic information of the input side and each output branch can be accurately captured. The generated current harmonic characteristic vector can reflect the frequency characteristics and harmonic distribution of the current waveform in detail, providing accurate input for subsequent overload analysis and early warning. Based on the current harmonic characteristic vectors of the input and output branches, the main cause of overload location analysis is performed. By comparing the current characteristics, it can be accurately determined whether the source of the overload is from the input side or the output side. This main cause location analysis can provide real-time overload early warning, quickly respond to the overload problem of the system, and help to take measures in advance to avoid system damage caused by overload. In the case where the input side overload is the main cause, the overload contribution of the branch is quantified based on the current harmonic characteristic vector of each output branch. By calculating the overload risk weight factor of each branch, the risk of overload of each output branch is quantified. The impact of the branch on the overall overload of the system can be accurately identified, so as to accurately identify which branches contribute more to the overload and give priority to overload relief, thereby improving the system's load management and response capabilities; based on the overload risk weight factor, global coordinated load reduction is performed on N output devices, which can ensure that each branch is coordinated during load reduction, avoid excessive load reduction on a branch and excessive load on other branches, thereby achieving load balancing; when the output side overload is the main cause, based on the real-time overload situation of the main branch device, its impact on other branches is analyzed, especially its harmonic-load coupling effect. Through the simulation of harmonic coupling, the output side load reduction strategy is generated to ensure that the load reduction operation of the output device not only reduces the load of the main branch, but also avoids overload of other branches due to harmonic coupling, achieving more accurate and scientific load regulation, and improving the stability and safety of the power supply system.

[0068] Embodiment 2 is based on the same inventive concept as the low voltage cabinet overload warning method based on current harmonic identification in the above embodiment. Figure 2 As shown, an embodiment of the present application provides a low-voltage cabinet overload warning device based on current harmonic identification, the device comprising:

[0069] The real-time monitoring module 10 is used to perform real-time monitoring of the current on both sides of the low-voltage cabinet, generate an input side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output side devices.

[0070] The positioning analysis module 20 is used to perform overload main cause positioning analysis based on the input side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, and output a real-time overload warning.

[0071] The contribution quantification module 30 is used to quantify the branch overload contribution based on the N output branch current harmonic characteristic vectors if the real-time overload warning is the main cause of input side overload, and output N overload risk weight factors.

[0072] The global coordinated load reduction module 40 is configured to perform global coordinated load reduction on the N output-side devices according to the N overload risk weight factors.

[0073] The load reduction strategy generation module 50 is used to analyze and generate an output side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output side overload on N-1 output side devices after isolation, if the real-time overload warning is the main cause of the output side overload.

[0074] Furthermore, the real-time monitoring module 10 is configured to perform the following steps:

[0075] The Hall current sensor installed on the busbar on the input side of the low-voltage cabinet collects the original current waveform data on the input side at a predefined sampling rate and outputs a time-series current waveform sequence; the time-series current waveform sequence is processed by grayscale mapping to output a waveform grayscale image; a preset sliding window is used to segment the waveform grayscale image into multiple segmented waveform images, wherein the overlap of adjacent time-series segmented waveform images is greater than 75%; time-series spectrum features are extracted from the multiple segmented waveform images to output multiple instantaneous harmonic feature vectors; the input side current harmonic feature vector is output by performing sliding weighted fusion on the multiple instantaneous harmonic feature vectors.

[0076] Furthermore, the positioning analysis module 20 is configured to perform the following steps:

[0077] Locally call historical overload current records, and perform fault feature vector fitting based on the historical overload current records to output a multi-level overload feature vector template; calculate the time-varying weighted similarity between the input side current harmonic feature vector and the multi-level overload feature vector template, and output the input side multi-level overload risk probability vector; preset a dynamic diagnosis threshold matrix, and obtain the input side overload analysis result by comparing the dynamic diagnosis threshold matrix with the input side multi-level overload risk probability vector; by analogy, perform synchronous overload main cause location analysis on the N output branch current harmonic feature vectors to produce N output branch overload analysis results, wherein the input side overload analysis result and the N output branch overload analysis results constitute the real-time overload warning.

[0078] Furthermore, the contribution quantification module 30 is configured to perform the following steps:

[0079] When the overload analysis results of the N output branches all indicate no overload risk, and the input side overload analysis result indicates input side overload, the real-time overload warning is determined to be the main cause of input side overload; in the risk scenario where the real-time overload warning is the main cause of input side overload, the N output side overload risk probability distributions of the N output branch current harmonic characteristic vectors are called; the branch overload contribution is quantified based on the N output side overload risk probability distributions, and the N overload risk weight factors are output.

[0080] Furthermore, the global coordinated load shedding module 40 is configured to perform the following steps:

[0081] In a risk scenario where the real-time overload warning is the main cause of input-side overload, the input-side overload level is extracted from the input-side overload analysis result; an overload adjustment scale is obtained by matching the input-side overload level in a dynamic load reduction coefficient mapping table; N collaborative load reduction instruction vectors are calculated and output based on the overload adjustment scale and N overload risk weight factors; the N collaborative load reduction instruction vectors are used to drive the N output-side devices, and a gradient load reduction operation is used to perform global collaborative load reduction.

[0082] Furthermore, when the input side overload analysis result indicates no overload risk, and the first output branch overload analysis result among the N output branch overload analysis results indicates output side overload, the real-time overload warning is determined to be the main cause of output side overload.

[0083] Furthermore, the load shedding strategy generating module 50 is configured to perform the following steps:

[0084] In a risk scenario where the real-time overload warning is the main cause of output side overload, the real-time main cause branch device corresponding to the first output branch overload analysis result is located; the first output side overload level is extracted from the first output branch overload analysis result; if the first output side overload level is lower than the preset emergency cut-off threshold, the output isolation instruction executes the electrical isolation of the real-time main cause branch device; and the output side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output side devices after the real-time main cause branch device is cut off.

[0085] Furthermore, the load shedding strategy generating module 50 is configured to perform the following steps:

[0086] Construct a branch topology network of the N-1 output-side devices; after calculating the branch harmonic transfer matrix based on the branch topology network, mark the harmonic strong coupling branch pairs based on the branch harmonic transfer matrix; use the harmonic strong coupling branch pairs as harmonic constraints, perform load priority allocation for the N-1 output-side devices, and obtain the output-side load reduction strategy.

[0087] Furthermore, if the first output side overload level is higher than the emergency removal threshold, the harmonic-load coupling disturbance characteristics of the N output side devices are simulated to generate the output side load reduction strategy.

[0088] Through the above detailed description of the low-voltage cabinet overload warning method based on current harmonic identification in this specification, those skilled in the art can clearly understand the low-voltage cabinet overload warning device based on current harmonic identification in this embodiment. Since it corresponds to the method disclosed in the embodiment, the description is relatively simple. For relevant matters, please refer to the method part description.

[0089] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A low-voltage cabinet overload warning method based on current harmonic identification is characterized by: The method comprises: Performing real-time monitoring of current on both sides of the low-voltage cabinet to generate an input-side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output-side devices; Perform overload main cause location analysis based on the input side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, and output real-time overload warning; If the real-time overload warning is the main cause of input-side overload, quantify the branch overload contribution based on the N output branch current harmonic characteristic vectors and output N overload risk weight factors; Performing global coordinated load reduction of the N output-side devices according to the N overload risk weight factors; If the real-time overload warning is the main cause of output side overload, the output side load reduction strategy is analyzed and generated based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output side overload on N-1 output side devices after isolation.

2. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 1 is characterized in that: The method further comprises: The Hall current sensor installed on the busbar on the input side of the low-voltage cabinet collects the raw current waveform data on the input side at a predefined sampling rate and outputs a time-series current waveform sequence; Processing the time-series current waveform sequence by grayscale mapping to output a waveform grayscale image; Using a preset sliding window to segment the waveform grayscale image into a plurality of segmented waveform images, wherein the overlap between adjacent time-series segmented waveform images is greater than 75%; Extracting time-series spectrum features from the plurality of segmented waveform images and outputting a plurality of instantaneous harmonic feature vectors; The input-side current harmonic feature vector is output by performing sliding weighted fusion on the multiple instantaneous harmonic feature vectors.

3. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 2 is characterized in that: Based on the input-side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, an overload main cause location analysis is performed to output a real-time overload warning, the method comprising: Locally calling historical overload current records, performing fault feature vector fitting based on the historical overload current records, and outputting a multi-level overload feature vector template; Calculating the time-varying weighted similarity between the input-side current harmonic feature vector and the multi-level overload feature vector template, and outputting the input-side multi-level overload risk probability vector; Presetting a dynamic diagnosis threshold matrix, and obtaining an input side overload analysis result by comparing the dynamic diagnosis threshold matrix with the input side multi-level overload risk probability vector; By analogy, a synchronous overload main cause location analysis is performed on the N output branch current harmonic characteristic vectors to produce N output branch overload analysis results, wherein the input side overload analysis result and the N output branch overload analysis results constitute the real-time overload warning.

4. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 3 is characterized in that: If the real-time overload warning is the main cause of input-side overload, the branch overload contribution is quantified based on the N output branch current harmonic characteristic vectors, and N overload risk weight factors are output. The method includes: When the N output branch overload analysis results all indicate no overload risk, and the input side overload analysis result indicates input side overload, determining that the real-time overload warning is the main cause of input side overload; In a risk scenario where the real-time overload warning is the main cause of input-side overload, calling N output-side overload risk probability distributions of the N output branch current harmonic characteristic vectors; The branch overload contribution is quantified based on the N output-side overload risk probability distributions, and the N overload risk weight factors are output.

5. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 4 is characterized in that: Performing global coordinated load reduction of the N output-side devices according to the N overload risk weight factors, the method comprising: In a risk scenario where the real-time overload warning is the main cause of input-side overload, extracting an input-side overload level from the input-side overload analysis result; Obtaining an overload adjustment scale by matching the dynamic load reduction coefficient mapping table according to the input side overload level; Calculating and outputting N coordinated load reduction instruction vectors according to the overload adjustment scale and N overload risk weight factors; The N coordinated load shedding instruction vectors are used to drive the N output-side devices, and a gradient load shedding operation is used to perform global coordinated load shedding.

6. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 5 is characterized in that: When the input side overload analysis result indicates no overload risk, and the first output branch overload analysis result among the N output branch overload analysis results indicates output side overload, it is determined that the real-time overload warning is the main cause of output side overload.

7. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 6 is characterized in that: If the real-time overload warning is the main cause of the output side overload, then based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output side overload on N-1 output side devices after isolation, an output side load reduction strategy is analyzed and generated, the method comprising: In a risk scenario where the real-time overload warning is the main cause of output-side overload, locating the real-time main cause branch device corresponding to the first output branch overload analysis result; Extracting a first output side overload level from the first output branch overload analysis result; If the overload level of the first output side is lower than the preset emergency removal threshold, the output isolation instruction executes the electrical isolation of the real-time main cause branch device; The output side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output side devices after the real-time main cause branch device is removed.

8. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 7 is characterized in that: The output-side load reduction strategy is generated by simulating the harmonic-load coupling disturbance characteristics of the N-1 output-side devices after the real-time main branch device is removed, and the method includes: Constructing a branch topology network of the N-1 output side devices; After calculating a branch harmonic transfer matrix based on the branch topology network, marking harmonic strong coupling branch pairs based on the branch harmonic transfer matrix; The load priority allocation of the N-1 output-side devices is performed with the harmonic strongly coupled branch pair as a harmonic constraint condition to obtain the output-side load reduction strategy.

9. The low-voltage cabinet overload warning method based on current harmonic identification according to claim 7 is characterized in that: If the first output side overload level is higher than the emergency removal threshold, the harmonic-load coupling disturbance characteristics of the N output side devices are simulated to generate the output side load reduction strategy.

10. A low voltage cabinet overload warning device based on current harmonic identification is characterized in that: A device for implementing the low-voltage cabinet overload warning method based on current harmonic identification according to any one of claims 1 to 9, comprising: A real-time monitoring module is used to perform real-time monitoring of the current on both sides of the low-voltage cabinet, generate an input-side current harmonic characteristic vector and N output branch current harmonic characteristic vectors, wherein the N output branch current harmonic characteristic vectors correspond to N output-side devices; A positioning analysis module, configured to perform overload main cause positioning analysis based on the input-side current harmonic characteristic vector and the N output branch current harmonic characteristic vectors, and output a real-time overload warning; a contribution quantification module, configured to quantify branch overload contributions based on the N output branch current harmonic characteristic vectors and output N overload risk weight factors if the real-time overload warning is the main cause of input-side overload; A global coordinated load reduction module, configured to perform global coordinated load reduction of the N output-side devices according to the N overload risk weight factors; The load reduction strategy generation module is used to analyze and generate an output side load reduction strategy based on the harmonic-load coupling disturbance characteristics of the real-time main cause branch device corresponding to the main cause of the output side overload on N-1 output side devices after isolation, if the real-time overload warning is the main cause of the output side overload.

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