Gain and PVT robust capacitance degradation dynamic amplifier circuit and module

Abstract

The invention discloses a capacitance degradation dynamic amplifier circuit and module with stable gain and PVT, and relates to the technical field of capacitance degradation dynamic amplifier design. The invention designs a capacitance degradation dynamic amplifier circuit, which samples and amplifies input signals VIP and VIN into gain signals VOP and VON through an amplifier part, and performs zero-cross detection on the VOP and VON through a zero-cross detection part to determine whether a preset gain target is reached or not. And the clock control part generates a stop signal phi SW to control the amplifier part to stop amplification when the zero-cross detection part detects that the preset gain target is reached, so that the circuit focuses on the actual amplification condition and is separated from the PVT condition to eliminate the influence of PVT change, and stable differential gain of the circuit is realized.

Description

Technical Field

[0001] The present invention relates to the technical field of capacitor degradation dynamic amplifier design, and more specifically, to: 1. a capacitor degradation dynamic amplifier circuit with robust gain and PVT; 2. a capacitor degradation dynamic amplifier module designed based on the capacitor degradation dynamic amplifier circuit; and 3. a pipelined successive approximation analog-to-digital converter module including the capacitor degradation dynamic amplifier module. Background Art

[0002] The residual amplifier is a key component of the Pipelined SAR ADC (Pipelined Successive Approximation Analog-to-Digital Converter). It needs to have sufficiently high gain, speed, and low enough noise to avoid degrading the overall ADC performance.

[0003] Currently, the residual amplifiers commonly used in pipelined SAR ADCs mainly include closed-loop amplifiers and open-loop dynamic amplifiers. Closed-loop amplifiers are generally based on op amp designs and adopt a gain-bootstrapping architecture. They can achieve both high gain and wide bandwidth, but this significantly increases power consumption. Open-loop dynamic amplifiers offer significant advantages in speed, power consumption, and output swing, but their performance is easily affected by process corners, power supply voltage, and temperature (PVT), leading to low gain and unstable operation.

[0004] Therefore, the present invention considers designing a capacitance-degraded dynamic amplifier (which is an optimized form of an open-loop dynamic amplifier) ​​to ensure gain and PVT robustness. Summary of the Invention

[0005] Based on this, it is necessary to provide a capacitance-degraded dynamic amplifier circuit and module with robust gain and PVT to address the problem that the existing open-loop dynamic amplifier is easily affected by PVT.

[0006] The present invention is achieved by adopting the following technical solutions:

[0007] In a first aspect, the present invention provides a capacitance-degraded dynamic amplifier circuit with robust gain and PVT, comprising: an amplifier section, a zero-crossing detection section, and a clock control section.

[0008] The amplifier section is used to sample the input signals VIP and VIN in combination with the common mode voltage VCM and the power supply voltage VDD and amplify them into gain signals VOP and VON. The zero-crossing detection section is used to perform zero-crossing detection on VOP and VON in combination with VCM and VDD to determine whether the preset gain target is achieved. The clock control section is used to generate a stop signal Φ when the zero-crossing detection section detects that the preset gain target has been achieved. SW To control the amplifier unit to stop amplification.

[0009] The preset gain target is: VOP-VON=α×(VIP-VIN); α represents the preset gain multiple.

[0010] The implementation of such a gain and PVT robust capacitor-degraded dynamic amplifier circuit is in accordance with a method or process of an embodiment of the present disclosure.

[0011] In a second aspect, the present invention discloses a capacitance-degraded dynamic amplifier module, which adopts the circuit layout of the capacitance-degraded dynamic amplifier circuit with robust gain and PVT as disclosed in the first aspect.

[0012] The implementation of the capacitance-degraded dynamic amplifier module is based on the method or process of an embodiment of the present disclosure.

[0013] In a third aspect, the present invention discloses a pipelined successive approximation analog-to-digital converter module, which includes the gain and PVT robust capacitor degradation dynamic amplifier module disclosed in the first aspect.

[0014] The implementation of the pipelined successive approximation analog-to-digital converter module is in accordance with the method or process of an embodiment of the present disclosure.

[0015] Compared with the prior art, the present invention has the following beneficial effects:

[0016] 1. The present invention designs a capacitor degradation dynamic amplifier circuit, which samples the input signals VIP and VIN through an amplifier part and amplifies them into gain signals VOP and VON. The zero-crossing detection part performs zero-crossing detection on VOP and VON to determine whether a preset gain target is reached, and the clock control part generates a stop signal Φ when the zero-crossing detection part detects that the preset gain target is reached. SW This controls the amplifier section to stop amplification; this allows the circuit to focus on the actual amplification situation and to be separated from the PVT conditions to eliminate the influence of PVT changes, thereby achieving a stable differential gain of the circuit.

[0017] 2. The present invention superimposes a MOS transistor on the input MOS transistor of the amplifier part to form a cascode structure, and uses a common-mode voltage VCM to bias the superimposed cascode transistor, so that the amplifier part can obtain a larger output swing and gain while working more stably. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0019] Figure 1 A circuit structure diagram of a capacitance-degraded dynamic amplifier circuit with robust gain and PVT provided in Example 1 of the present invention;

[0020] Figure 2 for Figure 1 Circuit diagram of the bias section of the amplifier section;

[0021] Figure 3 for Figure 1 The circuit diagram of the main amplifier part of the amplifier section;

[0022] Figure 4 for Figure 1 Circuit diagram of static amplifier;

[0023] Figure 5 for Figure 1 Circuit diagram of the clock control unit;

[0024] Figure 6 The control signals Φ1, Φ2, Φ provided in the embodiment 1 of the present invention are A Timing diagram of

[0025] Figure 7 The gain amplification simulation results provided by Example 1 of the present invention are Figure 1 ;

[0026] Figure 8 The gain amplification simulation results provided by Example 1 of the present invention are Figure 2 ;

[0027] Figure 9 The gain amplification simulation results provided by Example 1 of the present invention are Figure 3 ;

[0028] Figure 10 The gain amplification simulation results provided by Example 1 of the present invention are Figure 4 ;

[0029] Figure 11 This is a gain error variation diagram provided by Example 1 of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0031] It should be noted that when a component is referred to as being "mounted on" another component, it may be directly on the other component or there may be a central component. When a component is considered to be "set on" another component, it may be directly set on the other component or there may be a central component. When a component is considered to be "fixed to" another component, it may be directly fixed to the other component or there may be a central component.

[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this invention pertains. The terms used herein in the specification of the present invention are for the purpose of describing specific embodiments only and are not intended to limit the present invention. The term "or / and" as used herein includes any and all combinations of one or more of the associated listed items.

[0033] First, it should be noted that the gain- and PVT-robust capacitor-degradation dynamic amplifier circuit and module designed in this invention are specifically designed for pipelined SAR ADCs to meet their high gain, high speed, and low noise requirements. Furthermore, the gain- and PVT-robust capacitor-degradation dynamic amplifier circuit and module designed in this invention are designed to achieve excellent PVT resistance.

[0034] Example 1

[0035] See Figure 1 , which is a circuit structure diagram of the gain and PVT robust capacitance degradation dynamic amplifier circuit provided in this embodiment 1, which includes: an amplifier part, a zero-crossing detection part, and a clock control part.

[0036] The following describes each of the three parts:

[0037] 1. The amplifier section is used to sample the input signals VIP and VIN in combination with the common-mode voltage VCM and the power supply voltage VDD and amplify them into gain signals VOP and VON.

[0038] The amplifier part adopts a dynamic amplifier design based on the capacitance degradation principle, which includes: a bias part and an amplifier main body part.

[0039] 101. The bias unit is used to provide bias voltages VBP and VBN to the amplifier main unit.

[0040] See Figure 2 The bias part can be designed to include: 4 PMOS transistors PM5~PM8, 4 NMOS transistors NM5~NM8, and 1 current source IBias1.

[0041] The input of IBias1 is connected to VDD, and the output is connected to the source of PM5;

[0042] The drain of PM5 is connected to the source of PM6; the gate of PM5, the drain of PM6, and the gate of PM7 are connected together and used to output VBP; the source of PM7 is connected to VDD, and the drain is connected to the source of PM8; the gate of PM8 is connected to the gate of PM6;

[0043] The drain of NM5 is connected to the drain of PM6, the gate is connected to the gate of NM7, and the source is connected to the drain of NM6; the gate of NM6, the drain of NM7, and the gate of NM8 are connected together and used to output VBN; the drain of NM7 is connected to the drain of PM8; the source of NM8 and the source of NM6 are connected to VSS.

[0044] Of course, the bias unit may also adopt other designs, but it must meet the above output signal requirements.

[0045] 102. The main amplifier part serves as the main circuit for sampling and amplification, and is designed based on four pairs of common-source and common-gate transistors.

[0046] See Figure 3 The main body of the amplifier includes: 4 PMOS tubes PM1~PM4, 4 NMOS tubes NM1~NM4, and 2 degeneration capacitors C DEG1 ~C DEG2 , 4 sampling capacitors C 11 ~C 14 , 6 Class A switches S 11 ~S 16 , 6 Class II switches S 21 ~S 26 , 2 Category 3 switches S A1 ~S A2 , 4 Category 4 switches S W1 ~S W4 .

[0047] The gate of PM1 is connected to S 11 The first end, C 11 Upper plate; S 11 The second end of the C 11 The lower plate is connected to S 21 The first end, C 12 The lower plate, S A1 The first end of S 21 The second end of the S A1 The second end of PM1 is connected to VCM; the source of PM1 is connected to S W2 The first end of the drain is connected to the source of PM2; S W2 The second end is connected to S 23 The first end, C DEG2The gate of PM2 and the gate of NM1 are connected to VCM; the drain of PM2 is connected to the drain of NM1; the drain of PM2 is connected to the drain of NM1 through S 15 Connect to VCM; NM1's drain connects to VOP; NM1's source connects to NM2's drain; NM2's gate connects to C 12 Upper plate, S 12 The first end of S 12 The second end of NM2 is connected to VBN; the source of NM2 is connected to S W4 The first end of S W4 The second end is connected to S 25 The first end, C DEG1 The gate of PM3 is connected to S 13 The first end, C 13 Upper plate; S 13 The second end of the C 13 The lower plate is connected to S 22 The first end, C 14 The lower plate, S A2 The first end of S 22 The second end of S is connected to VIN; A2 The second end of PM3 is connected to VCM; the source of PM3 is connected to S W3 The first end of the drain is connected to the source of PM4; S W3 The second end is connected to S 24 The first end, C DEG1 The gate of PM4 and the gate of NM3 are connected to VCM; the drain of PM4 is connected to the drain of NM3; the drain of PM4 is connected to the drain of NM3 through S 16 Connect to VCM; NM3's drain connects to VON; NM3's source connects to NM4's drain; NM4's gate connects to C 14 Upper plate, S 14 The first end of S 14 The second end of NM4 is connected to VBN; the source of NM4 is connected to S W1 The first end of S W1 The second end is connected to S 26 The first end, C DEG2 The lower plate; S 23 The second end, S 24 The second end of S is connected to VDD; 25 The second end, S 26 The second end is connected to the ground VSS.

[0048] In other words, PM1 and PM2 form the first pair of cascode transistors; NM1 and NM2 form the second pair; PM3 and PM4 form the third pair; and NM3 and NM4 form the fourth pair. The cascode transistors protect the voltage at the drain of the input transistors. Since the capacitively degraded amplifier operates in the subthreshold region, the cascode design allows for more stable operation in this region. Furthermore, using VCM to bias the stacked cascode transistors allows the amplifier section to achieve greater output swing and gain while also providing more stable operation.

[0049] C T1 、C F1 Can be regarded as a load capacitor C L1 ; C T2 、C F2 Can be regarded as a load capacitor C L2 It should be noted that C T1 、C F1 、C T2 、C F2 The capacitance value satisfies: C T1 / C F1 =C T2 / C F2 =α-1; where α represents the preset gain multiple.

[0050] In addition, the switch of the enlarged main body must meet the following requirements:

[0051] S 11 ~S 16 Synchronize on or off; S 21 ~S 26 Synchronize on or off; S A1 ~S A2 Synchronize on or off; S W1 ~S W4 Synchronization on or off.

[0052] In this embodiment 1, the same control signal is used to control the switch: S 11 ~S 16 Controlled uniformly by the control signal Φ1; S 21 ~S 26 Controlled uniformly by the control signal Φ2; S A1 ~S A2 By the control signal Φ A Unified control; S W1 ~S W4 By Φ SW Unified control.

[0053] 2. The zero-crossing detection unit is used to perform zero-crossing detection on VOP and VON in combination with VCM and VDD to determine whether the preset gain target is achieved.

[0054] It should be noted that the preset gain target is: VOP-VON=α×(VIP-VIN).

[0055] Different from the traditional approach of using additional PVT compensation to correct PVT effects, the present invention adopts a zero-crossing detection approach and designs a zero-crossing detection unit.

[0056] See Figure 1 The zero-crossing detection unit is designed to include: 2 comparators Comp1~Comp2, 2 switches S1~S2, 2 fixed capacitors C F1 ~C F2 , 2 detection capacitors C T1 ~C T2 .

[0057] C F1 The upper plate is connected to VON; C F1 The lower plate, C T1 The upper plate and the first end of S1 are connected together and used to output the node voltage V TN ; The second end of S1 is connected to VCM; C T1 The lower plate of Comp1 is connected to GND; the negative input of Comp1 is connected to V TN , the positive input terminal is connected to VIN, and the control terminal is connected to the control signal Φ A , the power supply end is connected to VDD, and the output end is connected to the clock control unit;

[0058] C F2 The upper plate is connected to VOP; C F2 The lower plate, C T2 The upper plate of S2 and the first end of S2 are connected together and used to output the node voltage V TP ; The second end of S2 is connected to VCM; C T2 The lower plate of Comp2 is connected to GND; the negative input terminal of Comp2 is connected to V TP , the positive input terminal is connected to VIP, and the control terminal is connected to Φ A , the power supply end is connected to VDD, and the output end is connected to the clock control part.

[0059] It should be noted that S1~S2, S 11 ~S 16 Synchronous opening or closing. Referring to the above, in this embodiment 1, S1-S2 are also uniformly controlled by the control signal Φ1.

[0060] It should be noted that zero-crossing detection actually checks whether VON and VIP have reached the preset gain conditions; that is, the zero-crossing detector needs to perform real-time detection of VON and VIP, so Comp1~Comp2 must use static comparators (which support real-time detection) and cannot use dynamic comparators (which do not support real-time detection).

[0061] Comparators Comp1~Comp2 can be used Figure 5 The design of comparator Comp i It includes: 5 PMOS tubes P1~P5, 2 NMOS tubes N1~N2, 1 inverter INV, and 1 current source IBias2; i∈[1,2].

[0062] In Comp i Middle: The source of P1 is connected to the source of P5 and acts as Comp i The gate of P1, the gate of P5, and the drain of P5 are connected to the input of IBias2; the drain of P1 is connected to the source of P2; the gate of P2 is used as Comp i The source of P3 and P4 are connected to the drain of P2; the gate of P3 is used as Comp i The positive input terminal (i.e. Figure 4 IN1 in the circuit); the gate of P4 acts as Comp i The negative input terminal (i.e. Figure 4 IN2 in the circuit); the drain of P3 is connected to the drain of N2 and serves as Comp i The output terminal (i.e. Figure 4 The gate of N2 is connected to the gate of N1, the drain of N1, and the drain of P4; the output end of IBias2, the source of N2, and the source of N1 are grounded to VSS.

[0063] Then, for Comp1, its IN1 is VIP, IN2 is V TP For Comp2, IN1 is VIN and IN2 is V TN .

[0064] 3. The clock control unit is used to generate a stop signal Φ when the zero-crossing detection unit detects that the preset gain target has been reached. SW To control the amplifier unit to stop amplification.

[0065] See Figure 5 The clock control unit can be designed to include: two TSPC type triggers TSPC1~TSPC2, one NOR gate, and one AND gate.

[0066] The RST reset terminal of TSPC1 is connected to the output terminal of Comp1, the Q output terminal is connected to the input terminal 1 of NOR, and the CLK timing control terminal is connected to the control signal Φ A ; The RST reset terminal of TSPC2 is connected to the output terminal of Comp2, the Q output terminal is connected to the second input terminal of NOR, and the CLK timing control terminal is connected to Φ A ; The output of NOR is connected to the input of AND; the input of AND is connected to Φ A , the output terminal is used to output Φ SW .

[0067] It should be noted that TSPC1 to TSPC2 are TSPC type flip-flops, and if a rising edge is detected when the CLK timing control terminal is 1, the Q output terminal changes from 0 to 1.

[0068] See Figure 6 ,Based on the gain and PVT robust capacitor degradation dynamic amplifier circuit designed above,,it has two working stages: sampling stage and amplification stage.

[0069] ①In the sampling stage:

[0070] Φ1 and Φ2 are first high and then switch to low, and Φ1 switches to low earlier than Φ2. A is low level.

[0071] Specifically, due to Φ A Keep low, AND output Φ SW Keep it at 0, S W1 ~S W4 are disconnected, the main amplifier part does not work; the bias part generates VBP and VBN under the action of IBias1; since Φ1 and Φ2 are high level first, Φ A is low level, S1~S2, S 11 ~S 16 、S 21 ~S 26 All conduction, S A1 ~S A2 All turned off; C 11 、C 13 The upper plate is connected to VBP, and the lower plate is connected to VIP; C 12 、C 14 The upper plate is connected to VBN, and the lower plate is connected to VIN; V TP 、V TN Connected to VCM and maintained as VCM; C DEG1 The upper and lower plates are connected to VDD and VSS, then C DEG1 The upper plate is charged to VDD; C DEG2 The upper and lower plates of the C DEG2The top plate is charged to VDD.

[0072] Since Φ1 becomes low level before Φ2, C 11 ~C 14 The upper plate will float, causing the upper plate level to follow the change of the lower plate level until Φ A Changes to high level, C 11 ~C 14 The lower plate is set to VCM to achieve sampling.

[0073] ②In the amplification stage:

[0074] Φ1 and Φ2 are low level, Φ A is high level.

[0075] Specifically, once the amplification phase is entered, Φ A That is, switch to high level, S A1 ~S A2 Since TSPC1 and TSPC2 do not receive the comparator flip at this time, the outputs of TSPC1 and TSPC2 are both 0, NOR outputs 1, and AND outputs Φ SW Switch to 1, S W1 ~S W4 Both are turned on, and the main amplifier starts to work. Φ1 and Φ2 are low level, S 11 ~S 16 、S 21 ~S 26 All remain off; C 11 ~C 14 The lower plate of C is connected to VCM and is reset to VCM. DEG1 The upper plate of the capacitor is connected to VON through PM3 and PM4 to discharge, and the capacitor is L1 Accumulated charge on DEG1 The lower plate of the battery is connected to VOP through NM1 and NM2 for charging, and L2 Charge accumulates on the surface. C DEG2 The upper plate of the capacitor is connected to VOP through PM1 and PM2 to discharge, and L2 Accumulated charge on DEG2 The lower plate of the battery is connected to VON through NM3 and NM4 for charging, and the L1 Accumulated charge on.

[0076] Since in the sampling stage, V TP 、V TN Maintain VCM, and C T1 / C F1 =C T2 / C F2 =α-1, then considering the capacitor voltage division, we have: (VOP-VCM) / (VTP -VCM)=α、(VON-VCM) / (V TN -VCM)=α. In the amplification stage, S1~S2 are kept off, V TP As VOP increases, V TN As VON increases, it also increases slowly until V TP The size relationship with VIP is reversed, or V TN If any of the following situations occurs: the relationship between VOP and VIN is reversed, it means that VOP and VON have reached the preset gain target. At this time, Comp1 and Comp2 output at least one 1; TSPC1 and TSPC2 also output at least one 1 after receiving the comparator reversal; NOR outputs 0 based on the output of TSPC1 and TSPC2; Φ A is high, then the AND output Φ SW Switching to 0 further turns off SW1 and SW2, stopping the amplifier section from amplifying.

[0077] Simulation Verification

[0078] In order to illustrate the amplification effect and PVT resistance of the present invention, this embodiment 1 simulates the above-mentioned gain and PVT robust capacitor degradation dynamic amplifier circuit under various PVT conditions, taking α=8. The simulation curve results are shown as follows: Figures 7 to 10 As shown, the gain error changes as Figure 11 shown.

[0079] in, Figure 7 The signal change curve under condition 1 (Corner: ff, Temperature: 50°C, Voltage: 0.9V) is shown. It can be seen that the capacitor-degraded dynamic amplifier circuit of Example 1 well achieves 8x gain amplification under condition 1, and the amplification takes 4.1ns to complete.

[0080] Figure 8 The signal change curve under condition 2 (Corner: ss, Temperature: 25°C, Voltage: 1V) is shown. It can be seen that the capacitor-degraded dynamic amplifier circuit of Example 1 well achieves 8x gain amplification under condition 2, and the amplification takes 3.5ns to complete.

[0081] Figure 9 The signal change curve of condition 3 (Corner: ff, Temperature: 80°C, Voltage: 0.9V) is shown. It can be seen that the capacitor-degraded dynamic amplifier circuit of Example 1 well achieves 8x gain amplification under condition 3, and the amplification takes 3.3ns to complete.

[0082] Figure 10The signal change curve of condition 4 (Corner: tt, Temperature: 0°C, Voltage: 0.8V) is shown. It can be seen that the capacitor-degraded dynamic amplifier circuit of Example 1 well achieves 8x gain amplification under condition 4, and the amplification takes 1.2ns to complete.

[0083] Figure 11 The variation of the gain error of the capacitor-degraded dynamic amplifier circuit of the first embodiment with temperature is shown. It can be seen that the gain error fluctuates within ±3%, indicating that the capacitor-degraded dynamic amplifier circuit of the first embodiment has good amplification accuracy.

[0084] In summary, the capacitor-degraded dynamic amplifier circuit of the first embodiment has excellent anti-PVT performance.

[0085] Example 2

[0086] This embodiment 2 also discloses a gain- and PVT-robust capacitor-degraded dynamic amplifier module, which utilizes the circuit layout of the aforementioned gain- and PVT-robust capacitor-degraded dynamic amplifier circuit. The module packaging facilitates the promotion and application of the aforementioned capacitor-degraded dynamic amplifier circuit.

[0087] According to the specific circuit design in Example 1, the pins of the capacitance degradation dynamic amplifier with robust gain and PVT include: 11 pins. Among them, pin 1 is used to connect to VDD; pin 2 is used to connect to VSS; pin 3 is used to connect to GND; pin 4 is used to connect to VIN; pin 5 is used to connect to VIP; pin 6 is used to connect to VON; pin 7 is used to connect to VOP; pin 8 is used to connect to VCM; pin 9 is used to connect to Φ1; pin 10 is used to connect to Φ2; pin 11 is used to connect to Φ A .

[0088] In addition, this embodiment 2 also discloses a pipelined successive approximation analog-to-digital converter module, including the above-mentioned gain and PVT robust capacitor degradation dynamic amplifier module. The pipelined successive approximation analog-to-digital converter module has excellent conversion performance.

[0089] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0090] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the patent for this invention shall be determined by the appended claims.

Claims

1. A capacitance-degraded dynamic amplifier circuit with robust gain and PVT, characterized in that: include: An amplifier section, which is used to sample the input signals VIP and VIN in combination with the common mode voltage VCM and the power supply voltage VDD and amplify them into gain signals VOP and VON; A zero-crossing detection unit is used to perform zero-crossing detection on VOP and VON in combination with VCM and VDD to determine whether a preset gain target is reached; wherein the preset gain target is: VOP-VON=α×(VIP-VIN); α represents the preset gain multiple; as well as The clock control unit is configured to generate a stop signal Φ when the zero-crossing detection unit detects that the preset gain target has been reached. SW To control the amplifier unit to stop amplification.

2. The gain and PVT robust capacitance degradation dynamic amplifier circuit according to claim 1, characterized in that: The amplifier section includes: a bias section and an amplifier main body section; The bias part is used to provide bias voltages VBP and VBN to the amplifier main body part; The main amplifier part includes: 4 PMOS transistors PM1~PM4, 4 NMOS transistors NM1~NM4, and 2 degeneration capacitors C DEG1 ~C DEG2 , 4 sampling capacitors C 11 ~C 14 , 6 Class A switches S 11 ~S 16 , 6 Class II switches S 21 ~S 26 , 2 Category 3 switches S A1 ~S A2 , 4 Category 4 switches S W1 ~S W4 ; The gate of PM1 is connected to S 11 The first end, C 11 Upper plate; S 11 The second end of the C 11 The lower plate is connected to S 21 The first end, C 12 The lower plate, S A1 The first end of S 21 The second end of the S A1 The second end of PM1 is connected to VCM; the source of PM1 is connected to S W2 The first end of the drain is connected to the source of PM2; S W2 The second end is connected to S 23 The first end, C DEG2 The gate of PM2 and the gate of NM1 are connected to VCM; the drain of PM2 is connected to the drain of NM1; the drain of PM2 is connected to the drain of NM1 through S 15 Connect to VCM; NM1's drain connects to VOP; NM1's source connects to NM2's drain; NM2's gate connects to C 12 Upper plate, S 12 The first end of S 12 The second end of NM2 is connected to VBN; the source of NM2 is connected to S W4 The first end of S W4 The second end is connected to S 25 The first end, C DEG1 The gate of PM3 is connected to S 13 The first end, C 13 Upper plate; S 13 The second end of the C 13 The lower plate is connected to S 22 The first end, C 14 The lower plate, S A2 The first end of S 22 The second end of S is connected to VIN; A2 The second end of PM3 is connected to VCM; the source of PM3 is connected to S W3 The first end of the drain is connected to the source of PM4; S W3 The second end is connected to S 24 The first end, C DEG1 The gate of PM4 and the gate of NM3 are connected to VCM; the drain of PM4 is connected to the drain of NM3; the drain of PM4 is connected to the drain of NM3 through S 16 Connect to VCM; NM3's drain connects to VON; NM3's source connects to NM4's drain; NM4's gate connects to C 14 Upper plate, S 14 The first end of S 14 The second end of NM4 is connected to VBN; the source of NM4 is connected to S W1 The first end of S W1 The second end is connected to S 26 The first end, C DEG2 The lower plate; S 23 The second end, S 24 The second end of S is connected to VDD; 25 The second end, S 26 The second end is connected to the ground VSS; Among them, C T1 、C F1 、C T2 、C F2 The capacitance value satisfies: C T1 / C F1 =C T2 / C F2 =α-1; S 11 ~S 16 Synchronize on or off; S 21 ~S 26 Synchronize on or off; S A1 ~S A2 Synchronize on or off; S W1 ~S W4 Synchronization on or off.

3. The gain and PVT robust capacitance degradation dynamic amplifier circuit according to claim 2, wherein: The bias unit includes: 4 PMOS transistors PM5-PM8, 4 NMOS transistors NM5-NM8, and 1 current source IBias1; The input of IBias1 is connected to VDD, and the output is connected to the source of PM5; The drain of PM5 is connected to the source of PM6; the gate of PM5, the drain of PM6, and the gate of PM7 are connected together and used to output VBP; the source of PM7 is connected to VDD, and the drain is connected to the source of PM8; the gate of PM8 is connected to the gate of PM6; The drain of NM5 is connected to the drain of PM6, the gate is connected to the gate of NM7, and the source is connected to the drain of NM6; the gate of NM6, the drain of NM7, and the gate of NM8 are connected together and used to output VBN; the drain of NM7 is connected to the drain of PM8; the source of NM8 and the source of NM6 are connected to VSS.

4. The gain and PVT robust capacitance degradation dynamic amplifier circuit according to claim 2 or 3, characterized in that: The zero-crossing detection unit includes: 2 comparators Comp1~Comp2, 2 switches S1~S2, 2 fixed capacitors C F1 ~C F2 , 2 detection capacitors C T1 ~C T2 ; C F1 The upper plate is connected to VON; C F1 The lower plate, C T1 The upper plate and the first end of S1 are connected together and used to output the node voltage V TN ; The second end of S1 is connected to VCM; C T1 The lower plate of Comp1 is connected to GND; the negative input of Comp1 is connected to V TN , the positive input terminal is connected to VIN, and the control terminal is connected to the control signal Φ A , the power supply end is connected to VDD, and the output end is connected to the clock control unit; C F2 The upper plate is connected to VOP; C F2 The lower plate, C T2 The upper plate of S2 and the first end of S2 are connected together and used to output the node voltage V TP ; The second end of S2 is connected to VCM; C T2 The lower plate of Comp2 is connected to GND; the negative input terminal of Comp2 is connected to V TP , the positive input terminal is connected to VIP, and the control terminal is connected to Φ A , the power supply end is connected to VDD, and the output end is connected to the clock control unit; Among them, S1~S2, S 11 ~S 16 Synchronization on or off.

5. The gain and PVT robust capacitance degradation dynamic amplifier circuit according to claim 4, wherein: Comparator i Includes: 5 PMOS tubes P1~P5, 2 NMOS tubes N1~N2, 1 inverter INV, 1 current source IBias2; i∈[1,2]; In Comp i Middle: The source of P1 is connected to the source of P5 and acts as Comp i The gate of P1, the gate of P5, and the drain of P5 are connected to the input of IBias2; the drain of P1 is connected to the source of P2; the gate of P2 is used as Comp i The source of P3 and P4 are connected to the drain of P2; the gate of P3 is used as Comp i The positive input terminal of P4; the gate of P4 serves as Comp i The negative input terminal of P3; the drain of P3 is connected to the drain of N2 and serves as Comp i The output terminal of N2; the gate of N2 is connected to the gate of N1, the drain of N1, and the drain of P4; the output terminal of IBias2, the source of N2, and the source of N1 are grounded to VSS.

6. The capacitance-degraded dynamic amplifier circuit with robust gain and PVT according to claim 4, wherein: The clock control unit includes: two TSPC type flip-flops TSPC1-TSPC2, one NOR gate, and one AND gate; The RST reset terminal of TSPC1 is connected to the output terminal of Comp1, the Q output terminal is connected to the input terminal 1 of NOR, and the CLK timing control terminal is connected to the control signal Φ A ; The RST reset terminal of TSPC2 is connected to the output terminal of Comp2, the Q output terminal is connected to the second input terminal of NOR, and the CLK timing control terminal is connected to Φ A ; The output of NOR is connected to the input of AND; the input of AND is connected to Φ A , the output terminal is used to output Φ SW .

7. The gain and PVT robust capacitance degradation dynamic amplifier circuit according to claim 2 or 3, characterized in that: S1~S2、S 11 ~S 16 Controlled uniformly by control signal Φ1; S 21 ~S 26 Controlled uniformly by control signal Φ2; S A1 ~S A2 By Φ A unified control; S W1 ~S W4 By Φ SW Unified control.

8. The gain and PVT robust capacitance degradation dynamic amplifier circuit according to claim 7, wherein: In the sampling phase, Φ1 and Φ2 are first high and then switch to low, and Φ1 switches to low earlier than Φ2. A is low level; In the amplification stage, Φ1 and Φ2 are low level, Φ A is high level.

9. A capacitance-degraded dynamic amplifier module with robust gain and PVT, characterized in that: It adopts the circuit layout of the gain and PVT robust capacitance degradation dynamic amplifier circuit as described in any one of claims 1-8.

10. A pipelined successive approximation analog-to-digital converter module, characterized in that: It includes the gain and PVT robust capacitance degradation dynamic amplifier module as claimed in claim 9.

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