Power line carrier communication data processing method, processor, communication terminal and system

Abstract

The invention belongs to the technical field of power line carrier communication, and relates to a power line carrier communication data processing method, a processor, a communication terminal and a system. The data polls are distributed and stored to four single-port read-write memories, and binary representation of the initial address index of each data is obtained; calculating the number of iteration layers of the radix-4 FFT, the number of butterfly operation groups in each layer of iteration, and the inter-butterfly data index difference and the intra-butterfly data index difference in each layer of iteration; rounding down the quotient of the initial address index of each data and the intra-butterfly data index difference in each layer of iteration to obtain a loop right shift value, and adding the binary representation of the initial address index and the binary representation of the loop right shift value to obtain the binary representation of the target address index of each data in each layer of iteration; therefore, each piece of data is stored in the single-port read-write memories according to the target address index, and four pieces of data to be processed are read in parallel from the four single-port read-write memories according to a fast Fourier transform rule so as to carry out fast Fourier transform.

Description

Technical Field

[0001] The present invention relates to the technical field of power line carrier communication, and in particular to a power line carrier communication data processing method, a processor, a communication terminal, a power line carrier communication system, and a computer-readable storage medium. Background Art

[0002] Power line carrier communication (PLC) is a technology that uses existing power lines as a communication medium to achieve data transmission. It superimposes high-frequency signals on alternating current to simultaneously transmit power and data, eliminating the need for laying additional communication lines. In current PLC systems, OFDM modulation technology is primarily used to modulate information onto multiple effective subcarriers. In OFDM technology, both time-domain and frequency-domain signal conversion is achieved through Fast Fourier Transform (FFT) / Inverse Fast Fourier Transform (IFFT). To meet the data transmission and reception rate requirements in PLC communication, strict requirements are placed on the data processing time during FFT or IFFT calculations. Excessive processing time may result in loss of received or transmitted data, leading to communication failure.

[0003] A prior art data processing method based on radix-4 FFTs (FFTs) has been proposed. This method performs a discrete Fourier transform (DFT) on N discrete time-domain data points. The core logic of this method is to decompose the N-point DFT into log4N layers of iterative computations. Each layer decomposes the data conversion problem into four sub-problems, ultimately transforming them into parallel computations performed by butterfly units. For example, when N is 16, the first layer decomposes the DFT of 16 discrete time-domain data points into four 4-point DFTs. The second layer decomposes each 4-point DFT into four 1-point DFTs. In other words, each butterfly unit in the second layer processes four data points simultaneously and directly outputs the frequency domain information for each data point. Because the butterfly computation in a radix-4 FFT requires simultaneous reading of four discrete time-domain data points, real-time reading of these four data points requires at least four clock cycles, which impacts data processing timeliness. As the number of data to be processed increases, the data processing cycle increases, making it impossible to effectively improve data processing timeliness and, consequently, failing to meet the data analysis timeliness requirements of power line carrier communications.

[0004] There are two ways to obtain four pieces of data to be processed within a single clock cycle: one is to set up a four-port read-write memory, and the other is to set up four single-port read-write memories. A four-port read-write memory integrates four independent sets of address lines, data lines, and control logic. It requires independent access channels for each port, conflict arbitration logic, and complex wiring resources to connect each port and storage unit. This not only increases hardware complexity and timing delays, but also increases dynamic power consumption when multiple address decoders and data buffers operate simultaneously. A single-port read-write memory, on the other hand, contains an independent set of address lines, data lines, and control signals. Only one read or write operation can be performed at a time through a single port, resulting in a simple hardware structure and low resource usage. Therefore, the prior art began using four single-port read-write memories for data storage. Specifically, the data in the discrete time domain data sequence is sequentially stored in the four single-port read-write memories in a round-robin manner. This allows the data to be read from the four single-port read-write memories in parallel within a single clock cycle during FFT processing.

[0005] However, this round-robin data storage method still has the problem of data that need to be processed in parallel being allocated to the same memory, which makes it impossible to obtain multiple data to be processed within one clock cycle; for example, when the number of data to be processed is 1024, according to the processing rules of the radix-4 FFT, the 0th, 256th, 512th, and 768th data need to be processed in parallel in the first layer iteration, and the data polling allocation method causes these data to be allocated to the first memory, and still needs to be acquired in four clock cycles, resulting in a longer data parsing time at the receiving end, which cannot meet the requirements of power line carrier communication for data processing timeliness. Summary of the Invention

[0006] To this end, the technical problem to be solved by the present invention is to overcome the problem that the power line carrier communication receiving end in the prior art uses a 4-FFT data processing method to parse and process the received signal, which has a long acquisition cycle for the data to be processed, and thus leads to a long data processing cycle, and cannot meet the requirements of power line carrier communication for data processing timeliness.

[0007] To solve the above technical problems, the present invention provides a power line carrier communication data processing method, which is applied to a processor of a power line carrier communication system, comprising: The data in the discrete data sequence are polled and distributed and stored in four single-port read-write memories, thereby obtaining a binary representation of the initial address index of each data; wherein the initial address index includes an initial chip select address and an initial on-chip address; Based on the number of data in the discrete data sequence, the number of radix-4 FFT iteration layers and the number of butterfly operation groups in each iteration layer are calculated, thereby calculating the inter-butterfly data index difference and the intra-butterfly data index difference in each iteration layer; The quotient of the initial address index of each data and the difference between the data indexes in each iteration layer is rounded down to the nearest integer to obtain the corresponding cyclic right shift value of each data in each iteration layer, thereby adding the binary representation of the initial address index of each data and the binary representation of the corresponding cyclic right shift value in each iteration layer to obtain the binary representation of the target address index of each data in each iteration layer; In the binary representation of the target address index of each data in each layer iteration, the lower two binary values ​​are used as the target chip select address, and the remaining high binary representation is used as the target chip address; Based on the target chip select address and target on-chip address of each data in each layer iteration, each data is stored in the corresponding single-port read-write memory, so that four to-be-processed data are read in parallel from the four single-port read-write memories according to the fast Fourier transform rule to perform fast Fourier transform.

[0008] Preferably, after performing the fast Fourier transform, the method further includes: storing the processing results after the fast Fourier transform in parallel in a single-port read-write memory where four data to be processed are located.

[0009] Preferably, each data is stored in a corresponding single-port read-write memory based on the target chip select address and the target on-chip address of each data in the m-th layer iteration, thereby reading the data to be processed from the four single-port read-write memories in parallel according to the fast Fourier transform rule to perform the m-th layer fast Fourier transform, and storing the processing results after the fast Fourier transform in parallel in the four single-port read-write memories where the data to be processed are located further includes: Read each data from the single-port read / write memory, calculate the binary representation of the target address index of each data in the m+1th iteration based on the initial address index of each data and the difference between the intra-chip data index in the m+1th iteration, and obtain the target chip select address and target intra-chip address of each data in the m+1th iteration; Each data is stored again in a corresponding single-port read-write memory to perform an m+1th layer fast Fourier transform; m≥1, m+1≤M, where M represents the number of iteration layers of the radix-4 FFT.

[0010] Preferably, the four single-port read-write memories are sorted using binary representation to obtain the sequence number of each single-port read-write memory.

[0011] Preferably, in the binary representation of the initial address index of each data, the lower two binary values ​​are the initial chip select address of each data, and the remaining high binary values ​​are the initial on-chip address of each data. The chip select address represents the serial number of the single-port read-write memory, and the on-chip address represents the storage serial number in the single-port read-write memory.

[0012] Preferably, the calculation formula for the number of iteration layers of the radix-4 FFT is: , in, Indicates the number of iteration layers of radix-4 FFT; Represents the number of data in a discrete data sequence; The calculation formula for the number of butterfly operation groups in each layer iteration is: , in, Indicates the number of butterfly operation groups in each layer iteration; Represents the loop variable for each layer iteration, , Indicates the mth layer iteration; The calculation formula for the index difference between butterfly data in each layer iteration is: , in, Represents the index difference between butterfly data in each layer iteration; The calculation formula for the intra-butterfly data index difference in each layer iteration is: , in, Indicates the intra-butterfly data index difference in each layer iteration.

[0013] The present invention further provides a processor, which is used to implement the above-mentioned power line carrier communication data processing method, including: An initial data allocation module is used to allocate and store data in a discrete data sequence to four single-port read-write memories, thereby obtaining a binary representation of the initial address index of each data; wherein the initial address index includes an initial chip select address and an initial on-chip address; A radix-4 FFT parameter calculation module is used to calculate the number of radix-4 FFT iteration layers and the number of butterfly operation groups in each iteration layer based on the number of data in the discrete data sequence, thereby calculating the inter-butterfly data index difference and the intra-butterfly data index difference in each iteration layer; A target address index acquisition module is used to round down the quotient of the initial address index of each data and the difference between the data index within the butterfly in each layer of iteration to obtain the corresponding cyclic right shift value of each data in each layer of iteration, thereby adding the binary representation of the initial address index of each data and the binary representation of the corresponding cyclic right shift value in each layer of iteration to obtain the binary representation of the target address index of each data in each layer of iteration; The target chip select on-chip address acquisition module is used to use the lower two binary values ​​of the target address index of each data in each layer iteration as the target chip select address and the remaining high binary representation as the target on-chip address; The target data allocation and processing module is used to store each data into the corresponding single-port read-write memory based on the target chip select address and target on-chip address of each data in each layer iteration, so as to read four to-be-processed data in parallel from four single-port read-write memories according to the fast Fourier transform rules for fast Fourier transform.

[0014] The present invention also provides a power line carrier communication system communication terminal, comprising the above-mentioned processor.

[0015] The present invention also provides a power line carrier communication system, comprising the above-mentioned power line carrier communication system communication terminal.

[0016] The present invention also provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the above-mentioned power line carrier communication data processing method are implemented.

[0017] The power line carrier communication data processing method provided in this application has the following beneficial effects: The present application first distributes the data in the discrete time domain sequence in the received signal to four single-port read-write memories in a round-robin manner. When the intra-butterfly data index interval of the radix-4 FFT is a multiple of 4, the problem of four data that need to be processed in parallel in one memory arises. Therefore, the present application introduces an address transformation algorithm to adjust the storage address of each data. First, the intra-butterfly data index difference at each layer iteration is calculated based on the parameter calculation formula of the radix-4 FFT, and then the cyclic right shift value is calculated based on the initial address of each data and the intra-butterfly data index difference. By adding the binary representation of the initial address of each data and the binary representation of its corresponding cyclic right shift value, the storage address of the data is dynamically mapped using the cyclic right shift value and the intra-butterfly data index difference at each layer iteration, breaking the periodicity of the polling allocation storage, so that the four parallel to-be-processed data originally stored in the same memory are distributed to different memories, so that the four single-port read-write memories can be accessed in parallel within one clock cycle and the to-be-processed data can be obtained, effectively improving the data parsing speed of the receiving end during power line carrier communication, and thus the frequency components of each subcarrier signal in the received signal can be obtained in time, ensuring the quality and rate of power line carrier communication. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings, wherein: Figure 1 Flowchart of the power line carrier communication data processing method provided in this application; Figure 2 This is a schematic diagram of the processor structure provided by this application. DETAILED DESCRIPTION

[0019] The present invention will be further described below with reference to the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it. However, the embodiments are not intended to limit the present invention.

[0020] See also Figure 1 , Figure 1 The figure shows a flow chart of a power line carrier communication data processing method provided by the present application. The method is applied to a processor of a power line carrier communication system, and specifically includes: S10: polling and distributing the data in the discrete data sequence and storing them in four single-port read-write memories, thereby obtaining a binary representation of the initial address index of each data; wherein the initial address index includes an initial chip select address and an initial on-chip address.

[0021] Specifically, the discrete data sequence can be a discrete time domain data sequence or a discrete frequency domain data sequence. The discrete time domain data sequence is a high-frequency signal transmitted through the power line, which is obtained by the receiving end using the radio frequency to receive the signal and then processing the received signal using the AGC and DFE modules; the discrete frequency domain data sequence is the value of the constellation point mapping of the data to be sent at the transmitting end on each subcarrier.

[0022] S20: Based on the number of data in the discrete data sequence, calculate the number of iteration layers of the radix-4 FFT and the number of butterfly operation groups in each iteration layer, thereby calculating the inter-butterfly data index difference and the intra-butterfly data index difference in each iteration layer.

[0023] Specifically, the radix-4 FFT decomposes the DFT of multiple data into multiple layers of iterative calculations, with each layer of iteration corresponding to a split-and-merge operation, thereby splitting the multiple data to be processed into smaller subsequences. Each iterative layer contains a butterfly operation group consisting of several thousand butterfly units. Each butterfly unit performs a DFT on four data items and outputs the Fourier transformed result. The inter-butterfly data index difference represents the address index interval between the starting data of adjacent butterfly operation groups in the same iterative layer, and the intra-butterfly data index difference represents the address index interval between two data items within each butterfly unit. For example, in the second iterative layer, there are two butterfly operation groups, each containing two butterfly units. The inter-butterfly data index difference represents the address index interval between the first data item of the first butterfly operation group and the second data item of the second butterfly operation group.

[0024] S30: Round down the quotient of the initial address index of each data and the difference between the data indexes within the butterfly in each layer of iteration to obtain the corresponding circular right shift value of each data in each layer of iteration, thereby adding the binary representation of the initial address index of each data and the binary representation of the corresponding circular right shift value in each layer of iteration to obtain the binary representation of the target address index of each data in each layer of iteration.

[0025] S40: In the binary representation of the target address index of each data in each layer iteration, the lower two binary values ​​are used as the target chip select address, and the remaining high binary representation is used as the target chip address.

[0026] S50: storing each data into a corresponding single-port read / write memory based on the target chip select address and target on-chip address of each data in each layer iteration, thereby reading four to-be-processed data in parallel from the four single-port read / write memories according to the fast Fourier transform rule to perform fast Fourier transform.

[0027] In addition, it should be noted that in step S10, it is only necessary to use the data polling allocation method to obtain the initial address index of each data, and there is no need to actually write each data into each single-port read-write memory according to the initial address index. The solution provided by this application only needs to write each data into the corresponding single-port read-write memory according to the target address index of the current iteration in each iteration, read the data after the iteration is completed, recalculate the target address index of each data in the next layer of iteration, and rewrite each data into the corresponding single-port read-write memory.

[0028] Furthermore, after the data transformation, the method further includes storing the processing results after the fast Fourier transform in parallel in the single-port read-write memory where the four to-be-processed data are located.

[0029] First, the data in the discrete time domain sequence in the received signal is allocated to four single-port read-write memories in a round-robin manner. When the intra-butterfly data index interval of the radix-4 FFT is a multiple of 4, the problem of four data that need to be processed in parallel in one memory will arise. Therefore, the present application introduces an address transformation algorithm to adjust the storage address of each data. First, the intra-butterfly data index difference at each layer iteration is calculated based on the parameter calculation formula of the radix-4 FFT, and then the cyclic right shift value is calculated based on the initial address of each data and the intra-butterfly data index difference. By adding the binary representation of the initial address of each data and the binary representation of its corresponding cyclic right shift value, the storage address of the data is dynamically mapped using the cyclic right shift value and the intra-butterfly data index difference at each layer iteration, breaking the periodicity of the polling allocation storage, so that the four parallel to-be-processed data originally stored in the same memory are allocated to different memories, so that the four single-port read-write memories can be accessed in parallel within one clock cycle and the to-be-processed data can be obtained, effectively improving the data parsing speed of the receiving end during power line carrier communication, and thus the frequency components of each subcarrier signal in the received signal can be obtained in time, and the noise frequency band signal can be filtered out to ensure the quality and rate of power line carrier communication.

[0030] Specifically, the four single-port read-write memories are sorted using binary representation to obtain the sequence number of each single-port read-write memory.

[0031] In the binary representation of the initial address index of each data, the lower two binary values ​​are the initial chip select address of each data, and the remaining high binary values ​​are the initial on-chip address of each data. The chip select address represents the serial number of the single-port read-write memory, and the on-chip address represents the storage serial number in the single-port read-write memory.

[0032] Furthermore, each data is stored in a corresponding single-port read-write memory based on the target chip select address and the target on-chip address of each data in the m-th layer iteration, thereby reading the data to be processed from the four single-port read-write memories in parallel according to the fast Fourier transform rule to perform the m-th layer fast Fourier transform, and storing the processing results after the fast Fourier transform in parallel in the four single-port read-write memories where the data to be processed are located, further comprising: Read each data from the single-port read / write memory, calculate the binary representation of the target address index of each data in the m+1th iteration based on the initial address index of each data and the difference between the intra-chip data index in the m+1th iteration, and obtain the target chip select address and target intra-chip address of each data in the m+1th iteration; Each data is stored again in a corresponding single-port read-write memory to perform an m+1th layer fast Fourier transform; m≥1, m+1≤M, where M represents the number of iteration layers of the radix-4 FFT.

[0033] Specifically, the calculation formula for the number of iteration layers of radix-4 FFT is: , in, Indicates the number of iteration layers of radix-4 FFT; Represents the number of data in a discrete data sequence; The calculation formula for the number of butterfly operation groups in each layer iteration is: , in, Indicates the number of butterfly operation groups in each layer iteration; Represents the loop variable for each layer iteration, , Indicates the mth layer iteration; The calculation formula for the index difference between butterfly data in each layer iteration is: , in, Represents the index difference between butterfly data in each layer iteration; The calculation formula for the intra-butterfly data index difference in each layer iteration is: , in, Indicates the intra-butterfly data index difference in each layer iteration.

[0034] The following is a specific example to illustrate the above method. In this example, a radix-4 FFT with N=1024 is used as an example: According to the above FFT parameter calculation formula, it can be calculated that: the number of iteration layers M=5, the number of butterfly operation groups in the first iteration layer is 1, the number of butterfly operation groups in the second iteration layer is 4, the number of butterfly operation groups in the third iteration layer is 16, the number of butterfly operation groups in the fourth iteration layer is 64, and the number of butterfly operation groups in the fourth iteration layer is 256; in the first iteration layer, the inter-butterfly data index difference is 1024, and the intra-butterfly data index difference is 256; in the second iteration layer, the inter-butterfly data index difference is 256, and the intra-butterfly data index difference is 64.

[0035] For example, each row of data in Table 1 is the address index of the four data that each butterfly unit needs to process in parallel in the first layer iteration: Table 1

[0036] The four single-port read-write memories are sorted using binary representation to obtain the sequence number of each single-port read-write memory. Specifically, the binary representation of the first single-port read-write memory is 00, the binary representation of the second single-port read-write memory is 01, the binary representation of the third single-port read-write memory is 10, and the binary representation of the fourth single-port read-write memory is 11.

[0037] 1024 data polling is distributed and stored in four single-port read-write memories, thereby obtaining a binary representation of the initial address index of each data; wherein the initial address index includes the initial chip select address and the initial on-chip address; for example, the initial address index value of the first data in the first single-port read-write memory 00 is 0, and its binary representation is 0000000000, and the initial address index value of the first data in the second single-port read-write memory 01 is 1, and its binary representation is 0000000001.

[0038] Table 2 shows the initial address index values ​​of each data in the four single-port read-write memories in the first layer iteration: Table 2

[0039] Comparing Table 1 and Table 2, it can be seen that the data with initial address index values ​​of 0, 256, 512, and 768 need to be processed in parallel. However, after being directly stored in a round-robin manner, these data are all located in the first single-port read-write memory 00. Therefore, when acquiring data according to the fast Fourier transform rule, it is still necessary to acquire these four to-be-processed data separately within multiple clock cycles, which does not effectively improve the timeliness of data processing.

[0040] The storage location of each data is adjusted as follows according to the method provided in this application: Calculate the quotient of the initial address index value of each data divided by the index difference of the butterfly data in the current iteration layer, round down the obtained quotient to obtain the cyclic right shift value of the data, and add the binary representation of the initial address index of each data and the binary representation of its corresponding cyclic right shift value to obtain the adjusted target address index binary representation, and use the lower two binary bits in the target address index binary representation as the chip select address of the data, that is, the binary representation of the single-port read-write memory where the data needs to be stored, and use the remaining upper eight binary bits as the storage location of the data in the single-port read-write memory.

[0041] The pseudo code for storage address adjustment is as follows: function [9:0] addr_map(input [9:0]addr_in, input [9:0] p_interval); reg [1:0] rsht; % Circular right shift value reg [1:0] addr_bank; %mem chip select address rsht = addr_in / p_interval; addr_bank = addr_in[1:0] + rsht; addr_map = {addr_in,addr_bank}; endfunction Taking the data with an initial address index value of 0 as an example, its circular right shift value = 0 / 256 = 0, and the binary representation of its initial address index value is 0000000000, and the binary representation of the target address index value is still 0000000000, that is, the address of the data is not adjusted; taking the data with an initial address index value of 256 as an example, its circular right shift value = 256 / 256 = 1, and the binary representation of its initial address index value is 01000000000, and the binary representation of the target address index value is 0100000000+01=0100000001, and the adjusted target chip select address is 01, and the target on-chip address is 01000000, that is, the adjusted storage address of the data is the 01000000 bit in the second single-port read-write memory 01.

[0042] Table 3 shows the storage locations of the data at each initial address index value in the first layer iteration after adjustment using the method provided by this application: Table 3

[0043] As can be seen from Table 3, the data with initial address index values ​​of 0, 256, 512 and 768 that need to be processed in parallel are stored in different single-port read-write memories after being processed by the method provided by this application, so that these data can be obtained simultaneously within one clock cycle, effectively improving the timeliness of data processing.

[0044] For example, each row of data in Table 4 is the address index of the four data that each butterfly unit in each butterfly operation group needs to process in parallel in the second layer iteration: Table 4

[0045] Table 5 shows the initial address index values ​​of each data in the four single-port read-write memories in the second-level iteration: Table 5

[0046] The storage address of each data is adjusted in the same way. It should be noted that the index difference of the intra-butterfly data in the second iteration is 64. Considering that the storage address of each data has changed after the first iteration, each subsequent iteration needs to calculate its corresponding circular right shift value based on the initial address index value of each data. Therefore, after each iteration, the storage location of all data needs to be reset to the initial address index value, and then the corresponding circular right shift value in the current iteration is calculated based on its initial address index value and the index difference of the intra-butterfly data in the current iteration.

[0047] Table 6 shows the storage locations of the data at each initial address index value in the second-level iteration after adjustment using the method provided by this application: Table 6

[0048] It can be seen from the data in Tables 4 to 6 that the data with initial address index values ​​of 0, 64, 128 and 192 that need to be processed in parallel are still located in the same single-port read-write memory if they are directly stored using polling allocation. After adjusting the storage position using the method provided in this application, these data are located in four single-port read-write memories respectively, so that they can be acquired and processed within one clock cycle.

[0049] Based on the power line carrier communication data processing method provided in the above embodiment, the embodiment of the present application further provides a processor, which is used to implement the above power line carrier communication data processing method, such as Figure 2 As shown, the processor specifically includes: The initial data allocation module 10 is used to allocate and store the data in the discrete data sequence into four single-port read-write memories, thereby obtaining a binary representation of the initial address index of each data; wherein the initial address index includes the initial chip select address and the initial on-chip address.

[0050] The radix-4 FFT parameter calculation module 20 is used to calculate the number of radix-4 FFT iteration layers and the number of butterfly operation groups in each iteration layer based on the number of data in the discrete data sequence, thereby calculating the inter-butterfly data index difference and the intra-butterfly data index difference in each iteration layer.

[0051] The target address index acquisition module 30 is used to round down the quotient of the initial address index of each data and the difference between the data index within the butterfly in each layer of iteration to obtain the corresponding circular right shift value of each data in each layer of iteration, thereby adding the binary representation of the initial address index of each data and the binary representation of the corresponding circular right shift value in each layer of iteration to obtain the binary representation of the target address index of each data in each layer of iteration.

[0052] The target chip select intra-chip address acquisition module 40 is used to use the lower two binary values ​​of the target address index of each data in each layer iteration as the target chip select address and the remaining high binary representation as the target intra-chip address.

[0053] The target data allocation and processing module 50 is used to store each data into the corresponding single-port read-write memory based on the target chip select address and target on-chip address of each data in each layer iteration, thereby reading four to-be-processed data in parallel from four single-port read-write memories according to the fast Fourier transform rules to perform fast Fourier transform.

[0054] An embodiment of the present application further provides a power line carrier communication system communication terminal, which includes the above-mentioned processor.

[0055] An embodiment of the present application further provides a power line carrier communication system, which includes the above-mentioned power line carrier communication system communication terminal.

[0056] An embodiment of the present application further provides a computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the steps of the above-mentioned power line carrier communication data processing method are implemented.

[0057] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware. Furthermore, the present application may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0058] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0059] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0060] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 The steps for the function specified in one or more boxes.

[0061] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.

Claims

1. A power line carrier communication data processing method, characterized in that: Processors for power line carrier communication systems include: The data in the discrete data sequence are polled and distributed and stored in four single-port read-write memories, thereby obtaining a binary representation of the initial address index of each data; wherein the initial address index includes an initial chip select address and an initial on-chip address; Based on the number of data in the discrete data sequence, the number of radix-4 FFT iteration layers and the number of butterfly operation groups in each iteration layer are calculated, thereby calculating the inter-butterfly data index difference and the intra-butterfly data index difference in each iteration layer; The quotient of the initial address index of each data and the difference between the data indexes in each iteration layer is rounded down to the nearest integer to obtain the corresponding cyclic right shift value of each data in each iteration layer, thereby adding the binary representation of the initial address index of each data and the binary representation of the corresponding cyclic right shift value in each iteration layer to obtain the binary representation of the target address index of each data in each iteration layer; In the binary representation of the target address index of each data in each layer iteration, the lower two binary values ​​are used as the target chip select address, and the remaining high binary representation is used as the target chip address; Based on the target chip select address and target on-chip address of each data in each layer iteration, each data is stored in the corresponding single-port read-write memory, so that four to-be-processed data are read in parallel from the four single-port read-write memories according to the fast Fourier transform rule to perform fast Fourier transform.

2. The power line carrier communication data processing method according to claim 1, characterized in that: After the fast Fourier transform is performed, the method further includes: storing the processing results after the fast Fourier transform in parallel in the single-port read-write memory where the four to-be-processed data are located.

3. The power line carrier communication data processing method according to claim 2, characterized in that: Based on the target chip select address and the target on-chip address of each data in the m-th layer iteration, each data is stored in the corresponding single-port read-write memory, thereby reading the data to be processed from the four single-port read-write memories in parallel according to the fast Fourier transform rule to perform the m-th layer fast Fourier transform, and storing the processing results after the fast Fourier transform in parallel in the four single-port read-write memories where the data to be processed are located, further comprising: Read each data from the single-port read / write memory, calculate the binary representation of the target address index of each data in the m+1th iteration based on the initial address index of each data and the difference between the intra-chip data index in the m+1th iteration, and obtain the target chip select address and target intra-chip address of each data in the m+1th iteration; Each data is stored again in a corresponding single-port read-write memory to perform an m+1th layer fast Fourier transform; m≥1, m+1≤M, where M represents the number of iteration layers of the radix-4 FFT.

4. The power line carrier communication data processing method according to claim 1, characterized in that: The four single-port read-write memories are sorted using binary representation to obtain a sequence number of each single-port read-write memory.

5. The power line carrier communication data processing method according to claim 4, characterized in that: In the binary representation of the initial address index of each data, the lower two binary values ​​are the initial chip select address of each data, and the remaining high binary values ​​are the initial on-chip address of each data. The chip select address represents the serial number of the single-port read-write memory, and the on-chip address represents the storage serial number in the single-port read-write memory.

6. The power line carrier communication data processing method according to claim 1, characterized in that: The formula for calculating the number of iteration layers of radix-4 FFT is: ， in, Indicates the number of iteration layers of radix-4 FFT; Represents the number of data in a discrete data sequence; The calculation formula for the number of butterfly operation groups in each layer iteration is: ， in, Indicates the number of butterfly operation groups in each layer iteration; Represents the loop variable for each layer iteration, , Indicates the mth layer iteration; The calculation formula for the index difference between butterfly data in each layer iteration is: ， in, Represents the index difference between butterfly data in each layer iteration; The calculation formula for the intra-butterfly data index difference in each layer iteration is: ， in, Indicates the intra-butterfly data index difference in each layer iteration.

7. A processor, characterized in that: The processor is used to implement the power line carrier communication data processing method according to any one of claims 1 to 6, comprising: An initial data allocation module is used to allocate and store data in a discrete data sequence to four single-port read-write memories, thereby obtaining a binary representation of the initial address index of each data; wherein the initial address index includes an initial chip select address and an initial on-chip address; A radix-4 FFT parameter calculation module is used to calculate the number of radix-4 FFT iteration layers and the number of butterfly operation groups in each iteration layer based on the number of data in the discrete data sequence, thereby calculating the inter-butterfly data index difference and the intra-butterfly data index difference in each iteration layer; A target address index acquisition module is used to round down the quotient of the initial address index of each data and the difference between the data index within the butterfly in each layer of iteration to obtain the corresponding cyclic right shift value of each data in each layer of iteration, thereby adding the binary representation of the initial address index of each data and the binary representation of the corresponding cyclic right shift value in each layer of iteration to obtain the binary representation of the target address index of each data in each layer of iteration; The target chip select on-chip address acquisition module is used to use the lower two binary values ​​of the target address index of each data in each layer iteration as the target chip select address and the remaining high binary representation as the target on-chip address; The target data allocation and processing module is used to store each data into the corresponding single-port read-write memory based on the target chip select address and target on-chip address of each data in each layer iteration, so as to read four to-be-processed data in parallel from four single-port read-write memories according to the fast Fourier transform rules for fast Fourier transform.

8. A communication terminal of a power line carrier communication system, characterized in that: comprising the processor of claim 7.

9. A power line carrier communication system, characterized in that: Including the power line carrier communication system communication terminal as described in claim 8.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the power line carrier communication data processing method according to any one of claims 1 to 6 are implemented.

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