Mobile industry processor interface (MIPI) repeater signal switching method and apparatus

Abstract

This application discloses a signal switching method and apparatus for a Mobile Industry Processor Interface (MIPI) repeater, relating to the field of mobile industry processor interface technology. This method actively triggers repeater initialization. After initialization, the MIPI input signal is then connected, ensuring strict synchronization between the repeater's output LP-HS switching and the input signal. Through register initialization configuration, the repeater can pre-know the relevant parameters and requirements for signal transmission, enabling a rapid response upon signal arrival. Synchronizing the output LP-HS switching with the input signal based on pre-configured parameters ensures no timing deviations or distortions occur during signal transmission. This achieves fast and accurate transmission of MIPI input signals, improving signal transmission quality. Consequently, it effectively avoids signal delay and packet loss, enhancing the overall system performance and stability.

Description

Technical Field

[0001] This application relates to the field of mobile industry processor interface technology, and in particular to a method and apparatus for switching signals of a mobile industry processor interface (MIPI) repeater. Background Technology

[0002] The Mobile Industry Processor Interface (MIPI) is a widely used high-speed serial interface standard in mobile devices, providing an efficient data transmission channel between the processor and components such as displays and cameras, significantly promoting the performance improvement and functional diversification of mobile devices. The MIPI protocol divides signal transmission modes into a low-power (LP) mode and a high-speed (HS) mode. Due to the characteristics of the MIPI protocol, the LP-HS switching of the continuous clock signal only occurs in the initial stage during MIPI signal transmission; subsequent signals will maintain the HS high-speed mode. However, this switching process is crucial, as it provides a clear signal start reference for backend devices, allowing them to accurately locate the starting position of data and thus systematically parse the subsequently transmitted data. Simultaneously, it is also a key basis for protocol synchronization by backend devices, helping them adjust their parameters to achieve consistency with the transmitter and ensuring stable signal transmission in the subsequent HS high-speed mode.

[0003] However, in complex MIPI signal transmission environments, while traditional repeaters can enhance signals and extend transmission distances, they also present significant problems. Their signal relay function activates upon detecting an input signal, but internal circuit initialization (such as clock synchronization and level calibration) requires time. This can cause the output signal to miss the initial LP-HS switching process. Because backend devices lack this crucial information, signal integrity is compromised, making it impossible to accurately resolve signal start boundaries. This can lead to system reliability issues such as display abnormalities, data frame loss, and device wake-up failures. Summary of the Invention

[0004] To address the above problems, this application provides a method for switching signals in a Mobile Industry Processor Interface (MIPI) repeater, comprising the following:

[0005] In a first aspect, this application provides a method for switching signals in a Mobile Industry Processor Interface (MIPI) repeater, the method comprising:

[0006] Before the repeater receives the MIPI input signal, the register of the repeater is initialized and configured.

[0007] After the initialization configuration is completed, in response to the MIPI input signal, the LP-HS switching at the repeater output is synchronized with the input signal based on the pre-configured parameters.

[0008] Optionally, the initialization configuration of the repeater's registers includes:

[0009] Configure the digital and analog layer parameters of the receiver RX, and configure the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, and set RX and TX to bypass mode;

[0010] The configuration of the PLL of the transmitter TX includes: configuring preloaded PLL parameters according to a preset MIPI clock, so that the repeater locks the target frequency in advance when there is no input signal.

[0011] Optionally, configuring the digital and analog layer parameters of the receiver (RX) and the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter (TX) includes:

[0012] Configure the number of lanes, line sequence mapping, equalizer (EQ) parameters, and clock hardware mode for the RX.

[0013] Configure the digital and analog parameters related to TX signal transmission, as well as the PLL prescaler coefficient, serial output divider settings, charge pump current, and loop filter parameters.

[0014] Optionally, the step of configuring preloaded PLL parameters according to a preset MIPI clock to enable the repeater to lock onto the target frequency in advance when there is no input signal includes:

[0015] Calculate the MIPI byte clock based on the preset MIPI clock configuration;

[0016] The prescaler factor N is determined based on the MIPI byte clock, and the serial output divider level M is determined based on the range of the MIPI physical layer serial clock; the MIPI physical layer serial clock frequency is 4 times the MIPI byte clock frequency.

[0017] Calculate the final frequency division factor and preload it into the PLL, start the TX PLL and lock the target frequency. The final frequency division factor is 4 times N multiplied by M.

[0018] Optionally, synchronizing the LP-HS switching at the repeater output with the input signal based on pre-configured parameters includes:

[0019] After the MIPI input signal is received, the preset MIPI clock configuration signal is transmitted to the TX PLL via the RX.

[0020] The TX PLL generates a stable clock configuration signal output based on pre-configured parameters, fully preserving the switching process of the continuous clock LP-HS, and ensuring that the output is synchronized with the input signal.

[0021] Secondly, this application provides a mobile industry processor interface (MIPI) repeater signal switching device, the device comprising:

[0022] A configuration unit is used to initialize and configure the registers of the repeater before the repeater receives the MIPI input signal;

[0023] The synchronization unit is used to synchronize the LP-HS switching at the repeater output with the input signal in response to the MIPI input signal after the initialization configuration is completed, based on the pre-configured parameters.

[0024] Optionally, the configuration unit is specifically used for:

[0025] Configure the digital and analog layer parameters of the receiver RX, and configure the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, and set RX and TX to bypass mode;

[0026] The configuration of the PLL of the transmitter TX includes: configuring preloaded PLL parameters according to a preset MIPI clock, so that the repeater locks the target frequency in advance when there is no input signal.

[0027] Optionally, the configuration unit configures the digital and analog layer parameters of the receiver (RX) and the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter (TX), including:

[0028] Configure the number of lanes, line sequence mapping, equalizer (EQ) parameters, and clock hardware mode for the RX.

[0029] Configure the digital and analog parameters related to TX signal transmission, as well as the PLL prescaler coefficient, serial output divider settings, charge pump current, and loop filter parameters.

[0030] Optionally, the configuration unit configures preloaded PLL parameters according to a preset MIPI clock, enabling the repeater to lock onto the target frequency in advance when there is no input signal, including:

[0031] Calculate the MIPI byte clock based on the preset MIPI clock configuration;

[0032] The prescaler factor N is determined based on the MIPI byte clock, and the serial output divider level M is determined based on the range of the MIPI physical layer serial clock; the MIPI physical layer serial clock frequency is 4 times the MIPI byte clock frequency.

[0033] Calculate the final frequency division factor and preload it into the PLL, start the TX PLL and lock the target frequency. The final frequency division factor is 4 times N multiplied by M.

[0034] Optionally, the synchronization unit synchronizes the LP-HS switching at the repeater output with the input signal based on pre-configured parameters, including:

[0035] After the MIPI input signal is received, the preset MIPI clock configuration signal is transmitted to the TX PLL via the RX.

[0036] The TX PLL generates a stable clock configuration signal output based on pre-configured parameters, fully preserving the switching process of the continuous clock LP-HS, and ensuring that the output is synchronized with the input signal.

[0037] Thirdly, this application provides an apparatus comprising a memory and a processor, the memory for storing instructions or code, and the processor for executing the instructions or code to cause the apparatus to perform the Mobile Industry Processor Interface (MIPI) repeater signal switching method described in any implementation of the first aspect.

[0038] Fourthly, this application provides a computer-readable storage medium storing code, wherein when the code is executed, a device running the code implements the Mobile Industry Processor Interface (MIPI) repeater signal switching method described in any of the implementations of the first aspect.

[0039] This application provides a signal switching method for a MIPI repeater in the mobile industry processor interface. When executing the method, before the repeater receives a MIPI input signal, the repeater's registers are initialized. After initialization, in response to the MIPI input signal, the LP-HS switching at the repeater's output is synchronized with the input signal based on pre-configured parameters. Thus, once a MIPI input signal is received, the repeater immediately starts working, ensuring the output signal completely follows the input and maintains signal integrity. The register initialization allows the repeater to know the relevant parameters and requirements for signal transmission in advance, enabling a rapid response when the signal arrives. Synchronizing the LP-HS switching at the output with the input signal based on pre-configured parameters ensures that timing deviations or distortions do not occur during signal transmission. This achieves fast and accurate MIPI signal transmission, improving signal transmission quality. Consequently, signal delay and packet loss problems can be effectively avoided, improving the performance and stability of the entire system. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in this embodiment or the prior art, the drawings used in the description of the embodiment or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A flowchart illustrating a method for switching signals in a Mobile Industry Processor Interface (MIPI) repeater, as provided in this application embodiment;

[0042] Figure 2A schematic diagram illustrating a zero-loss pre-synchronization process for LP-HS switching of a MIPI repeater, provided in an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of a signal switching device for a Mobile Industry Processor Interface (MIPI) repeater, provided as an embodiment of this application. Detailed Implementation

[0044] As described in the background section of this application, in the application of traditional MIPI repeaters, their signal relay function is typically activated after a MIPI input signal is detected. Due to the characteristics of the MIPI protocol, the LP-HS switching of the continuous clock signal only occurs in the initial stage of signal transmission, and subsequent signals will maintain the HS high-speed mode. When the repeater is activated, its internal circuitry requires a certain delay to complete initialization (such as clock synchronization, level calibration, etc.). This delay causes the repeater output signal to lose the initial LP-HS switching process, which is a key indicator for some back-end devices to identify the start of the signal and protocol synchronization.

[0045] Therefore, the existing technology has the following problems: (1) Signal integrity is damaged: loss of LP-HS switching causes the back-end equipment to be unable to correctly resolve the signal start boundary; (2) System reliability is reduced: it may cause display abnormalities, data frame loss or equipment failure to wake up.

[0046] To address the aforementioned technical problems, this application provides a method for switching signals in a Mobile Industry Processor Interface (MIPI) repeater. When executing this method, before the repeater receives a MIPI input signal, the repeater's registers are initialized. After initialization, in response to the MIPI input signal, the LP-HS switching at the repeater's output is synchronized with the input signal based on pre-configured parameters. Thus, once a MIPI input signal is received, the repeater immediately begins operation, ensuring the output signal completely follows the input and maintains signal integrity. The register initialization allows the repeater to anticipate relevant signal transmission parameters and requirements, enabling a rapid response upon signal arrival. Synchronizing the LP-HS switching at the output with the input signal based on pre-configured parameters ensures no timing deviations or distortions occur during signal transmission. This achieves fast and accurate MIPI signal transmission, improving signal transmission quality. Consequently, signal delay and packet loss are effectively avoided, enhancing the overall system performance and stability, making it particularly suitable for mobile device applications with high real-time and reliability requirements for signal transmission.

[0047] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0048] Figure 1 This is a flowchart illustrating a signal switching method for a MIPI (Mobile Industry Processor Interface) repeater, provided as an embodiment of this application. (Combined with...) Figure 1 As shown in the embodiments of this application, the MIPI repeater signal switching method provided may include:

[0049] S101. Before the repeater receives the MIPI input signal, the register of the repeater is initialized and configured.

[0050] The Mobile Industry Processor Interface (MIPI) is a high-speed serial interface standard designed for mobile devices such as smartphones and automotive systems. It enables high-bandwidth, low-power data transmission between modules such as cameras and displays and the processor through a unified physical layer protocol, such as D-PHY / C-PHY. Repeaters are key hardware components in the MIPI interface ecosystem, used to extend the transmission distance of MIPI signals or enable cascading of multiple devices. They address attenuation and timing deviation issues in high-speed transmission by regenerating and synchronizing signals, ensuring that the low-latency, high-bandwidth characteristics specified by the MIPI protocol are not affected.

[0051] Before a repeater receives MIPI input signals, its internal registers must be fully initialized and configured, specifically including hierarchical settings for the receiver (RX), transmitter (TX), and phase-locked loop (PLL) parameters. TX, or Transmitter, is the high-speed signal transmitter, typically initiating communication. It converts processed data into the high-speed signal format specified by the MIPI protocol, achieving reliable long-distance transmission through pre-emphasis and drive strength adjustment. RX, or Receiver, is responsible for receiving MIPI high-speed signals, performing clock recovery, equalization compensation, and protocol parsing on the input data to ensure signal integrity and data accuracy. PLL, or Phase-Locked Loop, provides a precise clock source for TX, ensuring strict synchronization between the output and input signals through frequency synthesis and phase locking, eliminating transmission delay.

[0052] The configuration process for RX parameters includes configuring both digital layer parameters and analog layer parameters. The digital layer parameter configuration includes configuring the number of RX lanes, line sequence mapping, and clock hardware mode.

[0053] The configuration of analog layer parameters includes setting equalizer (EQ) parameters, including pre-emphasis intensity and receiver compensation coefficient, to compensate for high-frequency attenuation of the signal in the transmission medium.

[0054] The parameter configuration for TX includes both digital layer parameter configuration and analog layer parameter configuration. Digital layer parameter configuration includes configuring the data format and encoding method related to signal transmission. Analog layer parameter configuration includes setting the drive strength to match different load impedances, and configuring pre-emphasis parameters to enhance high-frequency signal energy.

[0055] Configuring the PLL of the transmitter (TX) includes selecting the MIPI byte clock as the reference clock of the TX PLL through an internal register, and pre-calculating and preloading the pre-divider coefficient (N-divider), serial output divider level (M-divider), charge pump current, and loop filter parameters of the TX PLL, thereby achieving PLL operating point pre-configuration.

[0056] Specifically, firstly, the MIPI byte clock is calculated based on the preset MIPI clock configuration. Then, the pre-division factor N is determined according to the range of the MIPI byte clock. The determination method of the pre-division factor N is shown in Table 1, which is a pre-division factor (N-divider) mapping table provided in this application embodiment. Then, the serial output divider level M is determined according to the range of the MIPI physical layer serial clock MipiTXPhyClk. The MIPI physical layer serial clock frequency is 4 times the MIPI byte clock frequency. The determination of the serial output divider level is shown in Table 2, which is a serial output divider level (M-divider) mapping table provided in this application embodiment. After obtaining N and M, the final division factor is further calculated and preloaded into the PLL. The TX PLL is started and the target frequency is locked. The final division factor is 4 times N multiplied by M, i.e., DivSet = 4 × N × M.

[0057] Table 1. Mapping table of predivision coefficients (N-divider):

[0058]

[0059] Table 2. Serial Output Divider Range Mapping Table:

[0060]

[0061] After completing the parameter configuration, set RX and TX to Bypass Mode. In this mode, the repeater only performs physical layer forwarding of signals and does not perform data parsing or protocol processing, thereby further shortening the signal path delay.

[0062] S102. After completing the initialization configuration, in response to the MIPI input signal, the LP-HS switching at the repeater output is synchronized with the input signal based on the pre-configured parameters.

[0063] LP-HS switching refers to the transition between Low Power (LP) and High Speed ​​(HS) modes defined in the MIPI protocol, used to balance power consumption and data rate requirements. In this application, because the parameters of the receiver (RX) and transmitter (TX) are pre-configured, including the N-divider of the TX PLL and the M-divider of the serial output divider, these parameters have been optimized according to the actual clock frequency. Therefore, the repeater can respond quickly after a MIPI input signal is received.

[0064] The specific process is as follows: The preset MIPI clock configuration signal is transmitted to the TX PLL via the RX; the TX PLL generates a stable clock configuration signal output based on the pre-configured parameters. In this way, the stability of the continuous clock during the LP-HS switching process is fully preserved, ensuring that the signal at the repeater output is strictly synchronized with the input signal.

[0065] With this design, the repeater can quickly enter the working state when a signal arrives, and the output signal completely follows the input signal, maintaining the integrity and stability of the signal, thereby effectively improving the quality and reliability of signal transmission.

[0066] The above embodiments provide a detailed description of a MIPI (Mobile Industry Processor Interface) repeater signal switching method according to this application. To enable those skilled in the art to more clearly understand the implementation process of this method, the following description, in conjunction with... Figure 2 This application provides a complete description of the LP-HS retention switching method in the MIPI repeater signal switching method for the mobile industry processor interface, such as... Figure 2 As shown, Figure 2 This is a schematic diagram of a zero-loss pre-synchronization process for LP-HS handover of a MIPI repeater provided in an embodiment of this application. The following is based on... Figure 2 The schematic diagram of the LP-HS handover zero-loss pre-synchronization process of the MIPI repeater shown in this application provides a complete description of the MIPI repeater signal handover method for the mobile industry processor interface in this application:

[0067] S201. System powered on.

[0068] When the system starts up, it first performs a power-on operation to provide a foundation for subsequent signal processing and configuration.

[0069] S202. Parameter pre-configuration.

[0070] After the system powers on, a parameter pre-configuration phase is performed. This phase includes configuring the receiver (RX) parameters, transmitter (TX) parameters, and the TX PLL reference frequency divider. This parameter pre-configuration ensures that the repeater can be optimally set according to the actual clock frequency and signal requirements.

[0071] S203. Bypass activation mode enters low power standby state.

[0072] After parameter pre-configuration is complete, the repeater enters bypass activation mode and then enters a low-power standby state. In this state, the repeater consumes less power while maintaining sensitivity to input signals so that it can respond quickly when a signal arrives.

[0073] S204. Input MIPI signal.

[0074] When a MIPI input signal is input to the repeater, the repeater begins to respond to the input signal. This step is the trigger point for the signal switching process.

[0075] S205. Pre-configured PLL for fast phase locking.

[0076] Upon receiving the MIPI input signal, the repeater uses pre-configured parameters to enable the TX PLL to quickly lock onto the phase. This step ensures that the repeater can rapidly generate a clock signal synchronized with the input signal, thereby achieving synchronization of the LP-HS switching.

[0077] S206. Output the complete LP-HS switching waveform.

[0078] The repeater outputs an LP-HS switching waveform synchronized with the input signal. This step ensures the integrity and stability of the signal during transmission, avoiding signal loss or distortion that may occur during LP-HS switching.

[0079] Through the above steps, the MIPI repeater signal switching method provided in this application can achieve fast response and low power consumption while ensuring signal integrity, and is suitable for application scenarios such as mobile devices that have high requirements for real-time and reliability of signal transmission.

[0080] The above are some specific implementations of a MIPI (Mobile Industry Processor Interface) repeater signal switching method provided in this application. Based on this, this application also provides a corresponding device. The device provided in this application will be described below from the perspective of functional modularity.

[0081] Figure 3 This is a schematic diagram of a signal switching device for a Mobile Industry Processor Interface (MIPI) repeater, provided as an embodiment of this application. (Combined with...) Figure 3 As shown in the embodiment of this application, the Mobile Industry Processor Interface (MIPI) repeater signal switching device 300 includes:

[0082] Configuration unit 310 is used to initialize and configure the registers of the repeater before the repeater receives the MIPI input signal;

[0083] Synchronization unit 320 is used to, after completing the initialization configuration, respond to the MIPI input signal and synchronize the LP-HS switching at the repeater output with the input signal based on the pre-configured parameters.

[0084] In one implementation of this application embodiment, the configuration unit is specifically used for:

[0085] Configure the digital and analog layer parameters of the receiver RX, and configure the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, and set RX and TX to bypass mode;

[0086] The configuration of the PLL of the transmitter TX includes: configuring preloaded PLL parameters according to a preset MIPI clock, so that the repeater locks the target frequency in advance when there is no input signal.

[0087] In one implementation of this application, the configuration unit configures the digital and analog layer parameters of the receiver RX, and configures the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, including:

[0088] Configure the number of lanes, line sequence mapping, equalizer (EQ) parameters, and clock hardware mode for the RX.

[0089] Configure the digital and analog parameters related to TX signal transmission, as well as the PLL prescaler coefficient, serial output divider settings, charge pump current, and loop filter parameters.

[0090] In one implementation of this application, the configuration unit configures preloaded PLL parameters according to a preset MIPI clock, enabling the repeater to lock onto the target frequency in advance when there is no input signal, including:

[0091] Calculate the MIPI byte clock based on the preset MIPI clock configuration;

[0092] The prescaler factor N is determined based on the MIPI byte clock, and the serial output divider level M is determined based on the range of the MIPI physical layer serial clock; the MIPI physical layer serial clock frequency is 4 times the MIPI byte clock frequency.

[0093] Calculate the final frequency division factor and preload it into the PLL, start the TX PLL and lock the target frequency. The final frequency division factor is 4 times N multiplied by M.

[0094] In one implementation of this application, the synchronization unit synchronizes the LP-HS switching at the repeater output with the input signal based on pre-configured parameters, including:

[0095] After the MIPI input signal is received, the preset MIPI clock configuration signal is transmitted to the TX PLL via the RX.

[0096] The TX PLL generates a stable clock configuration signal output based on pre-configured parameters, fully preserving the switching process of the continuous clock LP-HS, and ensuring that the output is synchronized with the input signal.

[0097] This application also provides corresponding devices and computer storage media for implementing the solutions provided in this application.

[0098] The device includes a memory and a processor. The memory stores instructions or code, and the processor executes the instructions or code to cause the device to perform the method described in any embodiment of this application.

[0099] The computer storage medium stores code, and when the code is run, the device running the code implements the method described in any embodiment of this application.

[0100] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that all or part of the steps in the methods of the above embodiments can be implemented by means of software plus a general-purpose hardware platform. Based on this understanding, the technical solution of this application can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as a read-only memory (ROM) / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network communication device such as a router) to execute the methods described in various embodiments or some parts of the embodiments of this application.

[0101] It is understood that in the specific embodiments of this application, the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved need to obtain user permission or consent when the above embodiments of this application are applied to specific products or technologies, and the collection, use and processing of related data need to comply with the relevant laws, regulations and standards of relevant countries and regions.

[0102] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0103] It should also be noted that the various embodiments in this specification are described in a progressive manner, and the same or similar parts between the various embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, for the device and apparatus embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method embodiments. The device and apparatus embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components indicated as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of the solution in this embodiment according to actual needs. Those skilled in the art can understand and implement this without creative effort.

[0104] The above description is merely one specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for switching signals in a Mobile Industry Processor Interface (MIPI) repeater, characterized in that, The method includes: Before the repeater receives the MIPI input signal, the register of the repeater is initialized and configured. After the initialization configuration is completed, in response to the MIPI input signal, the LP-HS switching at the repeater output is synchronized with the input signal based on the pre-configured parameters; The initialization configuration of the repeater's registers includes: Configure the digital and analog layer parameters of the receiver RX, and configure the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, and set RX and TX to bypass mode; The configuration of the phase-locked loop (PLL) of the transmitter TX includes: configuring preloaded PLL parameters according to a preset MIPI clock, so that the repeater locks the target frequency in advance when there is no input signal; The step of configuring preloaded PLL parameters according to a preset MIPI clock, enabling the repeater to lock onto the target frequency in advance when there is no input signal, includes: Calculate the MIPI byte clock based on the preset MIPI clock configuration; The prescaler factor N is determined based on the MIPI byte clock, and the serial output divider level M is determined based on the range of the MIPI physical layer serial clock; the MIPI physical layer serial clock frequency is 4 times the MIPI byte clock frequency. Calculate the final frequency division factor and preload it into the PLL, start the TX PLL and lock the target frequency. The final frequency division factor is 4 times N multiplied by M.

2. The method according to claim 1, characterized in that, The configuration of the digital and analog layer parameters of the receiver RX, and the configuration of the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX include: Configure the number of lanes, line sequence mapping, equalizer (EQ) parameters, and clock hardware mode for the RX. Configure the digital and analog parameters related to TX signal transmission, as well as the PLL prescaler coefficient, serial output divider settings, charge pump current, and loop filter parameters.

3. The method according to claim 1, characterized in that, The method of synchronizing the LP-HS switching at the repeater output with the input signal based on pre-configured parameters includes: After the MIPI input signal is received, the preset MIPI clock configuration signal is transmitted to the TX PLL via the RX. The TX PLL generates a stable clock configuration signal output based on pre-configured parameters, fully preserving the switching process of the continuous clock LP-HS, ensuring that the output is synchronized with the input signal.

4. A signal switching device for a Mobile Industry Processor Interface (MIPI) repeater, characterized in that, The device includes: A configuration unit is used to initialize and configure the registers of the repeater before the repeater receives the MIPI input signal; The synchronization unit is used to synchronize the LP-HS switching at the repeater output with the input signal in response to the incoming MIPI input signal after the initialization configuration is completed, based on the pre-configured parameters. The configuration unit is specifically used to: configure the digital layer and analog layer parameters of the receiver RX, configure the digital layer and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, and set RX and TX to bypass mode; The configuration of the PLL of the transmitter TX includes: configuring preloaded PLL parameters according to a preset MIPI clock, so that the repeater locks the target frequency in advance when there is no input signal; The configuration unit configures preloaded PLL parameters according to a preset MIPI clock, enabling the repeater to lock onto the target frequency in advance when there is no input signal, including: Calculate the MIPI byte clock based on the preset MIPI clock configuration; The prescaler factor N is determined based on the MIPI byte clock, and the serial output divider level M is determined based on the range of the MIPI physical layer serial clock; the MIPI physical layer serial clock frequency is 4 times the MIPI byte clock frequency. Calculate the final frequency division factor and preload it into the PLL, start the TX PLL and lock the target frequency. The final frequency division factor is 4 times N multiplied by M.

5. The apparatus according to claim 4, characterized in that, The configuration unit is specifically used for: Configure the digital and analog layer parameters of the receiver RX, and configure the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, and set RX and TX to bypass mode; The configuration of the PLL of the transmitter TX includes: configuring preloaded PLL parameters according to a preset MIPI clock, so that the repeater locks the target frequency in advance when there is no input signal.

6. The apparatus according to claim 4, characterized in that, The configuration unit configures the digital and analog layer parameters of the receiver RX, and configures the digital and analog layer parameters and phase-locked loop (PLL) of the transmitter TX, including: Configure the number of lanes, line sequence mapping, equalizer (EQ) parameters, and clock hardware mode for the RX. Configure the digital and analog parameters related to TX signal transmission, as well as the PLL prescaler coefficient, serial output divider settings, charge pump current, and loop filter parameters.

7. A computing device, characterized in that, The computing device includes: a memory and a processor; The memory is used to store computer programs; The processor is configured to implement the method as described in any one of claims 1 to 3 when executing the computer program.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 3.

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