Memory structure, manufacturing method thereof, operating method thereof and memory array

Abstract

The invention provides a memory structure, a manufacturing method thereof, an operating method thereof and a memory array. The memory structure comprises a plurality of insulating layers, a plurality of gate layers, a first doped layer, a plurality of second doped layers, a plurality of third doped layers, a columnar channel, a first dielectric layer, a plurality of second dielectric layers and a third dielectric layer. The first doped layer and the columnar channel penetrate through the insulating layers and the gate layers which are alternately stacked. The second doped layers are in direct contact with the first doped layers to form a plurality of tunnel diodes, in which the second doped layers and the insulating layers are alternately stacked. The third doped layer surrounds the columnar channel and is connected to the second doped layer. The first dielectric layer is located between the first doped layer and the gate layer. The second dielectric layer is located between the third doped layer and the gate layer. The third dielectric layer is located between the columnar channel and the third doped layer.

Description

Technical Field

[0001] The present disclosure relates to a memory structure, a method for manufacturing a memory structure, an operating method for a memory structure, and a memory array. Background Art

[0002] Dynamic random access memory (DRAM) has been widely used due to its advantages such as high density, low cost, and low power consumption. However, as memory technology approaches its physical limits, traditional DRAM (e.g., 1T1C DRAM) faces numerous challenges in its development. For example, DRAM size is difficult to scale down, DRAM processes are becoming increasingly complex, and the aspect ratio of capacitors increases significantly as size decreases. In view of these challenges, a new dynamic random access memory and its manufacturing method are needed to overcome these challenges. Summary of the Invention

[0003] The present disclosure provides a memory structure comprising a plurality of insulating layers, a plurality of gate layers, a first doped layer, a plurality of second doped layers, a columnar channel, a plurality of third doped layers, a fourth doped layer, a fifth doped layer, a first dielectric layer, a plurality of second dielectric layers, a third dielectric layer, and a plurality of fourth dielectric layers. The insulating layers and the gate layers are stacked alternately. The first doped layer penetrates the insulating layers and the gate layers and has a first conductivity type. The second doped layers each directly contact the first doped layer and have a second conductivity type different from the first conductivity type, wherein the first doped layer and the second doped layers form a plurality of tunnel diodes, and the second doped layers and the insulating layers are stacked alternately. The columnar channel penetrates the insulating layers and the gate layers. The third doped layers each surround the columnar channel, wherein the third doped layers each connect to the second doped layers and have a second conductivity type. The fourth doped layer and the fifth doped layer are coupled to the columnar channel. The first dielectric layer is disposed between the first doped layer and the gate layers. The second dielectric layers are each disposed between the third doped layer and the gate layers. The third dielectric layer is disposed between the columnar channel and the third doping layers. A plurality of fourth dielectric layers are respectively disposed between the second doping layers and the gate layers.

[0004] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type.

[0005] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type.

[0006] In some embodiments, the memory structure further includes a write bit line disposed on the first doped layer.

[0007] In some embodiments, the memory structure further includes a read bit line coupled to the fifth doped layer.

[0008] In some embodiments, the fourth doped layer is disposed under the columnar channel, the fifth doped layer is disposed on the columnar channel, and the fourth doped layer and the fifth doped layer have the second conductivity type.

[0009] In some embodiments, the memory structure further includes a read bit line disposed on the fifth doped layer.

[0010] In some embodiments, the pillar-shaped channel has a first conductivity type.

[0011] In some embodiments, the pillar-shaped channels are undoped.

[0012] In some embodiments, the doping concentration of the third doping layers is higher than the doping concentration of the second doping layers.

[0013] The present disclosure provides a memory array comprising a plurality of memory structures according to any of the aforementioned embodiments, a plurality of write bit lines, and a plurality of read bit lines. The write bit lines extend along a first direction, wherein the first doped layers of the memory structures arranged along the first direction are coupled to each other via the write bit lines. The read bit lines extend along a second direction, wherein the first direction is perpendicular to the second direction, and the fifth doped layers of the memory structures arranged along the second direction are coupled to each other via the read bit lines.

[0014] The present disclosure provides a method for manufacturing a memory structure, comprising the following operations: forming a first hole through a plurality of alternately stacked insulating layers and a plurality of first gate layers; forming a first dielectric layer to cover the sidewalls of the first hole; forming a first doped layer in the first hole, wherein the first doped layer has a first conductivity type; forming a second hole through the insulating layers and the first gate layers; partially removing the first gate layers exposed from the second hole to form a plurality of recesses; forming a plurality of second dielectric layers in the recesses; forming a plurality of second doped layers to cover the second dielectric layers, wherein the second doped layers have a second conductivity type different from the first conductivity type; forming a third dielectric layer in the second hole to cover the insulating layers and the second doped layers; forming a columnar channel in the second hole; removing the first dielectric layer, the first gate layers, and the second dielectric layers between the first doped layer and the second doped layers to form a plurality of channels; forming a plurality of third doped layers in the channels to directly contact the first doped layer and connect to the second doped layers, wherein the third doped layers have a second conductivity type.

[0015] In some embodiments, the manufacturing method further includes the following operations: after forming the third doped layers in the channels, forming a plurality of fourth dielectric layers adjacent to the third doped layers; and forming a plurality of second gate layers adjacent to the fourth dielectric layers.

[0016] In some embodiments, the manufacturing method further includes the following operations: before forming the second hole through these insulating layers and these first gate layers, forming a fourth doped layer in the substrate, and forming these insulating layers and these first gate layers on the substrate, wherein the second hole exposes the fourth doped layer; and doping the top portion of the columnar channel to form a fifth doped layer.

[0017] In some embodiments, the manufacturing method further includes the following operations: forming a write bit line on the first doped layer; and forming a read bit line on the fifth doped layer.

[0018] In some embodiments, the first conductivity type is N-type, and the second conductivity type is P-type.

[0019] In some embodiments, the first conductivity type is P-type, and the second conductivity type is N-type.

[0020] The present disclosure provides an operating method for a memory structure, which includes the following operations. A memory structure according to any of the aforementioned embodiments is received, wherein the gate layers, the third doping layers, the fourth doping layers, the fifth doping layers, and the columnar channels form a plurality of read transistors. When the read transistors are P-type transistors and the first conductivity type is N-type, a write operation is performed, and the write operation includes: applying a reverse bias to the first of the tunnel diodes so that one of the third doping layers corresponding to the first has a high potential; or applying a forward bias to the second of the tunnel diodes so that one of the third doping layers corresponding to the second has a low potential. When the read transistors are N-type transistors and the first conductivity type is P-type, a write operation is performed, and the write operation includes: applying a reverse bias to the third of the tunnel diodes so that one of the third doping layers corresponding to the third has a low potential; or applying a forward bias to the fourth of the tunnel diodes so that one of the third doping layers corresponding to the fourth has a high potential.

[0021] In some embodiments, the read transistors are P-type transistors, and the operating method further includes the following operations: applying 0V to the select gates of the gate layers corresponding to the third doped layer having a high potential or a low potential; applying multiple negative voltages to multiple unselected gates in the gate layers; and applying a positive voltage to the fourth doped layer or the fifth doped layer.

[0022] In some embodiments, the read transistors are N-type transistors, and the operating method further includes the following operations: applying 0V to the select gates of the gate layers corresponding to the third doped layer having a high potential or a low potential; applying multiple positive voltages to multiple unselected gates in the gate layers; and applying a positive voltage to the fourth doped layer or the fifth doped layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] A more complete understanding of the present disclosure may be obtained by reading the following detailed description of the embodiments and referring to the accompanying drawings.

[0024] Figure 1A is a schematic perspective view of a memory structure according to various embodiments of the present disclosure.

[0025] Figure 1B It is along Figure 1A Schematic cross-sectional view of section line 1B-1B'.

[0026] Figure 2 It is along Figure 1B Schematic cross-sectional view of the section line AA'.

[0027] Figure 3 It is along Figure 1B Schematic cross-sectional view of section line BB'.

[0028] Figure 4 is a perspective schematic diagram of a memory array according to various embodiments of the present disclosure.

[0029] Figure 5A and Figure 5B is a flow chart of a method of manufacturing a memory structure according to various embodiments of the present disclosure.

[0030] 6A to 6I is a schematic cross-sectional view of an intermediate stage in the fabrication of a memory structure according to various embodiments of the present disclosure.

[0031] Figure 7 and Figure 8 Schematic diagrams of equivalent circuits of memory structures according to various embodiments of the present disclosure.

[0032] Figure 9 、 Figure 11 and Figure 13 4 and 5 are circuit diagrams of memory arrays according to various embodiments of the present disclosure.

[0033] Figure 10 、 Figure 12 and Figure 14 4 and 5 are timing diagrams of control signals according to various embodiments of the present disclosure.

[0034] Description of reference numerals:

[0035] 100: Memory structure

[0036] 110: Substrate

[0037] 120: Gate layer

[0038] 130: Insulation layer

[0039] 400: Memory array

[0040] 500: Manufacturing method

[0041] 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, 544: Operation

[0042] 600: Memory Structure

[0043] 700, 800: Circuit

[0044] 1B-1B': Hatch

[0045] A-A', B-B': hatching

[0046] CC: Columnar Channel

[0047] CI: Circuit

[0048] D1: first doping layer

[0049] D2: second doping layer

[0050] D3: third doping layer

[0051] D4: fourth doping layer

[0052] D5: fifth doping layer

[0053] DL1: First dielectric layer

[0054] DL2: Second dielectric layer

[0055] DL3: third dielectric layer

[0056] DL4: Fourth dielectric layer

[0057] G1: first gate layer

[0058] G2: Second gate layer

[0059] GSL1, GSL2: overall selection line

[0060] H1: First hole

[0061] H2: Second hole

[0062] MC 11 , MC 12 , MC 13 , MC 14 , MC 15 , MC 16 , MC21 , MC 22 , MC 23 , MC 24 , MC 25 , MC 26 :Memory unit

[0063] P1: Part 1

[0064] P2: Part 2

[0065] PB: Page Buffer

[0066] PG1, PG2: Page

[0067] RP: Recessed part

[0068] SN1, SN2: storage nodes

[0069] SSL1, SSL2: string selection lines

[0070] STI: Structure Isolation

[0071] SW: Sidewall

[0072] t 11 , t 12 , t 13 , t 14 , t 15 , t 21 , t 22 , t 23 , t 24 , t 31 , t 32 , t 33 , t 34 , t 35 :time

[0073] T: Channel

[0074] TD, TD1, TD2: tunnel diode

[0075] RT, RT p , RT n : Read transistor

[0076] WG1, WG2, WG3, WG4, WG5, WG6: write word lines

[0077] WBL, WBL 1- , WBL2: write bit line

[0078] RBL, RBL1, RBL2: read bit lines

[0079] RSL, RSL1, RSL2: Read source lines

[0080] V CC1 、V CC2 : Supply voltage

[0081] X: Second direction

[0082] Y: first direction DETAILED DESCRIPTION

[0083] The following multiple embodiments are described and disclosed in detail with reference to the accompanying drawings. For clarity, many practical details will be included in the following description. However, it should be understood that these practical details are not intended to limit the present disclosure. In other words, these practical details are not essential to some embodiments of the present disclosure. In addition, to simplify the drawings, some conventional structures and components are shown schematically in the drawings.

[0084] In this document, it is understood that the terms "first," "second," and "third" are used to describe various elements, components, regions, layers, and / or blocks. However, these elements, components, regions, layers, and / or blocks should not be limited by these terms. These terms are limited to identifying a single element, component, region, layer, and / or block. Therefore, a first element, component, region, layer, and / or block in the following text may also be referred to as a second element, component, region, layer, and / or block without departing from the true meaning of the present disclosure.

[0085] In addition, it should be understood that when element A is referred to as being “connected to” or “coupled to” element B, element A may be directly connected to element B or indirectly connected to element B (for example, an intermediate element C (and / or other elements) may be provided between element A and element B).

[0086] The present disclosure provides a memory structure, which is a three-dimensional (3D) dynamic random access memory (DRAM) structure. The memory structure includes a plurality of memory cells, each of which includes a tunnel diode and a read transistor to form a 1D1T DRAM structure. The memory structure of the present disclosure has a high density of memory cells, which facilitates the miniaturization of the memory structure. In addition, the process for manufacturing the memory structure is simple, which can reduce manufacturing costs and thus replace the traditional 1T1C DRAM structure. In addition, the plurality of memory structures can form a memory array, which has a high density of memory cells, which facilitates the miniaturization of the memory array.

[0087] Figure 1A is a perspective schematic diagram of a memory structure 100 according to various embodiments of the present disclosure. Figure 1B It is along Figure 1A Schematic cross-sectional view of section line 1B-1B'. Figure 2It is along Figure 1B Schematic cross-sectional view of the section line AA'. Figure 3 It is along Figure 1B The cross-sectional diagram of the section line BB'. Figures 1A to 3 As shown, the memory structure 100 includes a substrate 110, an isolation structure STI, multiple gate layers 120, multiple insulating layers 130, a first doped layer D1, multiple second doped layers D2, multiple third doped layers D3, a fourth doped layer D4, a fifth doped layer D5, a columnar channel CC, a first dielectric layer DL1, multiple second dielectric layers DL2, a third dielectric layer DL3 and multiple fourth dielectric layers DL4.

[0088] In some embodiments, the substrate 110 is a semiconductor substrate. In some embodiments, the substrate 110 includes any suitable semiconductor material and / or semiconductor material for forming a semiconductor structure. The semiconductor material includes, for example, one or more materials, such as crystalline silicon, silicon oxide, strained silicon, silicon germanium, doped or undoped polysilicon, doped or undoped silicon wafer, germanium, gallium arsenide, other suitable semiconductor materials or combinations thereof. In some embodiments, the substrate 110 is a silicon substrate. In some embodiments, the gate layer 120 includes a metal conductive material, a non-metallic conductive material or a combination thereof, such as a metal nitride. The material of the gate layer 120 includes, for example, tungsten nitride, tungsten, copper, aluminum, gold, silver, other suitable metals, metal alloys, polysilicon or combinations thereof. In some embodiments, the insulating layer 130 includes an oxide, a nitride or a combination thereof, such as silicon dioxide, silicon nitride or a combination thereof. In some embodiments, the isolation structure STI is a shallow trench isolation (STI). In some embodiments, the memory structure 100 further includes a complementary metal-oxide-semiconductor (CMOS) device (not shown) disposed in the substrate 110 to be electrically connected to the first doped layer D1 or the fourth doped layer D4 .

[0089] Please also refer to Figure 1A and Figure 1B The gate layer 120 and the insulating layer 130 are alternately stacked. The number of the gate layer 120 and the insulating layer 130 can be adjusted arbitrarily and is not limited thereto. The first doped layer D1 penetrates the gate layer 120 and the insulating layer 130 and has a first conductivity type. Figure 1BAs shown, the first doped layer D1 includes a first portion P1 and a second portion P2 connected to each other, wherein the first portion P1 penetrates the gate layer 120 and the insulating layer 130, and the second portion P2 is located in the substrate 110. The second doped layers D2 are each directly in contact with the first doped layer D1 and have a second conductivity type different from the first conductivity type. The first doped layer D1 and the second doped layer D2 form a plurality of tunnel diodes TD, wherein the second doped layers D2 and the insulating layer 130 are alternately stacked, and the tunnel diodes TD serve as channel selectors. Figure 1B As shown, the tunnel diodes TD are connected to each other in the vertical direction, so the memory structure 100 can have a high density of tunnel diodes TD, which is conducive to size reduction. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type, so the first doped layer D1 is a cathode and the second doped layer D2 is an anode. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type, so the first doped layer D1 is an anode and the second doped layer D2 is a cathode. The columnar channel CC passes through the gate layer 120 and the insulating layer 130. As shown in FIG. Figure 1B and Figure 2 As shown, the third doped layers D3 each surround the columnar channel CC and are each connected to the second doped layer D2, wherein the third doped layers D3 have the second conductivity type. In some embodiments, the third doped layers D3 directly contact the second doped layer D2. Figure 2 As shown, each gate layer 120 includes a first gate layer G1 and a second gate layer G2. The first gate layer G1 surrounds the first doped layer D1, the third doped layer D3 and the columnar channel CC. The second gate layer G2 is located on both sides of the second doped layer D2.

[0090] Please continue to refer to Figure 1B and Figure 2 , the fourth doped layer D4 and the fifth doped layer D5 are each coupled to the columnar channel CC. In some embodiments, as Figure 1B As shown, the fourth doping layer D4 is disposed under the columnar channel CC, and the fifth doping layer D5 is disposed on the columnar channel CC, but the configuration is not limited thereto, and the fourth doping layer D4 and the fifth doping layer D5 have the second conductivity type. In some embodiments, the fourth doping layer D4 is a source, and the fifth doping layer D5 is a drain. In other embodiments, the fourth doping layer D4 is a drain, and the fifth doping layer D5 is a source. The gate layer 120, the third doping layer D3, the fourth doping layer D4, the fifth doping layer D5, and the columnar channel CC form a plurality of read transistors RT. The read transistor RT can be a P-type transistor or an N-type transistor. As shown in FIG. Figure 1B As shown, these read transistors RT are connected to each other in the vertical direction, so the memory structure 100 can have a high density of read transistors RT, which is beneficial to size reduction. Figure 2 As shown, the columnar channel CC of the read transistor RT is surrounded by a third doped layer D3 and a gate layer 120, and the third doped layer D3 and the gate layer 120 serve as the gate of the read transistor RT. The third doped layer D3 is annular. A write operation can be performed, and a reverse bias (reverse bias) or a forward bias (forward bias) is applied to one of the tunnel diodes TD so that the corresponding third doped layer D3 surrounding the columnar channel CC has a high potential or a low potential. Thus, data 1 or data 0 is written to the read transistor RT. The third doped layer D3 can store charge and is chargeable or dischargeable. The potential of the third doped layer D3 can be controlled by charging or discharging the third doped layer D3. The third doped layer D3 can also be called a storage node (SN), and the storage node determines the threshold voltage of the read transistor RT. The operation method of the memory structure 100 will be further explained with a circuit diagram later.

[0091] like Figures 1B to 3 As shown, the first dielectric layer DL1 is disposed between the first doped layer D1 and the gate layer 120 and between the first doped layer D1 and the insulating layer 130, so the gate layer 120 is electrically isolated from the first doped layer D1. The second dielectric layer DL2 is each disposed between the third doped layer D3 and the gate layer 120, so the gate layer 120 is electrically isolated from the third doped layer D3. The third dielectric layer DL3 is disposed between the columnar channel CC and the third doped layer D3 and between the columnar channel CC and the insulating layer 130, so the columnar channel CC is electrically isolated from the third doped layer D3. The third dielectric layer DL3 is annular. The fourth dielectric layer DL4 is each disposed between the second doped layer D2 and the gate layer 120, so the gate layer 120 is electrically isolated from the second doped layer D2. Please refer again Figure 1A and Figure 1B In some embodiments, the third dielectric layer DL3 is disposed between the fifth doped layer D5 and one of the insulating layers 130. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include a gate oxide. In some embodiments, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3, and the fourth dielectric layer DL4 each include silicon dioxide, silicon nitride, silicon oxynitride, aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, tantalum oxide, other suitable high-k dielectric materials, or combinations thereof.

[0092] Please refer again Figure 1B and Figure 2. The first doped layer D1 has a first conductivity type, and the second doped layer D2, the third doped layer D3, the fourth doped layer D4 and the fifth doped layer D5 have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. In some embodiments, the materials of the first doped layer D1, the second doped layer D2, the third doped layer D3, the fourth doped layer D4 and the fifth doped layer D5 each include silicon, such as crystalline silicon, polycrystalline silicon or silicon germanium, but are not limited thereto. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. The read transistor RT including the fourth doped layer D4 and the fifth doped layer D5 is a P-type transistor, such as a P-type metal-oxide-semiconductor field-effect transistor (PMOSFET). In some embodiments, the doping concentration of the third doped layer D3 is higher than the doping concentration of the second doped layer D2. In some embodiments, the first doped layer D1 is an N+ doped region, the second doped layer D2 is a P- doped region, the third doped layer D3 is a P+ doped region, and the fourth doped layer D4 and the fifth doped layer D5 are P+ doped regions. In some embodiments, the columnar channel CC has the first conductivity type, and the columnar channel CC is, for example, an N- doped region. In other embodiments, the columnar channel CC is undoped.

[0093] Please refer again Figure 1B and Figure 2 . The first doped layer D1 has a first conductivity type, and the second doped layer D2, the third doped layer D3, the fourth doped layer D4 and the fifth doped layer D5 have a second conductivity type, wherein the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is P-type and the second conductivity type is N-type. The read transistor RT including the fourth doped layer D4 and the fifth doped layer D5 is an N-type transistor, such as an N-type metal-oxide-semiconductor field-effect transistor (NMOSFET). In some embodiments, the doping concentration of the third doped layer D3 is higher than the doping concentration of the second doped layer D2. In some embodiments, the first doped layer D1 is a P+ doped region, the second doped layer D2 is an N- doped region, the third doped layer D3 is an N+ doped region, and the fourth doped layer D4 and the fifth doped layer D5 are N+ doped regions. In some embodiments, the columnar channel CC has the first conductivity type, and the columnar channel CC is, for example, a P- doped region. In other embodiments, the columnar channel CC is undoped.

[0094] In some embodiments, the material of the columnar channel CC includes silicon, germanium, polysilicon, semiconductor oxides (such as indium oxide (In2O3), indium gallium zinc oxide (IGZO), indium tin oxide (ITO)), or other suitable Group III-V materials.

[0095] Please refer again Figure 1A Multiple memory structures 100 can form a memory array. The present disclosure provides a memory array comprising multiple memory structures 100, multiple write bit lines, and multiple read bit lines. The write bit lines extend along a first direction, wherein the first doped layers D1 of the memory structures 100 arranged along the first direction are coupled to each other via these write bit lines. The read bit lines extend along a second direction, wherein the first direction is perpendicular to the second direction, and the fifth doped layers D5 of the memory structures 100 arranged along the second direction are coupled to each other via these read bit lines. Figure 4 FIG is a perspective diagram of a memory array 400 according to various embodiments of the present disclosure. The memory array 400 includes 8 Figure 1A The memory structure 100 is shown, but the present disclosure is not limited thereto. The number of memory structures 100 can be arbitrarily adjusted to, for example, 2, 4, 6, 8, 10, 12, 14, 16, 18, or 20, depending on design requirements. The memory array 400 includes a plurality of memory structures 100 in a first direction Y and includes a plurality of write bit lines WBL extending along the first direction Y. The memory array 400 includes a plurality of memory structures 100 in a second direction X and includes a plurality of read bit lines RBL extending along the second direction X. The first direction Y is perpendicular to the second direction X. In the memory array 400, a plurality of gate layers 120 and a plurality of insulating layers are alternately stacked. In the second direction X, the gate layers 120 of adjacent memory structures 100 are separated by insulating layers. However, for clarity, the insulating layers are not shown. In addition, for the sake of clarity, the position of the components in the columnar structure is moved upward to clearly illustrate the relative positions of the first doped layer D1, the second doped layer D2, the third doped layer D3, the fifth doped layer D5, the first dielectric layer DL1, the second dielectric layer DL2, the third dielectric layer DL3 and the fourth dielectric layer DL4. The memory structure 100 is coupled to each other through the read bit line RBL and the write bit line WBL to form a memory array 400. Figure 4As shown, the first doped layers D1 of the memory structures 100 arranged along the first direction Y are coupled to each other via the write bit lines WBL, and the fifth doped layers D5 of the memory structures 100 arranged along the second direction X are coupled to each other via the read bit lines RBL. In the memory array 400, data can be written to the multiple memory structures 100 via the write bit lines WBL, and data in the multiple memory structures 100 can be read via the read bit lines RBL. Therefore, the memory array 400 can significantly improve the write and read speeds.

[0096] The present disclosure provides a method for manufacturing a memory structure. Figure 2 and Figures 5A to 6I . Figure 5A and Figure 5B 5 is a flow chart of a method 500 for fabricating a memory structure according to various embodiments of the present disclosure. The fabrication method 500 includes operations 512, 514, 516, 518, 520, 522, 524, 526, 528, 530, 532, 534, 536, 538, 540, 542, and 544. 6A to 6I is a cross-sectional schematic diagram of an intermediate stage of manufacturing a memory structure according to various embodiments of the present disclosure. 6A to 6I and Figure 2 The above operations 512 to 544 are described. The manufacturing method of the present disclosure has a simple process, thus reducing manufacturing costs.

[0097] Although a series of operations or steps are used below to illustrate the methods disclosed herein, the order in which these operations or steps are shown should not be construed as limiting the present disclosure. For example, certain operations or steps may be performed in different orders and / or simultaneously with other steps. Furthermore, it is not necessary to perform all of the illustrated operations, steps, and / or features to achieve the embodiments of the present disclosure. Furthermore, each operation or step described herein may include several sub-steps or actions.

[0098] In operation 512, as Figure 6A As shown, a first portion P1 of the first doped layer D1 and a fourth doped layer D4 are formed in the substrate 110. The first portion P1 of the first doped layer D1 and the fourth doped layer D4 are electrically isolated by an isolation structure STI embedded in the substrate 110. In some embodiments, the first portion P1 of the first doped layer D1 and the fourth doped layer D4 are each formed by doping a portion of the substrate 110. In operation 514, as shown in FIG. Figure 6A As shown, a plurality of insulating layers 130 and a plurality of first gate layers G1 are formed on the substrate 110. In operation 516, as shown in FIG. Figure 6AAs shown, a first hole H1 is formed through the insulating layer 130 and the first gate layer G1 to expose the first portion P1 of the first doped layer D1. In some embodiments, the first hole H1 is formed by an etching process.

[0099] In operation 518, as Figure 6B As shown, a first dielectric layer DL1 is formed to cover the sidewall SW of the first hole H1. In operation 520, as shown in FIG. Figure 6B As shown, a second portion P2 of the first doped layer D1 is formed in the first hole H1, wherein the first doped layer D1 has a first conductivity type. In some embodiments, the second portion P2 of the first doped layer D1 is formed by a deposition process. In some embodiments, the first doped layer D1 has a first conductivity type, and the fourth doped layer D4 has a second conductivity type, where the first conductivity type is different from the second conductivity type. In some embodiments, the first conductivity type is N-type and the second conductivity type is P-type. In other embodiments, the first conductivity type is P-type and the second conductivity type is N-type.

[0100] In operation 522, as Figure 6C As shown, a second hole H2 is formed through the insulating layer 130 and the first gate layer G1. The second hole H2 exposes the fourth doped layer D4. In some embodiments, the second hole H2 is formed by an etching process. In operation 524, as shown in FIG. Figure 6D As shown, the first gate layer G1 exposed from the second hole H2 is partially removed to form a plurality of recessed portions RP. After operation 524, the sidewall of the second hole H2 has a plurality of recessed portions RP. In some embodiments, the partial removal of the first gate layer G1 is performed by a wet etching process.

[0101] In operation 526, as Figure 6E As shown, a plurality of second dielectric layers DL2 are formed in the recessed portion RP to cover the partially removed first gate layer G1. In detail, each of the second dielectric layers DL2 is formed in the recessed portion RP and does not completely fill the recessed portion RP. In operation 528, as shown in FIG. Figure 6F As shown, a plurality of third doping layers D3 are formed to cover the second dielectric layer DL2, wherein the third doping layers D3 have a second conductivity type different from the first conductivity type. Specifically, each of the third doping layers D3 is formed in the recessed portion RP and fills the recessed portion RP. In operation 530, as shown in FIG. Figure 6F As shown, a third dielectric layer DL3 is formed in the second hole H2, covering the insulating layer 130 and the third doped layer D3. The third dielectric layer DL3 does not fill the second hole H2. In operation 532, as shown in FIG. Figure 6F As shown, a columnar channel CC is formed in the second hole H2 and fills the second hole H2.

[0102] In operation 534, as Figure 6GAs shown, the first dielectric layer DL1, the first gate layer G1, and the second dielectric layer DL2 between the first doped layer D1 and the third doped layer D3 are removed to form a plurality of trenches T. Specifically, portions of the first dielectric layer DL1, portions of the first gate layer G1, and portions of the second dielectric layer DL2 are removed to form the trenches T. In operation 536, as shown in FIG. Figure 6H As shown, a plurality of second doped layers D2 are formed in the trench T to directly contact the first doped layer D1 and connect to the third doped layer D3, wherein the second doped layer D2 has a second conductivity type. Figure 2 In some embodiments, the second doping layer D2 is formed by a deposition process. In some embodiments, as Figures 6F to 6H As shown, operations 528, 530, 532, 534, and 536 are sequentially performed. After forming the columnar channel CC in the second hole H2, the second doping layer D2 is formed to connect to the first doping layer D1 and the third doping layer D3. In other embodiments, after forming the second doping layer D2 to connect to the first doping layer D1 and the third doping layer D3, the columnar channel CC is formed in the second hole H2. In operation 538, as shown in FIG. Figure 2 As shown, a plurality of fourth dielectric layers DL4 are formed beside the second doped layer D2. In operation 540, as shown in FIG. Figure 2 As shown, a plurality of second gate layers G2 are formed beside the fourth dielectric layer DL4. In operation 542, as shown in FIG. Figure 6H As shown, the top portion of the columnar channel CC is doped to form a fifth doped layer D5.

[0103] In operation 544, as Figure 6I As shown, a write bit line WBL is formed on the first doping layer D1 and a read bit line RBL is formed on the fifth doping layer D5. Figure 6I The memory structure 600 is Figure 1B The difference between the memory structure 100 and the memory structure 600 is that the memory structure 600 further includes a write bit line WBL disposed on the first doping layer D1 and a read bit line RBL disposed on the fifth doping layer D5, wherein the write bit line WBL is coupled to the first doping layer D1, and the read bit line RBL is coupled to the fifth doping layer D5.

[0104] Please also refer to Figure 6I and Figure 7 . Figure 7 FIG. 7 is an equivalent circuit diagram of a memory structure 600 according to various embodiments of the present disclosure. The circuit 700 includes a memory cell MC. 11 , MC 12 , MC 13 , MC 14 , MC 15 , MC 16, write bit line WBL, read bit line RBL, read source line RSL and multiple write word lines WG1, WG2, WG3, WG4, WG5, WG6. Circuit 700 can also be called a string circuit. In some embodiments, in the memory structure 600, the first conductivity type is N-type, the second conductivity type is P-type, the first doping layer D1 is an N+ doping region, the second doping layer D2 is a P- doping region, and the first doping layer D1 and the second doping layer D2 are formed as shown in FIG. Figure 7 The multiple tunnel diodes TD1 shown in FIG. 1 are configured such that the first doped layer D1 is a cathode and the second doped layer D2 is an anode. Furthermore, the third doped layer D3 is a P+ doped region, and the fourth doped layer D4 and the fifth doped layer D5 are P+ doped regions. The gate layer 120, the third doped layer D3, the fourth doped layer D4, the fifth doped layer D5 and the columnar channel CC form a structure as shown in FIG. Figure 7 The plurality of read transistors RT shown p , that is, multiple P-type transistors. Figure 6I The third doping layers D3 correspond to Figure 7 The cathodes of the tunnel diodes TD1 are commonly connected to the write bit line WBL, and the anodes of the tunnel diodes TD1 are respectively connected to the storage nodes SN1.

[0105] Please continue to refer to Figure 6I and Figure 7 The present disclosure provides a memory cell MC 11 Operation method of memory cell MC 11 Includes tunnel diode TD1 and read transistor RT p The tunnel diode TD1 is coupled to the write bit line WBL, one of the gate layers 120 is coupled to the write word line WG1, and one of the third doped layers D3 is used as the read transistor RT. p The storage node SN1, the read transistor RT p The storage node SN1 is coupled to the read source line RSL and the read bit line RBL. The storage node SN1 forms a capacitor with the adjacent gate layer 120.

[0106] When data 0 is to be written, reverse bias is applied to the tunnel diode TD1. More specifically, the voltage applied to the write bit line WBL is higher than the voltage applied to the write word line WG1. As a result, electron tunneling occurs in the tunnel diode TD1, causing the storage node SN1 to have a high potential. The storage node SN1 determines the read transistor RT. p Therefore, during the read operation, no current flows through the read transistor RT. pWhen data 1 is to be written, a forward bias is applied to the tunnel diode TD1. More specifically, the voltage applied to the write bit line WBL is lower than the voltage applied to the write word line WG1. As a result, the storage node SN1 has a low potential, and the storage node SN1 determines the read transistor RT. p Therefore, during the read operation, the current flowing through the read transistor RT is measured. p In addition, please refer to the memory cell MC 11 To understand the memory cell MC 12 , MC 13 , MC 14 , MC 15 , MC 16 The structure and operation of the memory cell MC are not described in detail. 11 , MC 12 , MC 13 , MC 14 , MC 15 , MC 16 Can store data 1 or data 0 respectively.

[0107] Please continue to refer to Figure 6I and Figure 7 The present disclosure provides an operating method of a memory structure 600. A write operation is performed, which includes applying a reverse bias voltage to the first of the tunnel diodes TD1 so that the third doped layer D3 (or storage node SN1) corresponding to the first has a high potential, thereby writing data 0 to the corresponding read transistor RT. p Alternatively, a write operation is performed, which includes applying a forward bias to the second of the tunnel diodes TD1 so that one of the third doped layers D3 (or storage node SN1) corresponding to the second one has a low potential, thereby writing data 1 to the corresponding read transistor RT. p In some embodiments, the operating method further includes the following operations: applying 0V to the select gates of the gate layers 120 corresponding to the third doping layer D3 having a high potential or a low potential; applying multiple negative voltages to multiple unselected gates in the gate layers 120 to turn on the read transistors RT corresponding to the unselected gates; p Apply a positive voltage to the fourth doping layer D4 or the fifth doping layer D5 to read the read transistor RT of the corresponding select gate. p The data in is 0 or 1.

[0108] Please also refer to Figure 6I and Figure 8 . Figure 8 FIG8 is an equivalent circuit diagram of the memory structure 600 according to various embodiments of the present disclosure. The circuit 800 includes a memory cell MC21 , MC 22 , MC 23 , MC 24 , MC 25 , MC 26 , write bit line WBL, read bit line RBL, read source line RSL and multiple write word lines WG1, WG2, WG3, WG4, WG5, WG6. Circuit 800 can also be called a series circuit. In some embodiments, in the memory structure 600, the first conductivity type is P type, the second conductivity type is N type, the first doping layer D1 is a P+ doping region, the second doping layer D2 is an N- doping region, and the first doping layer D1 and the second doping layer D2 are formed as shown in FIG. Figure 8 The multiple tunnel diodes TD2 shown in FIG. 1 are configured such that the first doped layer D1 is an anode and the second doped layer D2 is a cathode. Furthermore, the third doped layer D3 is an N+ doped region, and the fourth doped layer D4 and the fifth doped layer D5 are N+ doped regions. The gate layer 120, the third doped layer D3, the fourth doped layer D4, the fifth doped layer D5 and the columnar channel CC form a structure as shown in FIG. Figure 8 The plurality of read transistors RT shown n , that is, multiple N-type transistors. Figure 6I The third doping layers D3 correspond to Figure 8 The anodes of the tunnel diodes TD2 are commonly connected to the write bit line WBL, and the cathodes of the tunnel diodes TD2 are respectively connected to the storage nodes SN2.

[0109] Please continue to refer to Figure 6I and Figure 8 The present disclosure provides a memory cell MC 21 Operation method of memory cell MC 21 Includes tunnel diode TD2 and read transistor RT n The tunnel diode TD2 is coupled to the write bit line WBL, one of the gate layers 120 is coupled to the write word line WG1, and one of the third doped layers D3 is used as the read transistor RT. n The storage node SN2, the read transistor RT n The storage node SN2 is coupled to the read source line RSL and the read bit line RBL. The storage node SN2 forms a capacitor with the adjacent gate layer 120.

[0110] When data 1 is to be written, a forward bias is applied to the tunnel diode TD2. More specifically, the voltage applied to the write bit line WBL is higher than the voltage applied to the write word line WG1. As a result, the storage node SN2 has a high potential, and the storage node SN2 determines the read transistor RT. n Therefore, during the read operation, the current flowing through the read transistor RT is measured.n When data 0 is to be written, reverse bias is applied to the tunnel diode TD2. More specifically, the voltage applied to the write bit line WBL is lower than the voltage applied to the write word line WG1. As a result, electron tunneling occurs in the tunnel diode TD2, causing the storage node SN2 to have a low potential. The storage node SN2 determines the read transistor RT. n Therefore, during the read operation, no current flows through the read transistor RT n In addition, please refer to the memory cell MC 21 To understand the memory cell MC 22 , MC 23 , MC 24 , MC 25 , MC 26 The structure and operation of the memory cell MC are not described in detail. 21 , MC 22 , MC 23 , MC 24 , MC 25 , MC 26 Can store data 1 or data 0 respectively.

[0111] Please continue to refer to Figure 6I and Figure 8 The present disclosure provides an operating method of a memory structure 600. A write operation is performed, which includes applying a reverse bias voltage to the first of the tunnel diodes TD2 so that the third doped layer D3 (or storage node SN2) corresponding to the first one has a low potential, thereby writing data 0 to the corresponding read transistor RT. n Alternatively, a write operation is performed, which includes applying a forward bias to the second of the tunnel diodes TD2 so that one of the third doped layers D3 (or storage node SN2) corresponding to the second one has a high potential, thereby writing data 1 to the corresponding read transistor RT. n In some embodiments, the operating method further includes the following operations: applying 0V to the select gates of the gate layers 120 corresponding to the third doping layer D3 having a high potential or a low potential; applying multiple positive voltages to multiple unselected gates in the gate layers 120 to turn on the read transistors RT corresponding to the unselected gates; n Apply a positive voltage to the fourth doping layer D4 or the fifth doping layer D5 to read the read transistor RT of the corresponding select gate. n The data in is 0 or 1.

[0112] Please refer again Figure 1A 、 Figure 1B and Figure 4. In some embodiments, the memory array 400 further includes a plurality of read source lines (not shown) extending along the first direction Y, and the fourth doped layers D4 of the memory structures 100 arranged along the first direction Y are coupled to each other through these read source lines. In some embodiments, the read source lines are commonly connected to a page buffer (not shown). In some embodiments, the write bit lines WBL are respectively connected to string select lines (SSL) having transistors (not shown) to control whether the voltage of the write bit lines WBL is applied to the memory structure 100. In some embodiments, in the memory array 400, the first doped layers D1 are respectively connected to global select lines (GSL) having transistors (not shown) to control the voltage applied to the first doped layers D1.

[0113] Next, Figures 9 to 14 Further explains how to write, read, or clear data from the memory array. Figure 9 FIG. 1 is a circuit diagram of a memory array according to various embodiments of the present disclosure. Figure 9 As shown, circuit CI includes pages PG1 and PG2, write word lines WG1, WG2, and WG3, write bit lines WBL1 and WBL2, read source lines RSL1 and RSL2, string select lines SSL1 and SSL2, global select lines GSL1 and GSL2, and a page buffer PB. Pages PG1 and PG2 each include six memory cells, each of which includes a tunnel diode and a P-type read transistor. The page buffer PB may be further coupled to a sense amplifier (SA) (not shown). Write word lines WG1, WG2, and WG3 are coupled to the P-type read transistors in pages PG1 and PG2, respectively. In pages PG1 and PG2, during a read operation, read bit lines RBL1 and RBL2 may be applied or de-applied, thereby determining which page's data is read. In pages PG1 and PG2, string select lines SSL1 and SSL2 and global select lines GSL1 and GSL2, respectively, are used to control the switching of transistors, which serve as switches for selecting the string circuit. Transistors on different strings share the same string select line and the same global select line. The string circuits in page PG1 and page PG2 are connected to the source or drain of the transistors of the string select line and the global select line respectively. Supply voltage V CC1 、V CC2 They are used to provide voltage to the cathode of the tunnel diode. The read source lines RSL1 and RSL2 are respectively coupled to the serial circuits of different pages and coupled to the page buffer PB. The page buffer PB can read the data of the entire page at one time. The number of pages, write bit lines, read source lines, string select lines, overall select lines and memory cells is not limited to Figure 9 The quantity shown can be adjusted according to design requirements.

[0114] The following describes how to Figure 9 A write operation is performed in circuit CI, where page PG1 is the page selected for writing, and page PG2 is the page not selected for writing. For example, data 0 can be written to memory cell M1 on page PG1, and data 1 can be written to memory cell M2 using the operating voltages shown in Table 1 below. Specifically, the voltage of string select line SSL1 is 3.6V, which turns on the transistors, causing write bit line WBL1 to apply 3V to the cathode of the tunnel diode in the memory cell, and write bit line WBL2 to apply -1V to the cathode of the tunnel diode in the memory cell. The voltage of write word line WG1 is 0V, and the voltages of write word lines WG2 and WG3 are either -0.5V or 1V. Consequently, the tunnel diode of memory cell M1 is reverse biased, causing the storage node to have a high potential, thereby writing data 0 to memory cell M1. The tunnel diode of memory cell M2 is forward biased, causing the storage node to have a low potential, thereby writing data 1 to memory cell M2. In page PG1, the bias voltage applied to the tunnel diodes of the memory cells other than memory cells M1 and M2 is not enough to make the storage node have a high potential or a low potential. Page PG2 is a page that is not selected for writing, so the voltage of the string select line SSL2 is 0V. Please refer to Table 2 below, the supply voltage V CC2 The voltage of the write word line WG1 is 0V, and the voltages of the write word lines WG2 and WG3 are -0.5V or 1V. Therefore, in page PG2, the reverse bias applied to the tunnel diode of the memory cell is insufficient to make the storage node have a high potential.

[0115] Table 1

[0116] <![CDATA[WG1]]> <![CDATA[WG2]]> <![CDATA[WG3]]> <![CDATA[WBL1]]> <![CDATA[WBL2]]> <![CDATA[SSL1]]> <![CDATA[GSL1]]> <![CDATA[V CC1 ]]> Voltage (V) 0 -0.5 / 1 -0.5 / 1 3 -1 3.6 0 1.5

[0117] Table 2

[0118] <![CDATA[WG1]]> <![CDATA[WG2]]> <![CDATA[WG3]]> <![CDATA[WBL1]]> <![CDATA[WBL2]]> <![CDATA[SSL2]]> <![CDATA[GSL2]]> <![CDATA[V CC2 ]]> Voltage (V) 0 -0.5 / 1 -0.5 / 1 3 -1 0 3.6 1.5

[0119] Please also refer to Figure 9 and Figure 10 . Figure 10 is a timing diagram of control signals according to various embodiments of the present disclosure. The voltage of the write word line WG1 is maintained at 0V. The voltages of the unselected write word lines WG2 and WG3 are maintained at 1V or -0.5V. The voltage of the unselected string select line SSL2 is maintained at 0V. The voltage of the unselected global select line GSL2 is maintained at 3.6V. At time t 11 , the voltage of the write bit line WBL1 becomes 3V, and the voltage of the write bit line WBL2 becomes -1V. At time t 12, the voltage of the string selection line SSL1 becomes 3.6V, thus, the voltage 3V of the write bit line WBL1 is applied to the cathode of the tunnel diode of the memory cell M1, thereby writing data 0 to the memory cell M1, and the voltage -1V of the write bit line WBL2 is applied to the cathode of the tunnel diode of the memory cell M2, thereby writing data 1 to the memory cell M2. At time t 13 , the voltage of the string selection line SSL1 becomes 0V. At time t 14 , the voltage of the write bit line WBL1 becomes 0V. At time t 15 , the voltage of the global selection line GSL1 becomes 3.6V.

[0120] Figure 11 is a circuit diagram of a memory array according to various embodiments of the present disclosure. Figure 11 A read operation is performed in the circuit CI, where page PG1 is selected for reading and page PG2 is not selected for reading. For example, if the memory cell M1 of page PG1 stores data 0 and M2 stores data 1, the data of the memory cells M1 and M2 can be read using the operating voltages in Table 3 below. In more detail, the supply voltage V CC1 The voltage of the P-type read transistors in the memory cells M1 and M2 is determined by the storage node. The threshold voltage of the P-type read transistors in the memory cells M1 and M2 is determined by the storage node. The ... Figure 11 . In addition, the voltage of the read bit line RBL1 is 0.5V, and the read source lines RSL1 and RSL2 are respectively coupled to the serial circuits of pages PG1 and PG2 to read the current. The serial circuit containing the memory cell M1 cannot measure the current, which means that the memory cell M1 stores data 0. The serial circuit containing the memory cell M2 can measure the current, which means that the memory cell M2 stores data 1. Page PG2 is a page that is not selected for reading, so the voltage of the read bit line RBL2 is 0V. In addition, a reverse bias is applied to the tunnel diode of the memory cell in page PG2 to prevent current from leaking from the storage node. Please refer to Table 4 below, the supply voltage V CC2 The voltage of the write word line WG1 is 0V, and the voltages of the write word lines WG2 and WG3 are -0.5V. It can be seen that the tunnel diodes of the memory cells in page PG2 are all reverse biased.

[0121] Table 3

[0122]

[0123] Table 4

[0124]

[0125] Please also refer to Figure 11 and Figure 12 . Figure 12 1 is a timing diagram of control signals according to various embodiments of the present disclosure. The voltage of the unselected write word lines WG2 and WG3 is maintained at -0.5V. At time t 21 , the voltage of the write word line WG1 becomes 0V. At time t 22 , the voltage of the read bit line RBL1 becomes 0.5V. At time t 23 , the voltage of the read bit line RBL1 becomes 0V. At time t 24 , the voltage of the write word line WG1 becomes -0.5V. Therefore, at time t 22 To time t 23 During the period, a current can be measured on the read source line RSL2, indicating that the memory cell M2 stores data 1. On the other hand, no current is measured on the read source line RSL1, indicating that the memory cell M1 stores data 0.

[0126] Figure 13 is a circuit diagram of a memory array according to various embodiments of the present disclosure. Figure 13 An erase operation is performed in the circuit CI, where page PG1 is the page selected for erasure and page PG2 is the page not selected for erasure. For example, the data in the memory cell of page PG1 can be cleared by the operating voltage in the following Table 5. The voltage of the string selection line SSL1 is 3.6V, so the transistor can be turned on, and the write bit lines WBL1 and WBL2 apply 3V to the cathode of the tunnel diode in the memory cell. The voltages of the write word lines WG1, WG2, and WG3 are all 0V. Therefore, the tunnel diodes of the memory cells are all reverse biased so that the storage nodes have a high potential, thereby writing data 0 to the memory cells of page PG1. On the other hand, please refer to the following Table 6. In page PG2, the voltage of the string selection line SSL2 is 0V, so the memory cells of page PG2 will not be affected by the voltage of the write bit lines WBL1 and WBL2. Supply voltage V CC2 The voltage of the write word lines WG1, WG2, and WG3 are all 0V. Therefore, in page PG2, the reverse bias voltage applied to the tunnel diode of the memory cell is insufficient to make the storage node have a high potential.

[0127] Table 5

[0128] <![CDATA[WG1]]> <![CDATA[WG2]]> <![CDATA[WG3]]> <![CDATA[WBL1]]> <![CDATA[WBL2]]> <![CDATA[SSL1]]> <![CDATA[GSL1]]> <![CDATA[V CC1 ]]> Voltage (V) 0 0 0 3 3 3.6 0 1.5

[0129] Table 6

[0130] <![CDATA[WG1]]> <![CDATA[WG2]]> <![CDATA[WG3]]> <![CDATA[WBL1]]> <![CDATA[WBL2]]> <![CDATA[SSL2]]> <![CDATA[GSL2]]> <![CDATA[V CC2 ]]> Voltage (V) 0 0 0 3 3 0 3.6 1.5

[0131] Please also refer to Figure 13 and Figure 14 . Figure 14 1 is a timing diagram of control signals according to various embodiments of the present disclosure. The voltages of the write word lines WG1, WG2, and WG3 are maintained at 0V. The voltage of the global select line GSL2 is maintained at 3.6V. At time t 31 , the voltage of the write bit lines WBL1 and WBL2 becomes 3V. At time t 32 , the voltage of the string select line SSL1 becomes 3.6V. As a result, the voltage 3V of the write bit lines WBL1 and WBL2 is applied to the cathode of the tunnel diode of the memory cell of page PG1, thereby applying a reverse bias to the tunnel diode, thereby making the storage node have a high potential. In other words, data 0 is written to the memory cell. At time t 33 , the voltage of the string selection line SSL1 becomes 0V. At time t 34 , the voltages of the write bit lines WBL1 and WBL2 become 0 V. At time t35 , the voltage of the global selection line GSL1 becomes 3.6 V.

[0132] In summary, the present disclosure provides a memory structure, a manufacturing method, an operating method thereof, and a memory array. In the memory structure and memory array, each memory cell includes a tunnel diode and a read transistor, forming a 1D1T DRAM structure. The read transistors are interconnected vertically, thereby increasing the density of memory cells and facilitating miniaturization of the memory structure and memory array. Furthermore, the manufacturing method of the present disclosure has a simple process flow, thereby reducing manufacturing costs.

[0133] Although the present disclosure has been described in considerable detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0134] It will be apparent to those skilled in the art that various modifications and variations may be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the appended claims.

Claims

1. A memory structure comprising: Multiple insulating layers and multiple gate layers stacked alternately; a first doped layer, penetrating the insulating layers and the gate layers, and having a first conductivity type; a plurality of second doped layers, each directly contacting the first doped layer and having a second conductivity type different from the first conductivity type, wherein the first doped layer and the second doped layers form a plurality of tunnel diodes, and the second doped layers and the insulating layers are alternately stacked; a columnar channel penetrating the insulating layers and the gate layers; A plurality of third doped layers, each surrounding the columnar channel, wherein the third doped layers are each connected to the second doped layers, and the third doped layers have the second conductivity type; a fourth doped layer and a fifth doped layer, coupled to the columnar channel; a first dielectric layer disposed between the first doped layer and the gate layers; a plurality of second dielectric layers, each disposed between the third doped layers and the gate layers; a third dielectric layer disposed between the columnar channel and the third doped layers; as well as A plurality of fourth dielectric layers are respectively disposed between the second doped layers and the gate layers. 2 . The memory structure according to claim 1 , wherein the first conductivity type is N-type, and the second conductivity type is P-type. 3 . The memory structure according to claim 1 , wherein the first conductivity type is P-type, and the second conductivity type is N-type. 4 . The memory structure according to claim 1 , further comprising a write bit line disposed on the first doped layer. 5 . The memory structure of claim 1 , further comprising a read bit line coupled to the fifth doped layer. 6 . The memory structure according to claim 1 , wherein the fourth doped layer is disposed under the columnar channel, the fifth doped layer is disposed on the columnar channel, and the fourth doped layer and the fifth doped layer have the second conductivity type. 7 . The memory structure according to claim 6 , further comprising a read bit line disposed on the fifth doped layer. The memory structure according to claim 6 , wherein the pillar-shaped channel has the first conductivity type.

9. The memory structure of claim 1, wherein the pillar channel is undoped. 10 . The memory structure according to claim 1 , wherein the doping concentration of the third doping layers is higher than the doping concentration of the second doping layers.

11. A memory array comprising: A plurality of memory structures according to any one of claims 1 to 9; A plurality of write bit lines extending along a first direction, wherein the first doped layers of the memory structures arranged along the first direction are coupled to each other through the write bit lines; as well as A plurality of read bit lines extend along a second direction, wherein the first direction is perpendicular to the second direction, and the fifth doped layers of the memory structures arranged along the second direction are coupled to each other through the read bit lines.

12. A method for manufacturing a memory structure, comprising: forming a first hole penetrating the alternately stacked plurality of insulating layers and the plurality of first gate layers; forming a first dielectric layer to cover a sidewall of the first hole; forming a first doped layer in the first hole, wherein the first doped layer has a first conductivity type; forming a second hole penetrating through the insulating layers and the first gate layers; Partially removing the first gate layers exposed from the second hole to form a plurality of recessed portions; forming a plurality of second dielectric layers in the recessed portions; forming a plurality of second doped layers covering the second dielectric layers, wherein the second doped layers have a second conductivity type different from the first conductivity type; forming a third dielectric layer in the second hole to cover the insulating layers and the second doped layers; forming a columnar channel in the second hole; removing the first dielectric layer, the first gate layers, and the second dielectric layers between the first doped layer and the second doped layers to form a plurality of channels; as well as A plurality of third doping layers are formed in the channels to directly contact the first doping layer and connect to the second doping layers, wherein the third doping layers have the second conductivity type.

13. The manufacturing method according to claim 12, further comprising: After forming the third doped layers in the trenches, forming a plurality of fourth dielectric layers next to the third doped layers; as well as A plurality of second gate layers are formed beside the fourth dielectric layers.

14. The manufacturing method according to claim 12, further comprising: Before forming the second hole through the insulating layers and the first gate layers, forming a fourth doped layer in a substrate, and forming the insulating layers and the first gate layers on the substrate, wherein the second hole exposes the fourth doped layer; and A top portion of the columnar channel is doped to form a fifth doped layer.

15. The manufacturing method according to claim 14, further comprising: forming a write bit line on the first doped layer; as well as A read bit line is formed on the fifth doped layer. The manufacturing method according to claim 12 , wherein the first conductivity type is N-type, and the second conductivity type is P-type. The manufacturing method according to claim 12 , wherein the first conductivity type is P type, and the second conductivity type is N type.

18. A method for operating a memory structure, comprising: The memory structure according to claim 1 , wherein the gate layers, the third doped layers, the fourth doped layer, the fifth doped layer, and the pillar channel form a plurality of read transistors. as well as Performing a write operation, the write operation comprising: When the read transistors are P-type transistors, the first conductivity type is N-type. Applying a reverse bias voltage to a first one of the tunnel diodes so that one of the third doped layers corresponding to the first one has a high potential; or applying a forward bias voltage to a second one of the tunnel diodes so that one of the third doped layers corresponding to the second one has a low potential; When the read transistors are N-type transistors, the first conductivity type is P-type. A reverse bias is applied to a third of the tunnel diodes so that one of the third doped layers corresponding to the third one has a low potential; or a forward bias is applied to a fourth of the tunnel diodes so that one of the third doped layers corresponding to the fourth one has a high potential.

19. The operating method according to claim 18, wherein the read transistors are P-type transistors, the operating method further comprising: Applying 0V to a select gate of the gate layers corresponding to the third doping layer having the high potential or the low potential; applying a plurality of negative voltages to a plurality of unselected gates in the gate layers; as well as A positive voltage is applied to the fourth doping layer or the fifth doping layer.

20. The operating method according to claim 18, wherein the read transistors are N-type transistors, the operating method further comprising: Applying 0V to a select gate of the gate layers corresponding to the third doping layer having the high potential or the low potential; applying a plurality of positive voltages to a plurality of unselected gates in the gate layers; as well as A positive voltage is applied to the fourth doping layer or the fifth doping layer.

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