Trench-type insulated gate bipolar transistor with wide positive bias safe working area and preparation method of trench-type insulated gate bipolar transistor

Abstract

The invention relates to the technical field of power devices, in particular to a trench-type insulated gate bipolar transistor with a wide positive bias safe working area and a preparation method, and the trench-type insulated gate bipolar transistor comprises a drift region, and a first well region and a second well region are sequentially formed above the drift region; the doping concentration of the first well region is higher than that of the second well region, so that the carrier concentration of the first well region is higher than that of the second well region. In order to solve the problem that the pinch-off voltage of a trench-type insulated gate bipolar transistor in the prior art is too small, the high-concentration doped first well region is introduced to the bottom of the well region in the scheme, so that the carrier concentration in the region is improved, the voltage drop from a collector electrode to an emitter electrode when a device works is reduced, a channel is more difficult to pinch off, and the reliability of the device is improved. The pinch-off voltage is increased, and the device enters a desaturation region later, so that the device has a larger working current and a wider positive bias safe working region.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a trench-type insulated gate bipolar transistor with a wide forward-biased safe operating area and a preparation method thereof. Background Art

[0002] An insulated-gate bipolar transistor (IGBT) is a MOS-structured bipolar device that combines the high-speed performance of a power MOSFET with the low-resistance performance of a bipolar transistor. The IGBT's switching function is to apply a positive gate voltage to form a channel, providing base current to the PNP transistor, turning the IGBT on. Conversely, applying a reverse gate voltage eliminates the channel, allowing reverse base current to flow, turning the IGBT off. IGBT devices have two typical process structures: planar and trench gate. The planar IGBT's channel is located on a flat surface on the chip, while the trench gate IGBT bypasses the JFET region by machining a vertical trench structure into the device and placing the gate therein, thereby reducing the resistance per unit area.

[0003] Patent document CN202111630323.5 provides a trench gate IGBT device, which introduces an ohmic contact dielectric layer between the P+ ohmic contact region and the N+ ohmic contact region. The ohmic contact dielectric layer isolates the P+ ohmic contact region and the N+ ohmic contact region. After isolation, the P+ ohmic contact region and the N+ ohmic contact region can be effectively prevented from diffusing along the trench direction, thereby eliminating the restriction that the distance between the P+ ohmic contact region and the N+ ohmic contact region cannot be too small, reducing the risk of threshold voltage variation, and improving the device's on-current and RBSOA capability. At the same time, due to the presence of the ohmic contact dielectric layer, the design does not need to consider the impact of the diffusion of the device's P+ ohmic contact region and N+ ohmic contact region on the IGBT channel width, reducing the design difficulty and risk, and can solve the compromise relationship between the spacing between the P+ ohmic contact region and the N+ ohmic contact region and the performance of the IGBT device, improving the performance of the IGBT device and reducing the risk in the IGBT design.

[0004] Patent document CN202010928662.0 discloses a trench-gate IGBT device, comprising a collector metal layer, a collector region, a field stop layer, a drift region, a trench structure, and an emitter metal layer stacked sequentially from bottom to top. The trench structure includes a dummy gate structure and a gate structure, wherein the dummy gate structure is located above the drift region and the gate structure is located above the drift region and in the middle. The dummy gate structure includes a narrow portion and a wide portion, with the wide portion located below the narrow portion. A carrier storage layer is provided above the drift region between the gate structure and the narrow portion, and a P-type base region is provided above the carrier storage layer. A P+ emitter region and an N+ emitter region are provided above the P-type base region, and the P+ emitter region and the N+ emitter region are electrically connected to the emitter metal layer, respectively. This effectively reduces Miller capacitance, increases IGBT switching speed, reduces IGBT switching losses, and reduces device on-state voltage drop, while also improving various IGBT performance characteristics.

[0005] However, during the actual implementation process, the inventors found that when the existing trench-type insulated gate bipolar transistor device is working, the collector-emitter is forward biased, the gate is forward biased and greater than the threshold voltage. When the collector-emitter voltage is still small, the IGBT operates in the saturation region and the current continues to rise; as the collector voltage continues to increase, when the pinch-off voltage is reached, the conductive channel close to the collector side is pinched off, the IGBT operating current no longer increases, and the IGBT exits the saturation region and enters the desaturation region, also known as the linear region. IGBTs generally operate safely in the saturation region, where the collector-emitter voltage drop is small and the device power consumption is low. In the desaturation region (linear region), the IGBT loss increases and the heat generation is serious, which is an operating state that needs to be avoided. However, the pinch-off voltage of the existing technology is small, and the conductive channel is pinched off earlier, causing the device to enter the oversaturation region too early, resulting in problems of increased voltage drop and power consumption. Summary of the Invention

[0006] In view of the above problems existing in the prior art, a trench-type insulated gate bipolar transistor with a wide forward-biased safe operating area is provided.

[0007] On the other hand, a method for preparing the trench-type insulated gate bipolar transistor is also provided.

[0008] The specific technical solutions are as follows:

[0009] A trench-type insulated gate bipolar transistor with a wide forward-biased safe operating area, comprising:

[0010] a drift region having a first doping type;

[0011] A first well region and a second well region are sequentially formed above the drift region;

[0012] The first well region and the second well region have a second doping type;

[0013] An emitter region is formed above the second well region;

[0014] The emitter region has the first doping type;

[0015] A channel is formed in the emitter region, and the depth of the channel reaches the drift region;

[0016] The inner wall of the trench is formed with a gate oxide layer and filled with polysilicon;

[0017] The doping concentration of the first well region is higher than the doping concentration of the second well region, so that the carrier concentration of the first well region is greater than the carrier concentration of the second well region.

[0018] On the other hand, the gate oxide layer in the trench includes a first gate oxide layer and a second gate oxide layer;

[0019] The first gate oxide layer is formed at the lower end point of the trench and reaches the upper boundary of the first well region in the height direction;

[0020] The second gate oxide layer is formed above the first gate oxide layer along the sidewall of the trench;

[0021] The gate oxide thickness of the first gate oxide layer is smaller than the gate oxide thickness of the second gate oxide layer.

[0022] On the other hand, the gate oxide layer climbs along the inner wall of the trench to the upper surface of the emitter region;

[0023] The gate oxide layer completely covers the upper surface of the gate oxide layer;

[0024] An interlayer dielectric layer is formed above the gate oxide layer and the channel;

[0025] An emitter metal layer is formed above the interlayer dielectric layer;

[0026] Contact holes are formed between the gate oxide layer and the emitter region, so that the emitter metal layer contacts the second well region.

[0027] On the other hand, it also includes:

[0028] a field stop layer, wherein the field stop layer is formed below the drift region;

[0029] a collector region, wherein the collector region is formed below the field stop layer;

[0030] A collector metal layer is formed on the lower surface of the collector region.

[0031] On the other hand, the first well region reduces the voltage drop from the collector to the emitter to avoid channel pinch-off when the trench gate insulated gate bipolar transistor is in operation.

[0032] A preparation method for preparing the above-mentioned trench gate insulated gate bipolar transistor comprises:

[0033] Step S1: preparing a trench on the substrate to form a gate structure;

[0034] Step S2: performing two ion implantations on the substrate to form a first well region and a second well region respectively;

[0035] The doping concentration of the first well region is higher than that of the second well region;

[0036] Step S3: performing implantation above the second well region to form an emitter region, and then processing an interlayer dielectric layer and an emitter metal layer;

[0037] Step S4: processing the collector region and the collector metal layer on the back side of the substrate.

[0038] On the other hand, the step S1 includes:

[0039] Step S11: performing trench etching on the substrate to form a trench;

[0040] Step S12: depositing a gate oxide compound to a predetermined depth at the bottom of the trench, and then etching to form a first gate oxide layer;

[0041] Step S13: growing a second gate oxide layer on the first gate oxide layer;

[0042] Step S13: depositing polysilicon in the trench.

[0043] On the other hand, the step S2 includes:

[0044] Step S21: performing a first ion implantation on the substrate to form a second well region;

[0045] Step S22: performing a second ion implantation on the second well region to form the first well region.

[0046] On the other hand, step S3 includes:

[0047] Step S31: performing implantation above the second well region to form an emitter region;

[0048] Step S32: forming an interlayer dielectric layer above the gate oxide layer;

[0049] Step S33: etching the interlayer dielectric layer, the gate oxide layer, and the emitter region to form a contact hole;

[0050] Step S34: preparing the emitter metal layer from the contact hole.

[0051] On the other hand, the step S4 includes:

[0052] Step S41: thinning the back surface of the substrate and then preparing a field stop layer;

[0053] Step S42: forming a collector region below the field stop layer;

[0054] Step S43: forming a collector metal layer below the collector region.

[0055] The above technical solution has the following advantages or beneficial effects:

[0056] To address the problem of too low pinch-off voltage of trench-type insulated gate bipolar transistors in the prior art, this solution introduces a highly doped first well region at the bottom of the well region, thereby increasing the carrier concentration in this region and reducing the collector-to-emitter voltage drop when the device is operating, making it more difficult for the channel to pinch off, increasing the pinch-off voltage, and allowing the device to enter the desaturation region later, thereby having a larger operating current and a wider forward-biased safe operating area. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] The embodiments of the present invention will be described more fully with reference to the accompanying drawings, which are provided for illustration and description only and are not intended to limit the scope of the present invention.

[0058] Figure 1 is an overall schematic diagram of an embodiment of the present invention;

[0059] Figure 2 Schematic diagram of the preparation method in an embodiment of the present invention;

[0060] Figure 3 A schematic diagram of the device structure in an embodiment of the present invention;

[0061] Figure 4 This is a schematic diagram of step S1 in an embodiment of the present invention;

[0062] Figure 5 Schematic diagram of the groove in the embodiment of the present invention;

[0063] Figure 6 Schematic diagram of depositing gate oxide at the bottom of the trench according to an embodiment of the present invention;

[0064] Figure 7 Schematic diagram of the first gate oxide layer in an embodiment of the present invention;

[0065] Figure 8 Schematic diagram of the insulating gate structure in an embodiment of the present invention;

[0066] Figure 9 This is a schematic diagram of step S2 in an embodiment of the present invention;

[0067] Figure 10 Schematic diagram of the second well region in an embodiment of the present invention;

[0068] Figure 11 Schematic diagram of the first well region in an embodiment of the present invention;

[0069] Figure 12 This is a schematic diagram of step S3 in an embodiment of the present invention;

[0070] Figure 13 Schematic diagram of the emission area in an embodiment of the present invention;

[0071] Figure 14 Schematic diagram of contact holes in an embodiment of the present invention;

[0072] Figure 15 Schematic diagram of step S4 in an embodiment of the present invention. DETAILED DESCRIPTION

[0073] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts shall fall within the scope of protection of the present invention.

[0074] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0075] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, but they are not intended to limit the present invention.

[0076] The present invention comprises:

[0077] A trench-type insulated gate bipolar transistor with a wide forward-biased safe operating area, such as Figure 1 Shown, including:

[0078] a drift region 1 having a first doping type;

[0079] A first well region 2 and a second well region 3 are sequentially formed above the drift region 1;

[0080] The first well region 2 and the second well region 3 have a second doping type;

[0081] An emitter region 4 is formed above the second well region 2;

[0082] The emitter region 4 has a first doping type;

[0083] A channel is formed in the emitter region 4, and the depth of the channel reaches the drift region 1;

[0084] The inner wall of the trench is formed with a gate oxide layer 5 and filled with polysilicon 6;

[0085] The doping concentration of the first well region 2 is higher than the doping concentration of the second well region 3 , so that the carrier concentration of the first well region 2 is greater than the carrier concentration of the second well region 3 .

[0086] Specifically, to address the problem of too low pinch-off voltage of trench-type insulated gate bipolar transistors in the prior art, this solution introduces a highly doped first well region 2 at the bottom of the well region, thereby increasing the carrier concentration in the region and reducing the collector-to-emitter voltage drop when the device is operating, making it more difficult for the channel to pinch off, increasing the pinch-off voltage, and allowing the device to enter the desaturation region later, thereby having a larger operating current and a wider forward-biased safe operating area.

[0087] Specifically, the above technical solution is implemented as an insulated gate bipolar transistor. This insulated gate transistor device is a trench gate device, with an emitter metal layer 8 located at the top of the device, a collector region 10 and a collector metal layer 11 located at the bottom of the device, and a gate formed by a gate oxide layer 5 and polysilicon 6 in the trench.

[0088] When the device is operating, the collector-emitter direction of the device is forward-biased, the gate is forward-biased and greater than the threshold voltage, the device operates in the saturation region, and the current continues to increase. When the collector voltage increases to the pinch-off voltage, the conductive channel near the collector side will pinch off first, and then the operating current of the device will no longer increase, entering the desaturation region.

[0089] Based on this characteristic, this proposal studies the structural features of trench-gate devices. The trench depth of trench-gate devices usually reaches the drift region, and the first place where pinch-off occurs appears near the bottom of the conductive channel, that is, below the well region.

[0090] To address this characteristic, in this embodiment, the well region of a conventional trench-gate device is divided into a first well region 2 and a second well region 3. The first well region 2 is located below the second well region 3, that is, close to the bottom of the trench and covering a height where premature pinch-off is likely to occur. Heavy doping is used to increase the carrier concentration in this portion of the first well region 2. As the collector voltage rises, the high carrier concentration allows this portion to withstand greater current, thereby reducing the voltage drop from the collector to the emitter, making pinch-off less likely. This allows the device to enter the desaturation region later, resulting in a higher operating current and a wider forward-biased safe operating area.

[0091] In one embodiment, the gate oxide layer 5 in the trench includes a first gate oxide layer 51 and a second gate oxide layer 52;

[0092] The first gate oxide layer 51 is formed at the lower end of the trench and reaches the upper boundary of the first well region 2 in the height direction;

[0093] The second gate oxide layer 52 is formed above the first gate oxide layer 51 along the sidewall of the trench;

[0094] The gate oxide thickness of the first gate oxide layer 51 is greater than the gate oxide thickness of the second gate oxide layer 52 .

[0095] Specifically, considering that adjusting the well region to the first well region 2 and the second well region 3 with different carrier concentrations may result in a change in the threshold voltage, in this embodiment, the structure of the insulating gate is adjusted.

[0096] In a traditional trench gate structure, the gate is etched in the active area to form a trench of a certain depth. The trench is then sacrificially oxidized to form a gate oxide layer of a certain thickness. Finally, the trench in the gate oxide layer is filled with polysilicon to form a complete insulated gate. The sacrificial oxidation process creates a uniform thickness of the gate oxide layer.

[0097] In this embodiment, the well regions are pre-adjusted to form first and second well regions 2 and 3 with different carrier concentrations, so the threshold voltage will change. To maintain the consistency of the threshold voltage, the thickness of the gate oxide layer at the height of the first well region 2 is increased in this embodiment to form a thicker first gate oxide layer 51, thereby improving the consistency of the threshold voltage.

[0098] Specifically, the height of the upper end surface of the first gate oxide layer 51 is flush with the height of the upper surface of the first well region 2 , the junction depth of the first well region 2 is smaller than the depth of the channel, and the gate oxide thickness of the first gate oxide layer 52 is greater than that of the second gate oxide layer 52 .

[0099] In one embodiment, the gate oxide layer 5 climbs along the inner wall of the trench to the upper surface of the emitter region 4;

[0100] The gate oxide layer 5 completely covers the upper surface of the emitter region 4;

[0101] An interlayer dielectric layer 7 is formed above the gate oxide layer 5 and the channel;

[0102] An emitter metal layer 8 is formed above the interlayer dielectric layer 7;

[0103] Contact holes are formed in the gate oxide layer 5 and the emitter region 4 so that the emitter metal layer 8 contacts the second well region 3 .

[0104] Specifically, in order to achieve better device characteristics, in this embodiment, during the process of sacrificial oxidation of the channel, the upper surface of the emitter region 4 is also oxidized, thereby completely covering the upper surface of the emitter region 4 .

[0105] On this basis, an interlayer dielectric layer 7 is formed above the gate oxide layer 5 and the channel. The interlayer dielectric layer is etched to form a contact hole, and then a metal material is evaporated or deposited on it to form an emitter metal layer 8. The emitter metal layer 8 is made to contact with the second well region 3 below through accumulation.

[0106] In one embodiment, it further includes:

[0107] A field stop layer 9 is formed below the drift region 1;

[0108] A collector region 10 , wherein the collector region 10 is formed below the field stop layer 9 ;

[0109] The collector metal layer 11 is formed on the lower surface of the collector region 10 .

[0110] Specifically, to achieve better withstand voltage characteristics, in this embodiment, a field-stop layer 9 is introduced below the drift region 1. This effectively generates an electric field that more regularly penetrates the chip, enabling it to maintain a higher breakdown voltage. Furthermore, the field-stop layer 9 shortens the recombination time of charges, thereby better controlling dynamic characteristics.

[0111] Below the field stop layer, a collector region 10 is provided. The collector region 10 has a heavily doped second doping type.

[0112] In one embodiment, the first doping type is N-type, and the second doping type is P-type.

[0113] Among them, the drift region 1 is lightly N-type doped, the first well region 2 is heavily P-type doped, the second well region 3 is lightly P-type doped, the emitter region 4 is heavily N-type doped, the field stop layer 9 is heavily N-type doped, and the collector region is heavily P-type doped.

[0114] In another embodiment, the first doping type is P-type, and the second doping type is N-type.

[0115] A preparation method for preparing the trench gate insulated gate bipolar transistor, such as Figure 2 、 3 Shown, including:

[0116] Step S1: preparing a trench on the substrate to form a gate structure;

[0117] Step S2: performing two ion implantations on the substrate to form a first well region and a second well region respectively;

[0118] The doping concentration of the first well region is higher than that of the second well region;

[0119] Step S3: performing implantation above the second well region to form an emitter region, and then processing an interlayer dielectric layer and an emitter metal layer;

[0120] Step S4: Processing the collector region and collector metal layer on the back side of the substrate.

[0121] Specifically, to achieve a better fabrication process, in this embodiment, a trench fabrication process is first performed on substrate A1 to form an insulated gate structure. Substrate A1 is previously implanted with N-type light doping to form an N-type substrate, which can be used as an N-drift region in subsequent processes.

[0122] Subsequently, the substrate A1 is subjected to two ion implantations to form a first well region A2 and a second well region A3 respectively. Specifically, during the implantation process, the doping concentration of the first well region A2 is greater than that of the second well region A3, and the first well region A2 needs to be formed at the bottom of the second well region.

[0123] For the substrate A1, P-type light doping can be first performed to form a second well region A3 on the substrate A1, and then high-energy implantation can be performed on the second well region A3 to form a P-type heavily doped first well region A2 at the bottom of the second well region A3.

[0124] Then, an implantation is performed above the second well region A3 to form an emitter region A4, and an interlayer dielectric layer A5 and an emitter metal layer A6 are prepared;

[0125] After completing the front-side preparation process of the device, the back-side preparation process of the device is started, including further implanting the N-type lightly doped substrate A1 from the back to form an N-type heavily doped field stop region A7. At this time, the N-type lightly doped portion retained above is used as a drift region.

[0126] Then, a P-type heavy doping implant is performed on the bottom of the field stop region A7 to form a collector region A8. Finally, a collector metal layer A9 is formed by deposition to complete the device manufacturing process.

[0127] In one embodiment, Figure 4 As shown, step S1 includes:

[0128] Step S11: performing trench etching on the substrate to form a trench;

[0129] Step S12: depositing a gate oxide compound to a predetermined depth at the bottom of the trench, and then etching to form a first gate oxide layer;

[0130] Step S13: growing a second gate oxide layer on the first gate oxide layer;

[0131] Step S14: depositing polysilicon in the trench.

[0132] Specifically, in order to achieve a better trench gate preparation effect, in this embodiment, as Figure 5As shown, first, for a substrate that has been lightly N-type doped, photoresist is placed at predetermined positions on the surface to define the positions of two trenches, and then etching is performed to form a pair of trenches.

[0133] Then, if Figure 6 As shown, a gate oxide compound is deposited to a predetermined depth at the bottom of the trench by sacrificial oxidation and HDP process, thereby filling the bottom of the trench. The predetermined depth should be flush with the portion where the first well region A2 is to be formed later.

[0134] Subsequently, the gate oxide compound at the bottom of the trench is photolithographically processed, such as Figure 7 As shown, a slightly narrow trench is formed in the gate oxide compound for subsequent filling of polysilicon, and the gate oxide thickness of the predetermined first gate oxide layer A10 is adjusted by controlling the width of the sub-trench, thereby adjusting the threshold voltage of the device to achieve good voltage consistency.

[0135] Then, the photoresist is removed, and a second gate oxide layer A11 is grown on the first gate oxide layer A10 and on the upper surface of the substrate A1. Figure 8 As shown, a continuous gate oxide layer structure is formed, and finally polysilicon is deposited in the trench to form a trench gate structure.

[0136] In one embodiment, Figure 9 As shown, step S2 includes:

[0137] Step S21: performing a first ion implantation on the substrate to form a second well region;

[0138] Step S22: performing a second ion implantation on the second well region to form a first well region.

[0139] Specifically, in order to increase the carrier concentration of the first well region A2 at a height where the channel is easily pinched off, in this embodiment, during the injection process, as shown in FIG. Figure 10 As shown, for the substrate A1, a P-type light doping can be performed first to form a second well region A3 on the substrate A1, as shown in FIG. Figure 11 As shown, high energy implantation is then performed on the second well region A3, thereby forming a heavily P-type doped first well region A2 at the bottom of the second well region A3.

[0140] In one embodiment, Figure 12 As shown, step S3 includes:

[0141] Step S31: performing implantation above the second well region to form an emitter region;

[0142] Step S32: forming an interlayer dielectric layer above the gate oxide layer;

[0143] Step S33: etching the interlayer dielectric layer, the gate oxide layer and the emitter region to form contact holes;

[0144] Step S34: preparing an emitter metal layer from the contact hole.

[0145] Specifically, in order to achieve a better device preparation effect, in this embodiment, on the basis of forming the first well region A2 and the second well region A3, ion implantation and annealing are further performed on the top of the second well region A3, such as Figure 13 As shown, an N-type heavily doped emitter region A4 is formed within a certain depth above the second well region A3.

[0146] Subsequently, metal is deposited on the gate oxide layer to form a complete interlayer dielectric layer A5, and then Figure 14 As shown, the interlayer dielectric layer A5, gate oxide layer and emitter region A4 are etched to open contact holes. The depth of each contact hole can completely pass through the emitter region A4 and reach the second well region A3 below. The contact hole is opened at the center line of the emitter region A4.

[0147] Finally, metal material is gradually accumulated from the contact hole by deposition or evaporation to form the emitter metal layer A6.

[0148] In one embodiment, Figure 15 As shown, step S4 includes:

[0149] Step S41: thinning the back side of the substrate and then preparing a field stop layer;

[0150] Step S42: forming a collector region below the field stop layer;

[0151] Step S43: forming a collector metal layer below the collector region.

[0152] Specifically, to achieve better device preparation effects, in this embodiment, the back side of the substrate A1 is first thinned, and then an N-type heavily doped field stop layer A7 is formed through ion implantation and annealing steps, and the upper N-type lightly doped part is used as a drift region.

[0153] Then, the P-type heavy doping is performed on the lower portion of the field stop layer A7 by ion implantation to form a collector region A8. Finally, a collector metal layer A9 is formed under the collector region A8 by metal deposition.

[0154] The above are only preferred embodiments of the present invention and do not limit the implementation mode and protection scope of the present invention. For those skilled in the art, it should be aware that all solutions obtained by equivalent substitutions and obvious changes made using the description and illustrations of the present invention should be included in the protection scope of the present invention.

Claims

1. A trench insulated gate bipolar transistor with a wide forward-biased safe operating area, characterized in that: include: a drift region having a first doping type; A first well region and a second well region are sequentially formed above the drift region; The first well region and the second well region have a second doping type; An emitter region is formed above the second well region; The emitter region has the first doping type; A channel is formed in the emitter region, and the depth of the channel reaches the drift region; The inner wall of the trench is formed with a gate oxide layer and filled with polysilicon; The doping concentration of the first well region is higher than the doping concentration of the second well region, so that the carrier concentration of the first well region is greater than the carrier concentration of the second well region.

2. The trench gate insulated gate bipolar transistor according to claim 1, wherein: The gate oxide layer in the trench includes a first gate oxide layer and a second gate oxide layer; The first gate oxide layer is formed at the lower end point of the trench and reaches the upper boundary of the first well region in the height direction; The second gate oxide layer is formed above the first gate oxide layer along the sidewall of the trench; The gate oxide thickness of the first gate oxide layer is smaller than the gate oxide thickness of the second gate oxide layer.

3. The trench gate insulated gate bipolar transistor according to claim 1, wherein: The gate oxide layer climbs along the inner wall of the trench to the upper surface of the emitter region; The gate oxide layer completely covers the upper surface of the emitter region; An interlayer dielectric layer is formed above the gate oxide layer and the channel; An emitter metal layer is formed above the interlayer dielectric layer; Contact holes are formed between the gate oxide layer and the emitter region, so that the emitter metal layer contacts the second well region.

4. The trench gate insulated gate bipolar transistor according to claim 1, wherein: Also includes: a field stop layer, wherein the field stop layer is formed below the drift region; a collector region, wherein the collector region is formed below the field stop layer; A collector metal layer is formed on the lower surface of the collector region.

5. The trench gate insulated gate bipolar transistor according to claim 1, wherein: The first well region reduces the voltage drop from the collector to the emitter to avoid channel pinch-off when the trench gate insulated gate bipolar transistor is in operation.

6. A preparation method, characterized in that: For preparing the trench gate insulated gate bipolar transistor according to any one of claims 1 to 5, comprising: Step S1: preparing a trench on the substrate to form a gate structure; Step S2: performing two ion implantations on the substrate to form a first well region and a second well region respectively; The doping concentration of the first well region is higher than that of the second well region; Step S3: performing implantation above the second well region to form an emitter region, and then processing an interlayer dielectric layer and an emitter metal layer; Step S4: processing the collector region and the collector metal layer on the back side of the substrate.

7. The preparation method according to claim 6, characterized in that The step S1 comprises: Step S11: performing trench etching on the substrate to form a trench; Step S12: depositing a gate oxide compound to a predetermined depth at the bottom of the trench, and then etching to form a first gate oxide layer; Step S13: growing a second gate oxide layer on the first gate oxide layer; Step S14: depositing polysilicon in the trench.

8. The preparation method according to claim 6, characterized in that The step S2 comprises: Step S21: performing a first ion implantation on the substrate to form a second well region; Step S22: performing a second ion implantation on the second well region to form the first well region.

9. The preparation method according to claim 6, characterized in that The step S3 comprises: Step S31: performing implantation above the second well region to form an emitter region; Step S32: forming an interlayer dielectric layer above the gate oxide layer; Step S33: etching the interlayer dielectric layer, the gate oxide layer, and the emitter region to form a contact hole; Step S34: preparing the emitter metal layer from the contact hole.

10. The preparation method according to claim 6, characterized in that The step S4 comprises: Step S41: thinning the back surface of the substrate and then preparing a field stop layer; Step S42: forming a collector region below the field stop layer; Step S43: forming a collector metal layer below the collector region.

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