Chip structure, manufacturing method thereof and vehicle

Abstract

The invention provides a chip structure, a manufacturing method thereof and a vehicle. Specifically, the chip structure comprises a substrate layer and an N-type drift layer, the N-type drift layer is arranged on the upper surface of the substrate layer, at least a field oxide layer, a gate oxide layer, a polycrystalline silicon gate and an insulating medium layer are arranged on the upper surface of the N-type drift layer in a stacked mode, and a cellular structure is formed between the gate oxide layer and an N-type drift region of the N-type drift layer; the area where the cellular structure is located is provided with a first type of source electrode contact hole, the first type of source electrode contact hole penetrates from the insulating dielectric layer to the upper surface of the N-type drift layer, the insulating dielectric layer is provided with a grid electrode contact hole, and the grid electrode contact hole penetrates from the outer side of the insulating dielectric layer to the surface of the polycrystalline silicon grid electrode; and a second type source contact hole is arranged between the grid contact hole and the first type source contact hole. The problem that in the prior art, in the turn-off process of a SiC MOSFET chip, due to the fact that an energy escape path is too long, a source electrode contact hole is too hot is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a chip structure and a manufacturing method thereof, and a vehicle. Background Art

[0002] SiC, a third-generation semiconductor material, boasts wide bandgap, high critical breakdown electric field, and high saturation drift rate, enabling it to operate effectively in extreme scenarios. Among SiC power devices, the SiC MOSFET (Metal Oxide Semiconductor Field Effect Transistor) is a unipolar device. It boasts high input impedance, stable switching speed, and low on-resistance, making it the most popular SiC switching device. It can be used in extreme operating conditions such as high temperature, high voltage, and high frequency, and is widely used in aerospace, industrial control, new energy vehicles, and other fields. During the SiC MOSFET's turn-off process, electrons escape through the source contact. However, if the electron escape path is too long, the energy cannot escape through closer or more distant channels. Consequently, a large number of electrons escape through the source contact at the first cell. Overheating at the source contact can cause failure, impacting device reliability.

[0003] For the above problems, no effective solution has been proposed yet. Summary of the Invention

[0004] The main purpose of the present invention is to provide a chip structure and its manufacturing method and vehicle to solve the problem of overheating of the source contact hole caused by the long energy escape path during the shutdown process of SiC MOSFET chips in the prior art.

[0005] To achieve the above-mentioned objective, according to one aspect of the present invention, a chip structure is provided, comprising: a substrate layer; an N-type drift layer, the N-type drift layer being arranged on the upper surface of the substrate layer, and at least a field oxide layer, a gate oxide layer, a polysilicon gate, and an insulating dielectric layer being stacked on the upper surface of the N-type drift layer, wherein the polysilicon gate is located on an outer layer of the field oxide layer and the gate oxide layer, and the insulating dielectric layer is located on an outer layer of the polysilicon gate, and a cellular structure is formed between the gate oxide layer and an N-type drift region of the N-type drift layer; a first-type source contact hole is provided in the region where the cellular structure is located, the first-type source contact hole being provided from the insulating dielectric layer to the upper surface of the N-type drift layer, a gate contact hole being provided on the insulating dielectric layer, the gate contact hole being provided from the outer side of the insulating dielectric layer through the insulating dielectric layer to the surface of the polysilicon gate; a second-type source contact hole being provided between the gate contact hole and the first-type source contact hole, the second-type source contact hole being provided from the insulating dielectric layer to the upper surface of the N-type drift layer.

[0006] Furthermore, the second type of source contact hole is provided as at least one or more.

[0007] Furthermore, the chip structure also includes a third type of source contact hole, the gate contact hole is arranged between the second type of source contact hole and the third type of source contact hole, and the third type of source contact hole is arranged from the insulating dielectric layer to the upper surface of the N-type drift layer.

[0008] Furthermore, the distance between the second type source contact hole and the first type source contact hole is smaller than the distance between the third type source contact hole close to the terminal region and the first type source contact hole.

[0009] Furthermore, the length of the first type of source contact hole is 0.6-1.2 μm, and / or the length of the second type of source contact hole and the third type of source contact hole is 5-10 μm.

[0010] Furthermore, the cellular structure includes: a Pwell layer, the Pwell layer is located in the N-type drift region of the N-type drift layer, the upper surface of the Pwell layer is flush with the upper surface of the N-type drift layer, and a plurality of Pwell layers are provided; an N+ layer, the N+ layer is located in the Pwell region of each Pwell layer; a partial P+ layer, the partial P+ layer is located in the Pwell region of each Pwell layer and is located outside the N+ layer; a JFET layer, the JFET layer is located in the N-type drift region of the N-type drift layer, and a partial JFET layer is located between the Pwell layers.

[0011] Furthermore, at least a portion of the P+ layer is located within the N-type drift layer, and an upper surface of the P+ layer is flush with an upper surface of the N-type drift layer.

[0012] Furthermore, the field oxide layer is located on the upper surface of part of the P+ layer, the gate oxide layer is located on the upper surface of a preset area of ​​the JFET layer, the N+ layer and the P+ layer, the polysilicon gate is located on the upper surface of the gate oxide layer and the upper surface of part of the field oxide layer, and the insulating dielectric layer is located on the upper surface of the field oxide layer, the polysilicon gate and the JFET layer.

[0013] Furthermore, the doping concentration of the N-type drift layer is 10 14 cm -1 ~10 16 cm -1 .

[0014] Furthermore, the doping concentration of the Pwell layer is 10 16 cm -1 ~10 18 cm -1 , the doping concentration of the N+ layer is 10 19 cm -1 Above, the doping concentration of P+ layer is 10 19 cm -1The JFET layer is N-type SiC, the doping element is N element, and the doping concentration is 10 16 cm -1 ~10 18 cm -1 .

[0015] According to another aspect of the present invention, a method for manufacturing a chip structure is provided, comprising the following steps: providing a substrate, with an N-type drift region and a drain being provided on the front and back sides of the substrate, respectively; performing P-type ion implantation in the N-type drift region to form a plurality of Pwell regions; performing ion implantation in the Pwell region to form an N+ region and a P+ region; performing P-type ion implantation between adjacent Pwell regions to form a JFET region; preparing a field oxide layer by a deposition and then etching process; preparing a gate oxide layer by a thermal oxidation process; preparing a polysilicon gate by a deposition process; preparing an insulating dielectric layer by a deposition process; etching the insulating dielectric layer to obtain a source contact hole and a gate contact hole; and depositing metal to cover the bottom and sidewalls of the source contact hole and the gate contact hole with the metal, thereby forming an ohmic contact at the bottom of the source contact hole and the gate contact hole.

[0016] According to another aspect of the present invention, a vehicle is provided, comprising a chip structure, wherein the chip structure is any one of the above chip structures.

[0017] The technical solution of the present invention significantly shortens the electron escape path by providing a second type of source contact hole between the gate contact hole and the first type of source contact hole in the chip structure. This effectively reduces energy accumulation and overheating caused by an excessively long path, thereby lowering the risk of chip failure and enhancing the overall reliability of the SiC MOSFET chip. This solves the existing problem of source contact hole overheating caused by an excessively long energy escape path during the shutdown process of SiC MOSFET chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which constitute part of this application, are intended to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention and do not constitute an undue limitation of the present invention. In the accompanying drawings:

[0019] Figure 1 A cross-sectional schematic diagram of an embodiment of a conventional chip structure is shown;

[0020] Figure 2 A schematic plan view showing an embodiment of a conventional chip structure;

[0021] Figure 3 A schematic cross-sectional view of an embodiment of a chip structure according to the present invention is shown;

[0022] Figure 4A schematic plan view showing an embodiment of a chip structure according to the present invention is shown;

[0023] Figure 5 A schematic flow chart showing an embodiment of a method for manufacturing a chip structure according to the present invention is shown;

[0024] Figure 6 A diagram illustrating the process of implanting P-type ions into the N-type drift region of a chip structure according to the present invention is shown;

[0025] Figure 7 A diagram illustrating the process of N+ ion implantation of a chip structure according to the present invention is shown;

[0026] Figure 8 A diagram illustrating the process of P+ ion implantation of a chip structure according to the present invention is shown;

[0027] Figure 9 A process diagram illustrating an N-type ion implantation process of a chip structure according to the present invention is shown;

[0028] Figure 10 A diagram illustrating the process of forming a field oxide layer of a chip structure according to the present invention;

[0029] Figure 11 A diagram illustrating a process for forming a gate oxide layer of a chip structure according to the present invention is shown;

[0030] Figure 12 A diagram illustrating a process for forming a crystalline silicon gate electrode of a chip structure according to the present invention is shown;

[0031] Figure 13 A diagram illustrating a process for forming an insulating dielectric layer of a chip structure according to the present invention is shown;

[0032] Figure 14 A diagram illustrating the process of forming a source contact hole and a gate contact hole of a chip structure according to the present invention;

[0033] Figure 15 A diagram illustrating the process of metal deposition formation of a chip structure according to the present invention.

[0034] The above drawings include the following reference numerals:

[0035] 1. Substrate layer;

[0036] 2. N-type drift layer;

[0037] 3. Pwell layer;

[0038] 4. N+ layer;

[0039] 5. P+ layer;

[0040] 6. JFET layer;

[0041] 7. Field oxygen layer;

[0042] 8. Crystalline silicon gate;

[0043] 9. Gate oxide layer;

[0044] 10. Insulating dielectric layer;

[0045] 110. First type source contact hole;

[0046] 111. Second type source contact hole;

[0047] 112. The third type of source contact hole;

[0048] 12. Gate contact hole;

[0049] 13. Metal. DETAILED DESCRIPTION

[0050] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in this application can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0051] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, they indicate the presence of features, steps, operations, devices, components and / or combinations thereof.

[0052] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the terms used in this way are interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0053] Now, exemplary embodiments according to the present application will be described in more detail with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should not be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art. In the accompanying drawings, for the sake of clarity, the thickness of layers and regions may be exaggerated, and the same reference numerals are used to represent the same devices, and thus their descriptions will be omitted.

[0054] Combine Figures 1 to 15 As shown, according to a specific embodiment of the present application, a chip structure is provided.

[0055] Specifically, if Figure 3 As shown, the chip structure includes: a substrate layer 1 and an N-type drift layer 2, the N-type drift layer 2 is arranged on the upper surface of the substrate layer 1, and at least a field oxide layer 7, a gate oxide layer 9, a polysilicon gate 8 and an insulating dielectric layer 10 are stacked on the upper surface of the N-type drift layer 2, wherein the polysilicon gate 8 is located on the outer layer of the field oxide layer 7 and the gate oxide layer 9, and the insulating dielectric layer 10 is located on the outer layer of the polysilicon gate 8, and a cellular structure is formed between the gate oxide layer 9 and the N-type drift region of the N-type drift layer 2; the region where the cellular structure is located is provided with a first type source contact Contact hole 110, a first type of source contact hole 110 is set from the insulating dielectric layer 10 to the upper surface of the N-type drift layer 2, and a gate contact hole 12 is opened on the insulating dielectric layer 10, and the gate contact hole 12 is set from the outside of the insulating dielectric layer 10 through the insulating dielectric layer 10 to the surface of the polysilicon gate 8; wherein, a second type of source contact hole 111 is set between the gate contact hole 12 and the first type of source contact hole 110, and the second type of source contact hole 111 is set from the insulating dielectric layer 10 to the upper surface of the N-type drift layer 2.

[0056] The technical solution of the present invention significantly shortens the electron escape path by providing a second-type source contact hole 111 between the gate contact hole 12 and the first-type source contact hole 110 of the chip structure. This effectively reduces energy accumulation and overheating caused by an excessively long path, thereby lowering the risk of chip failure and enhancing the overall reliability of the SiC MOSFET chip. This solves the existing problem of source contact hole overheating during the shutdown process of SiC MOSFET chips due to an excessively long energy escape path.

[0057] Specifically, at least one or more second-type source contact holes 111 are provided. By increasing the number of second-type source contact holes, the electron escape paths can be further dispersed, improving energy escape efficiency and thereby reducing the risk of local overheating. This improves thermal management of the chip in the off state, enhancing its durability and long-term operational capability.

[0058] Furthermore, the chip structure also includes a third-type source contact hole 112. The gate contact hole 12 is disposed between the second-type source contact hole 111 and the third-type source contact hole 112. The third-type source contact hole 112 extends from the insulating dielectric layer 10 to the upper surface of the N-type drift layer 2. The distance between the second-type source contact hole 111 and the first-type source contact hole 110 is smaller than the distance between the third-type source contact hole 112 and the first-type source contact hole 110 near the terminal region. The principle of this design is based on the optimization of the electron escape path. By adjusting the distance between different types of source contact holes, electrons can escape faster during the shutdown process, reducing the energy retention time within the chip, thereby reducing the risk of overheating.

[0059] like Figure 1 、 Figure 2 The figure shows a traditional chip structure. The traditional chip structure only has a third-type source contact hole 112 and a first-type source contact hole 110. The first-type source contact hole 110 is the source contact hole of the cell area, and the third-type source contact hole 112 is arranged close to the terminal area. The distance between the third-type source contact hole 112 and the first-type source contact hole 110 is too far. When the device switches to the off state, the electrons stored in the transition area overflow through the first-type source contact hole 110. The distance is too far, and overheating may occur at the position of the first-type source contact hole 110, causing cell failure and affecting the reliability of the device.

[0060] like Figure 3 、 Figure 4 The chip structure of the present application is shown. Compared with the traditional chip structure, a second-type source contact hole 111 is set between the gate contact hole 12 and the first-type source contact hole 110. The distance between the second-type source contact hole 111 and the first-type source contact hole 110 is smaller than the distance between the third-type source contact hole 112 near the terminal area and the first-type source contact hole 110. When the device switches to the off state, some electrons stored in the transition area can first overflow through the third-type source contact hole 112 and the second-type source contact hole 111, and the remaining electrons overflow through the first-type source contact hole 110, shortening the energy escape path, reducing overheating caused by leakage current, reducing the probability of chip failure, and improving chip reliability.

[0061] Optionally, metal 13 is deposited in the first type source contact hole 110 , the second type source contact hole 111 , and the third type source contact hole 112 , and the metal 13 serves as an electrode for extracting gate signals and source signals.

[0062] Specifically, the length of the first type source contact hole 110 is 0.6-1.2 μm, and / or the length of the second type source contact hole 111 and the third type source contact hole 112 is 5-10 μm.

[0063] In this embodiment, the first type source contact hole 110 , the second type source contact hole 111 and the third type source contact hole 112 are all strip-shaped contact holes, and the lengths of the first type source contact hole 110 , the second type source contact hole 111 and the third type source contact hole 112 are all set according to actual conditions.

[0064] Furthermore, the cell structure includes: a Pwell layer 3, an N+ layer 4, a partial P+ layer 5 and a JFET layer 6, the Pwell layer 3 is located in the N-type drift region of the N-type drift layer 2, the upper surface of the Pwell layer 3 is flush with the upper surface of the N-type drift layer 2, and multiple Pwell layers 3 are provided; the N+ layer 4 is located in the Pwell region of each Pwell layer 3; the partial P+ layer 5 is located in the Pwell region of each Pwell layer 3 and is located outside the N+ layer 4; the JFET layer 6 is located in the N-type drift region of the N-type drift layer 2, and the partial JFET layer 6 is located between the Pwell layers 3.

[0065] It should be further explained that the P+ layer 5 primarily connects the N+ layer 4 and the Pwell layer 3 to prevent the adverse effects of parasitic transistors. The parasitic transistor effect primarily stems from the potential PNP structure between the Pwell and N+ regions. In the chip structure, the Pwell layer forms a p-type channel, while the N+ layer acts as a current source or sink. In certain circumstances, particularly when SiC MOSFET devices with the aforementioned chip structure operate at high frequencies or high currents, a parasitic PNP transistor structure may form between the Pwell layer, the N+ layer, and the adjacent N-type drift layer. This structure results in additional current gain and an unnecessary conduction path, thereby affecting the device's switching characteristics and stability. The introduction of the P+ layer essentially optimizes the current path, particularly during the transition from on-state to off-state. The high doping concentration of the P+ layer (typically several orders of magnitude higher than that of the Pwell layer) provides a low-impedance channel, allowing electrons from the N+ layer to flow quickly and efficiently through the Pwell layer without being trapped by unnecessary current gain. This optimizes the current path and enhances the device's switching speed and stability.

[0066] Specifically, at least a portion of the P+ layer 5 is located within the N-type drift layer 2, and the upper surface of the P+ layer 5 is flush with the upper surface of the N-type drift layer 2. By maintaining the upper surfaces of the P+ layer 5 and the N-type drift layer 2 at the same level, the electron escape path can be optimized, reducing scattering and delay during the electron escape process, thereby improving the switching speed and efficiency of the chip.

[0067] Under the control of the gate voltage, electrons in the N-type drift region below the JFET region are attracted to the interface of the Pwell region, forming an N-type conductive channel. This channel is the primary path for electrons to travel from the source to the drain. When a positive voltage is applied between the source and drain electrodes, electrons flow from the source region (N+ layer 4) to the drain region through the formed channel. In the on-state, the P+ layer 5 not only serves as a bridge connecting the N+ region and the Pwell region but also plays a role in electron storage. Due to the high doping concentration of the P+ layer, it can attract and store electrons from the N-type drift layer 2. These electrons provide the necessary charge carriers for current transmission during the device's on-state. Meanwhile, the P+ main junction (P+ layer 5 in the transition region) connected to the cell is reverse biased in the on-state and does not significantly affect the flow of electrons. In the on-state, the transition region primarily provides a channel from the cell region to the chip edge, and the electrons stored in the P+ layer 5 do not directly participate in current transmission.

[0068] When the device switches from the on state to the off state, that is, the gate voltage drops below the threshold voltage, the reduction in the gate voltage causes the channel to disappear, cutting off the direct electron channel between the source and the drain. At the moment the device is turned off, the electrons that have entered the channel need to have a certain path to escape to avoid energy accumulation inside the device and causing overheating. At this time, the body diode in the device starts to work, and the freewheeling effect leads the remaining electrons from the drain back to the source. During the shutdown process of the device, electrons mainly escape through the source contact hole. Specifically, in the cell region, electrons mainly escape to the metal source through the first type of source contact hole, while the electrons stored in the P+ layer 5 in the transition region overflow through the first type of source contact hole 110, the second type of source contact hole 111 and the third type of source contact hole 112.

[0069] Specifically, the field oxide layer 7 is located on the upper surface of a portion of the P+ layer 5, the gate oxide layer 9 is located on the upper surface of a predetermined area of ​​the JFET layer 6, the N+ layer 4, and the P+ layer 5, the polysilicon gate 8 is located on the upper surface of the gate oxide layer 9 and the upper surface of a portion of the field oxide layer 7, and the insulating dielectric layer 10 is located on the upper surfaces of the field oxide layer 7, the polysilicon gate 8, and the JFET layer 6. The principle of this stacked structure is to form a stable electric field control environment through the reasonable arrangement of the field oxide layer, gate oxide layer, polysilicon gate, and insulating dielectric layer, ensuring that electrons can escape accurately and efficiently during chip operation, while reducing leakage current and improving device stability and reliability.

[0070] Specifically, the field oxide layer 7 is usually made of silicon dioxide (SiO2) material, and its thickness determines the performance and reliability of the MOSFET device. The presence of the field oxide layer 7 ensures electrical isolation between the gate and the semiconductor, thereby preventing the occurrence of leakage current.

[0071] The polysilicon gate electrode is located above the gate oxide layer 9 of the chip structure. When a positive voltage is applied to the gate, it can attract electrons in the N-type drift region to form an inversion layer, i.e., a channel, at the interface of the Pwell layer, thereby allowing current to flow from the source to the drain. On the contrary, when the gate voltage is zero or negative, the channel disappears, the current path is cut off, and the device enters the off state. The thickness of the crystalline silicon gate electrode is usually selected in the range of several hundred nanometers. Thicker polysilicon will increase the parasitic capacitance between the gate and the semiconductor, affecting the switching speed and high-frequency response of the device. A thickness of several hundred nanometers can provide sufficient thickness for depositing and forming the gate structure while ensuring that the capacitance effect does not significantly reduce the switching performance.

[0072] Gate oxide layer 9 is located on the upper surface of the predetermined region of JFET layer 6, N+ layer 4, and P+ layer 5. Gate oxide layer 9 is typically 50 to 100 nm thick, ensuring good electrical isolation without affecting channel mobility. The presence of gate oxide layer 9 ensures electrical isolation between the gate and the semiconductor, preventing the gate signal from directly penetrating into the semiconductor and thus avoiding leakage current.

[0073] The insulating dielectric layer 10 (usually composed of silicon dioxide SiO2) plays a vital role. It not only isolates the direct contact between the metal layers, but also effectively isolates the electrical connection between the metal and the semiconductor, thereby ensuring stable operation and performance optimization of the device.

[0074] Specifically, the doping concentration of the N-type drift layer 2 is 10 14 cm -1 ~10 16 cm -1 The principle of setting this doping concentration is based on the optimization of SiC material properties. By controlling the doping concentration of the N-type drift layer 2, the on-resistance can be reduced while maintaining the device's voltage resistance, thereby improving the device's switching speed and efficiency.

[0075] Specifically, the doping concentration of the Pwell layer 3 is 10 16 cm -1 ~10 18 cm -1 , the doping concentration of N+ layer 4 is 10 19 cm -1 Above, the doping concentration of P+ layer 5 is 10 19 cm -1 The JFET layer 6 is N-type SiC, the doping element is N element, and the doping concentration is 10 16 cm -1 ~10 18 cm -1 By precisely controlling the doping concentration of each layer, effective current control and optimization of the electron escape path are achieved, while ensuring the stability of the device under high voltage.

[0076] According to another aspect of the present invention, a method for manufacturing a chip structure is provided. Figure 5 As shown, the process includes the following steps: providing a substrate, with an N-type drift region and a drain being provided on the front and back sides of the substrate respectively; performing P-type ion implantation in the N-type drift region to form a plurality of Pwell regions; performing ion implantation in the Pwell region to form an N+ region and a P+ region; performing P-type ion implantation between adjacent Pwell regions to form a JFET region; preparing a field oxide layer by a deposition and then etching process; preparing a gate oxide layer by a thermal oxidation process; preparing a polysilicon gate by a deposition process; preparing an insulating dielectric layer by a deposition process; etching the insulating dielectric layer to obtain a source contact hole and a gate contact hole; depositing metal to cover the bottom and sidewalls of the source contact hole and the gate contact hole with the metal, thereby forming an ohmic contact at the bottom of the source contact hole and the gate contact hole.

[0077] like Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 As described above, the Pwell region, the N+ region, the P+ region and the JFET region are formed by implanting various ions into the N-type drift region.

[0078] It's important to further clarify that before the field oxide layer is formed through a deposition-and-etch process, the implanted ions are activated through a high-temperature annealing process at a temperature of 1500°C to 1700°C. Ion implantation is a commonly used doping technique that accelerates ions to the SiC wafer surface and then embeds them into the crystal lattice to form the desired doped regions. However, during the ion implantation process, the high-speed implanted ions can cause lattice damage in the material, forming point defects and dislocations, which is known as "implantation damage." High-temperature heating increases the atoms' mobility, allowing them to rearrange themselves, repairing the damage caused by the implantation and activating the doped ions, enabling them to effectively participate in the electrical conduction process. Activating the ions means transitioning them from a trapped state in the crystal lattice to an electrically active state, thereby forming P-type or N-type doped regions. The annealing process is typically performed in an inert atmosphere, such as argon or nitrogen, to prevent oxidation or other unwanted chemical reactions.

[0079] Ion implantation often leaves tiny holes or damaged areas on the upper surface of the N-type drift layer 2. These surface defects also need to be repaired, otherwise they will reduce device performance and reliability. Before annealing, a sacrificial oxide layer is sometimes used to remove these surface defects.

[0080] Specifically, if Figure 10As shown, in this embodiment, the field oxide layer is typically deposited using chemical vapor deposition (CVD) or physical vapor deposition (PVD) technology. Precursor gases (such as silicon tetrachloride SiCl4 and oxygen O2) react at high temperature to form silicon dioxide (SiO2) and deposit on the upper surface of the N-type drift layer 2. During the deposition process, parameters such as temperature, pressure, and gas flow rate need to be precisely controlled to ensure the uniformity and appropriate thickness (usually several hundred nanometers) of the field oxide layer. As the deposition process proceeds, SiO2 molecules form a thin film on the SiC surface, gradually thickening to the desired thickness. After deposition is completed, a photolithography mask needs to be formed on the field oxide layer to protect areas that should not be etched. The precise pattern of the photolithography mask will determine the final structure of the field oxide layer and ensure the correct position of the gate contact hole and the source contact hole. The SiO2 areas not covered by the mask are removed by dry etching (such as plasma etching) or wet etching (such as using a chemical solution).

[0081] like Figure 11 As shown, the gate oxide layer 9 is prepared by a thermal oxidation process. Thermal oxidation is a process in which the semiconductor material (in the chip structure, usually on the upper surface of the JFET region and part of the N+ region) is placed in a high temperature environment to react with oxygen or water vapor to form a thin oxide film on the surface.

[0082] like Figure 12 As shown, the polysilicon gate 8 is usually made by chemical vapor deposition (CVD). During the deposition process, a silicon source (such as silicon tetrachloride SiCl4 or silane SiH4) is introduced into the reaction chamber together with a carrier gas (such as hydrogen H2 or nitrogen N2) under high temperature and specific pressure conditions. The silicon source decomposes and deposits as polysilicon on the surface of the gate oxide layer 9 and part of the field oxide layer 7. The deposition temperature is generally controlled between 600°C and 700°C to promote the formation of high-quality polysilicon. The role of the polysilicon gate 8 in the chip structure is to act as a gate electrode to receive and control the external gate voltage. Changes in the gate voltage can change the electric field between the polysilicon and the channel below, thereby controlling the conductive state of the channel. When the gate voltage is higher than a certain threshold, the channel is formed and the device is turned on; when the gate voltage is lower than the threshold, the channel disappears and the device is turned off.

[0083] like Figure 13 As shown, the insulating dielectric layer, usually silicon dioxide (SiO2), is deposited by techniques such as chemical vapor deposition (CVD) or physical vapor deposition (PVD). The deposited insulating dielectric layer may not be completely flat, and steps such as chemical mechanical polishing (CMP) are required to achieve surface flatness.

[0084] like Figure 14As shown, a layer of photoresist is deposited on the insulating dielectric layer. Then, through ultraviolet exposure and development, the desired pattern is transferred to the photoresist to protect the insulating dielectric portion to be retained from being etched. Next, an etching process is used to remove the insulating dielectric layer not covered by the photolithography mask to form source contact holes and gate contact holes. The source contact hole formed by etching penetrates the insulating dielectric layer and directly contacts the upper surface of the N-type drift layer 2, allowing the source metal to form an ohmic contact with the semiconductor material and lead to the source signal. Similarly, the gate contact hole penetrates the insulating dielectric layer and contacts the polysilicon gate, allowing the gate metal to form a good electrical connection with the polysilicon and control the gate signal.

[0085] like Figure 15 As shown, metal deposition first involves selecting a suitable metal material. In this embodiment, aluminum material is selected as the deposited metal, and the metal material is deposited on the formed source contact hole and gate contact hole by evaporation or sputtering process. Metal deposition must ensure complete coverage of the bottom and sidewalls of the contact hole and fill all pores to form a continuous metal layer. Any pores not covered by metal may cause poor contact, affecting the performance and reliability of the device. Once the metal deposition is completed, a so-called ohmic contact is formed at the bottom of the source contact hole and the gate contact hole. Ohmic contact is a low-resistance metal-semiconductor contact that allows current to flow freely between the metal and the semiconductor without significantly affecting the voltage drop.

[0086] The primary function of deposited metal is to conduct source and gate signals from the inside to the outside, a prerequisite for the device to connect and function with other circuit components. The formation of ohmic contact significantly reduces the contact resistance between the metal and the semiconductor, allowing current to flow through the source and gate with minimal loss, improving the device's overall conductivity.

[0087] From the above description, it can be seen that the above embodiments of the present invention achieve the following technical effects:

[0088] During the shutdown process, electrons escape through the source contact hole at the main junction. However, if the electron escape path is too long, the corresponding energy cannot escape in a closer channel. A large number of electrons escape through the first type of source contact hole at the cell. At this time, overheating may occur at the source contact hole position, causing failure, affecting the reliability of the device. By optimizing the chip structure and layout design, a second type of source contact hole is added between the transition zone gate contact hole and the first type of source contact hole (according to the distance estimation, the number of second type source contact holes does not need to be fixed), shortening the electron escape path, avoiding leakage current overheating and causing chip failure, and improving the reliability of the chip structure.

[0089] The above embodiments can also be used in the field of equipment technology. That is, according to another aspect of the present invention, a vehicle is provided, including a chip structure, which is the chip structure of any one of the above embodiments.

[0090] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship of a device or feature to other devices or features as shown in the figures. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figures. For example, if the device in the drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0091] In addition to the above, it should be noted that references to "one embodiment," "another embodiment," "an embodiment," and the like in this specification refer to specific features, structures, or characteristics described in conjunction with that embodiment as included in at least one embodiment generally described in this application. The appearance of the same expression in multiple places in the specification does not necessarily refer to the same embodiment. Furthermore, when a specific feature, structure, or characteristic is described in conjunction with any embodiment, it is intended that such feature, structure, or characteristic, when implemented in conjunction with other embodiments, also falls within the scope of the present invention.

[0092] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0093] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. A chip structure, characterized in that: include: substrate layer (1); An N-type drift layer (2) is provided on the upper surface of the substrate layer (1). The upper surface of the N-type drift layer (2) is at least stacked with a field oxide layer (7), a gate oxide layer (9), a polysilicon gate (8), and an insulating dielectric layer (10), wherein the polysilicon gate (8) is located on the outer layer of the field oxide layer (7) and the gate oxide layer (9), the insulating dielectric layer (10) is located on the outer layer of the polysilicon gate (8), and a cellular structure is formed between the gate oxide layer (9) and the N-type drift region of the N-type drift layer (2); A first type of source contact hole (110) is provided in the region where the cell structure is located, and the first type of source contact hole (110) is provided from the insulating dielectric layer (10) to the upper surface of the N-type drift layer (2), and a gate contact hole (12) is provided on the insulating dielectric layer (10), and the gate contact hole (12) is provided from the outer side of the insulating dielectric layer (10) through the insulating dielectric layer (10) to the surface of the polysilicon gate (8); wherein a second type of source contact hole (111) is provided between the gate contact hole (12) and the first type of source contact hole (110), and the second type of source contact hole (111) is provided from the insulating dielectric layer (10) to the upper surface of the N-type drift layer (2).

2. The chip structure according to claim 1, characterized in that: The second type of source contact hole (111) is at least provided as one or more.

3. The chip structure according to claim 1, wherein: The chip structure further comprises a third type of source contact hole (112), the gate contact hole (12) being arranged between the second type of source contact hole (111) and the third type of source contact hole (112), and the third type of source contact hole (112) being arranged from the insulating dielectric layer (10) through to the upper surface of the N-type drift layer (2).

4. The chip structure according to claim 3, characterized in that: The distance between the second type source contact hole (111) and the first type source contact hole (110) is smaller than the distance between the third type source contact hole (112) close to the terminal region and the first type source contact hole (110).

5. The chip structure according to claim 4, characterized in that: The length of the first type source contact hole (110) is 0.6-1.2 μm, and / or the length of the second type source contact hole (111) and the third type source contact hole (112) is 5-10 μm.

6. The chip structure according to claim 3, characterized in that: The cellular structure comprises: A Pwell layer (3), the Pwell layer (3) being located in the N-type drift region of the N-type drift layer (2), the upper surface of the Pwell layer (3) being flush with the upper surface of the N-type drift layer (2), and a plurality of Pwell layers (3) being provided; An N+ layer (4), the N+ layer (4) being located in a Pwell region of each of the Pwell layers (3); A portion of the P+ layer (5), wherein a portion of the P+ layer (5) is located in the Pwell region of each of the Pwell layers (3) and is located outside the N+ layer (4); A JFET layer (6), the JFET layer (6) is located in the N-type drift region of the N-type drift layer (2), and part of the JFET layer (6) is located between the Pwell layers (3).

7. The chip structure according to claim 6, characterized in that: At least a portion of the P+ layer (5) is located within the N-type drift layer (2), and the upper surface of the P+ layer (5) is flush with the upper surface of the N-type drift layer (2).

8. The chip structure according to claim 6, characterized in that: The field oxide layer (7) is located on a portion of the upper surface of the P+ layer (5); the gate oxide layer (9) is located on the upper surfaces of a preset area of ​​the JFET layer (6), the N+ layer (4), and the P+ layer (5); the polysilicon gate (8) is located on the upper surface of the gate oxide layer (9) and a portion of the upper surface of the field oxide layer (7); and the insulating dielectric layer (10) is located on the upper surfaces of the field oxide layer (7), the polysilicon gate (8), and the JFET layer (6).

9. The chip structure according to claim 1, wherein: The doping concentration of the N-type drift layer (2) is 10 14 cm -1 ~10 16 cm -1 .

10. The chip structure according to claim 6, characterized in that: The doping concentration of the Pwell layer (3) is 10 16 cm -1 ~10 18 cm -1 The doping concentration of the N+ layer (4) is 10 19 cm -1 Above, the doping concentration of the P+ layer (5) is 10 19 cm -1 The JFET layer (6) is N-type SiC, the doping element is N element, and the doping concentration is 10 16 cm -1 ~10 18 cm -1 .

11. A method for manufacturing a chip structure according to any one of claims 1 to 10, characterized in that: The steps include: Providing a substrate, wherein an N-type drift region and a drain are respectively provided on the front side and the back side of the substrate; Performing P-type ion implantation in the N-type drift region to form multiple Pwell regions; Ion implantation is performed in the Pwell region to form an N+ region and a P+ region; P-type ion implantation is performed between adjacent Pwell regions to form a JFET region; Prepare a field oxide layer by a deposition and then etching process; preparing a gate oxide layer by a thermal oxidation process; preparing a polysilicon gate by a deposition process; preparing an insulating dielectric layer by a deposition process; Etching the insulating dielectric layer to obtain a source contact hole and a gate contact hole; Metal is deposited to cover the bottom and sidewalls of the source contact hole and the gate contact hole, thereby forming ohmic contacts at the bottoms of the source contact hole and the gate contact hole.

12. A vehicle comprising a chip structure, characterized in that: The chip structure is the chip structure according to any one of claims 1 to 10.

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