Detector and manufacturing method thereof

Abstract

The invention provides a detector and a manufacturing method thereof, the detector comprises a detector array chip, an indium column array and a reading circuit, the detector array chip comprises a first corrosion cut-off layer, a second corrosion cut-off layer, an NPN transistor array, an emitter region contact layer and an electrode layer; by adopting the NPN transistor array structure, high-gain optical signal detection under low working voltage can be realized, by arranging the first corrosion cut-off layer and the second corrosion cut-off layer, the first corrosion cut-off layer can be used as a stop layer for etching and removing the substrate, and the second corrosion cut-off layer can be used as a stop layer for etching and removing the substrate. The second corrosion cut-off layer can be used as a stop layer for etching and removing the film layer close to one side of the emitter region contact layer, so that the substrate can be removed, high absorption of a non-absorption region to visible light is avoided, and high-sensitivity detection in a wide spectrum range from visible light to short wave infrared is realized.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a detector and a manufacturing method thereof. Background Art

[0002] Infrared detectors enable highly sensitive, high-response spectral detection and are widely used in fields such as security monitoring, spectral analysis, and industrial detection. Existing PIN-structured InGaAs focal plane detectors suffer from a lack of gain and low sensitivity. Gain-type avalanche photodiode (APD)-structured InGaAs focal plane detectors also suffer from high power consumption and high avalanche noise. Furthermore, the InP substrate causes additional losses in the visible light band, impacting device performance. Therefore, there is an urgent need for a high-gain, low-power, and wide-spectrum detector. Summary of the Invention

[0003] In view of the above problems, the present invention provides a high-gain, low-power, wide-spectrum detector and a method for manufacturing the same.

[0004] According to a first aspect of the present invention, a detector is provided, comprising a detector array chip, an indium column array and a readout circuit, wherein the detector array chip is connected to the readout circuit via the indium column array, and the detector array chip comprises a first corrosion cutoff layer, a second corrosion cutoff layer, an NPN transistor array, an emitter contact layer and an electrode layer; the first corrosion cutoff layer is located on a side of the indium column array away from the readout circuit; the second corrosion cutoff layer is located on a side of the first corrosion cutoff layer close to the indium column array; the NPN transistor array is located on a side of the second corrosion cutoff layer close to the indium column array; the emitter contact layer is located on a side of the NPN transistor array close to the indium column array; and the electrode layer connects the emitter contact layer and the indium column array.

[0005] According to an embodiment of the present invention, the NPN transistor array includes a first N-electrode layer, a P-electrode layer and a second N-electrode layer; the first N-electrode layer is located between the second corrosion stop layer and the emitter contact layer; the P-electrode layer is located between the first N-electrode layer and the emitter contact layer; and the second N-electrode layer is located between the P-electrode layer and the emitter contact layer.

[0006] According to an embodiment of the present invention, the detector array chip further includes a first transition layer, and the first transition layer is located between the second corrosion stop layer and the first N-electrode layer.

[0007] According to an embodiment of the present invention, the detector array chip further includes a second transition layer and a third transition layer, wherein the second transition layer is located between the P electrode layer and the second N electrode layer, and the third transition layer is located between the second N electrode layer and the emitter contact layer.

[0008] According to an embodiment of the present invention, the detector array chip further comprises a contact hole, which extends from the emitter region contact layer to a surface of the second corrosion stop layer on a side away from the first corrosion stop layer; the electrode layer comprises an array electrode and a common electrode, the array electrode connecting the emitter region contact layer and the corresponding indium column in the indium column array, and the common electrode connecting the second corrosion stop layer and the corresponding indium column in the indium column array through the contact hole.

[0009] According to an embodiment of the present invention, the thickness of the first corrosion stop layer is greater than or equal to 0.05 micrometers and less than or equal to 0.5 micrometers; the doping type of the first corrosion stop layer is N-type doping, and the doping concentration of the first corrosion stop layer is greater than or equal to 1×10 17 per cubic centimeter and less than or equal to 2×10 19 per cubic centimeter.

[0010] According to an embodiment of the present invention, the thickness of the second corrosion stop layer is greater than or equal to 0.02 micrometers and less than or equal to 0.2 micrometers; the doping type of the second corrosion stop layer is N-type doping, and the doping concentration of the second corrosion stop layer is greater than or equal to 1×10 17 per cubic centimeter and less than or equal to 2×10 19 per cubic centimeter.

[0011] According to a second aspect of the present invention, there is provided a method for manufacturing a detector, comprising:

[0012] forming a detector array chip;

[0013] preparing indium column arrays on the detector array chip and the readout circuit respectively;

[0014] Connecting the detector array chip and the readout circuit via the indium column array;

[0015] Wherein, forming the detector array chip comprises:

[0016] forming a first corrosion stop layer;

[0017] forming a second etch stop layer on the first etch stop layer;

[0018] forming an NPN transistor array on the second etching stop layer;

[0019] forming an emitter contact layer on the NPN transistor array;

[0020] An electrode layer is formed on the emitter contact layer, wherein the electrode layer connects the emitter contact layer and the indium column array.

[0021] According to an embodiment of the present invention, before forming the first corrosion stop layer, the manufacturing method further includes:

[0022] forming a buffer layer on the substrate;

[0023] The forming of the first corrosion stop layer comprises:

[0024] forming a first corrosion stop layer on a surface of the buffer layer away from the substrate;

[0025] After connecting the detector array chip and the readout circuit via the indium pillar array, the manufacturing method further includes:

[0026] The substrate and the buffer layer are removed.

[0027] According to an embodiment of the present invention, the electrode layer includes an array electrode and a common electrode, and forming the electrode layer on the emitter region contact layer includes:

[0028] forming an array electrode on the emitter region contact layer, wherein the array electrode connects the emitter region contact layer and corresponding indium pillars in the indium pillar array;

[0029] forming a contact hole, wherein the contact hole extends from the emitter region contact layer to a surface of the second etching stop layer away from the first etching stop layer;

[0030] A common electrode is formed on the emitter region contact layer, and the common electrode is connected to the second etching stop layer and the corresponding indium pillars in the indium pillar array through the contact hole.

[0031] Beneficial effects of the present invention: The detector provided by the present invention includes a detector array chip, an indium column array and a readout circuit. The detector array chip is connected to the readout circuit through the indium column array. The detector array chip includes a first corrosion cutoff layer, a second corrosion cutoff layer, an NPN transistor array, an emitter contact layer and an electrode layer; the first corrosion cutoff layer is located on the side of the indium column array away from the readout circuit; the second corrosion cutoff layer is located on the side of the first corrosion cutoff layer close to the indium column array; the NPN transistor array is located on the side of the second corrosion cutoff layer close to the indium column array; the emitter contact layer is located on the side of the NPN transistor array close to the indium column array; the electrode layer connects the emitter contact layer and the indium column array; the embodiment of the present invention adopts an NPN transistor array structure to achieve high-gain optical signal detection at a low operating voltage. By setting the first corrosion cutoff layer and the second corrosion cutoff layer, the first corrosion cutoff layer can be used as a stop layer for etching and removing the substrate, and the second corrosion cutoff layer can be used as a stop layer for etching and removing the film layer close to the emitter contact layer, thereby removing the substrate and avoiding high absorption of visible light by the non-absorption region, thereby achieving high-sensitivity detection in a wide spectral range from visible light to short-wave infrared. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0033] Figure 1 A schematic diagram of the structure of a detector according to an embodiment of the present invention is shown;

[0034] Figure 2 A flowchart schematically illustrates a method for manufacturing a detector according to an embodiment of the present invention;

[0035] Figure 3 A flowchart schematically illustrates a method for manufacturing a detector array chip according to an embodiment of the present invention;

[0036] Figure 4 The figure schematically shows the epitaxial structure of a detector according to an embodiment of the present invention. DETAILED DESCRIPTION

[0037] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to specific embodiments and the accompanying drawings. It is apparent that the embodiments described are only a portion of the embodiments of the present invention, not all of them. All other embodiments derived by persons of ordinary skill in the art based on the embodiments of the present invention without creative effort are intended to fall within the scope of protection of the present invention.

[0038] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0039] In the present invention, unless otherwise expressly specified or limited, the terms "mounted," "connected," "connect," "fixed," etc. should be understood in a broad sense. For example, they may refer to fixed connection, detachable connection, or integration; mechanical connection, electrical connection, or mutual communication; direct connection or indirect connection through an intermediate medium; internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0040] In the description of the present invention, it should be understood that the terms "longitudinal", "length", "circumferential", "front", "rear", "left", "right", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the subsystem or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0041] Throughout the drawings, identical elements are represented by identical or similar reference numerals. Conventional structures or configurations may be omitted where they may obscure the understanding of the present invention. Furthermore, the shapes, sizes, and positional relationships of the components in the drawings do not reflect actual size, proportion, or actual positional relationships. Furthermore, any reference symbols between parentheses in the present invention should not be construed as limiting the present invention.

[0042] Similarly, in order to streamline the present invention and aid in understanding one or more of the various disclosed aspects, in the above description of exemplary embodiments of the present invention, the various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. Descriptions with reference to the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples" and the like mean that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0043] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the technical features being referred to. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means at least two, such as two or three, unless otherwise specifically defined.

[0044] like Figure 1 As shown, it is a structural schematic diagram of a detector according to an embodiment of the present invention, wherein the detector includes a detector array chip 10, an indium column array 20 and a readout circuit 30, wherein the detector array chip 10 is connected to the readout circuit 30 through the indium column array 20, and the detector array chip 10 includes a first corrosion stop layer 3, a second corrosion stop layer 4, an NPN transistor array 100, an emitter contact layer 11 and an electrode layer 13; the first corrosion stop layer 3 is located on a side of the indium column array 20 away from the readout circuit 30; the second corrosion stop layer 4 is located on a side of the first corrosion stop layer 3 close to the indium column array 20; the NPN transistor array 100 is located on a side of the second corrosion stop layer 4 close to the indium column array 20; the emitter contact layer 11 is located on a side of the NPN transistor array 100 close to the indium column array 20; and the electrode layer 13 connects the emitter contact layer 11 and the indium column array 20.

[0045] It should be noted that the detector can operate in a back-illuminated manner. The detector array chip 10 is provided with an indium column array 20, and the readout circuit 30 is also provided with an indium column array 20. The indium column array 20 includes a plurality of indium columns 201. The indium column array 20 on the detector array chip 10 and the indium column array 20 on the readout circuit 30 are correspondingly welded. Except for the indium column array 20, the gap between the detector array chip 10 and the readout circuit 30 is filled with resin 14. In some embodiments, the readout circuit 30 can be a Si-based readout circuit.

[0046] It is understood that the embodiment of the present invention can achieve high-gain optical signal detection at a low operating voltage by adopting the NPN transistor array 100 structure. By providing the first etching stop layer 3 and the second etching stop layer 4, the first etching stop layer 3 can be used as an etching removal substrate 1 (such as Figure 4 ) is formed as a stop layer, and the second corrosion stop layer 4 can be used as a stop layer for etching away the film layer on the side close to the emission region contact layer 11, thereby being able to remove the substrate 1 and avoid high absorption of visible light (400nm-900nm) in the non-absorption region, thereby achieving high-sensitivity detection in a wide spectral range from visible light to short-wave infrared, and having great application prospects in the fields of low-light-level night vision, security monitoring, detection imaging, etc.

[0047] In some embodiments, the material of the first corrosion stop layer 3 is, for example, In 0.53 Ga 0.47 As; the thickness of the first corrosion stop layer 3 is greater than or equal to 0.05 microns and less than or equal to 0.5 microns, for example, 0.1 microns; the doping type of the first corrosion stop layer 3 is N-type doping, and the doping concentration of the first corrosion stop layer 3 is greater than or equal to 1×10 17 per cubic centimeter and less than or equal to 2×10 19 per cubic centimeter, for example, 1×10 18 per cubic centimeter.

[0048] In some embodiments, the material of the second corrosion stop layer 4 is, for example, InGaAsP, and the thickness of the second corrosion stop layer 4 is greater than or equal to 0.02 microns and less than or equal to 0.2 microns, for example, 0.05 microns; the doping type of the second corrosion stop layer 4 is N-type doping, and the doping concentration of the second corrosion stop layer 4 is greater than or equal to 1×10 17 per cubic centimeter and less than or equal to 2×10 19 per cubic centimeter, for example, 1×10 18 per cubic centimeter.

[0049] In some embodiments, the NPN transistor array 100 includes a first N-electrode layer 6 (collection region), a P-electrode layer 7 (base region) and a second N-electrode layer 9 (emitter region); the first N-electrode layer 6 is located between the second corrosion stop layer 4 and the emitter region contact layer 11; the P-electrode layer 7 is located between the first N-electrode layer 6 and the emitter region contact layer 11; and the second N-electrode layer 9 is located between the P-electrode layer 7 and the emitter region contact layer 11.

[0050] In some embodiments, the material of the first N-electrode layer 6 is, for example, In 0.53 Ga 0.47 As, the thickness of the first N-electrode layer 6 is, for example, 1.5 microns, and the doping concentration of the first N-electrode layer 6 is, for example, 1×10 15 Per cubic centimeter. The material of the P electrode layer 7 is, for example, In 0.53 Ga 0.47 As, the thickness of the P electrode layer 7 is, for example, 0.1 micrometers, and the doping concentration of the P electrode layer 7 is, for example, 2×10 17 The material of the second N-electrode layer 9 is, for example, InP, the thickness of the second N-electrode layer 9 is, for example, 0.2 microns, and the doping concentration of the second N-electrode layer 9 is, for example, 1×10 16 per cubic centimeter.

[0051] In some embodiments, the material of the emitter contact layer 11 is, for example, In 0.53 Ga 0.47 As, the thickness of the emitter contact layer 11 is, for example, 0.3 μm, the doping type of the emitter contact layer 11 is N-type, and the doping concentration of the emitter contact layer 11 is, for example, 1×10 19 per cubic centimeter.

[0052] In some embodiments, the detector array chip 10 further includes a first transition layer 5, which is located between the second corrosion stop layer 4 and the first N electrode layer 6. The material of the first transition layer 5 is, for example, In 0.53 Ga 0.47 As, the thickness of the first transition layer 5 is, for example, 0.05 μm. In this embodiment, by arranging the first transition layer 5 between the second corrosion stop layer 4 and the first N-electrode layer 6, it can play a role in doping concentration transition, so that the concentration of N-type impurities increases from 1×10 18 per cubic centimeter to 1×10 15 per cubic centimeter.

[0053] In some embodiments, the detector array chip 10 further includes a second transition layer 8 and a third transition layer 10. The second transition layer 8 is located between the P electrode layer 7 and the second N electrode layer 9, and the third transition layer 10 is located between the second N electrode layer 9 and the emitter contact layer 11. The second transition layer 8 is made of, for example, intrinsic InGaAsP, and has a thickness of, for example, 0.025 microns. The third transition layer 10 is made of, for example, InGaAsP with an N-type doping type, and has a thickness of, for example, 0.045 microns. In this embodiment, the second transition layer 8 and the third transition layer 10 are disposed on both sides of the second N electrode layer 9, primarily serving as energy band transitions and serving as InGaAsP. 0.53 Ga 0.47 Energy band transition between different materials such as As and InP.

[0054] In some embodiments, the detector array chip 10 further includes a contact hole 103, which extends from the emitter contact layer 11 to a surface of the second corrosion stop layer 4 on a side away from the first corrosion stop layer 3; the electrode layer 13 includes an array electrode 131 and a common electrode 132, the array electrode 131 connects the emitter contact layer 11 and the corresponding indium column 201 in the indium column array 20, and the common electrode 132 connects the second corrosion stop layer 4 and the corresponding indium column 201 in the indium column array 20 through the contact hole 103.

[0055] It should be noted that the material of the electrode layer 13 can be any one of Ti, Pt, and Au, and the present invention is not limited thereto. The array electrode 131 is connected to the second N-electrode 9 (emitter region) via the emitter region contact layer 11, and the common electrode 132 is connected to the first N-electrode layer 6 (collector region) via the second etching stop layer 4, thereby achieving conduction between the NPN transistor array 100 and the readout circuit 30 to read the electrical signal converted from the optical signal.

[0056] Next, see Figure 2 and Figure 3 , are respectively a flow chart of a method for manufacturing a detector according to an embodiment of the present invention and a flow chart of a method for manufacturing a detector array chip according to an embodiment of the present invention, wherein the method for manufacturing the detector comprises:

[0057] S1, forming a detector array chip;

[0058] S2, preparing indium column arrays on the detector array chip and readout circuit respectively;

[0059] S3. Connecting the detector array chip and the readout circuit via the indium column array.

[0060] Wherein, the step S1, forming a detector array chip, includes:

[0061] S101, forming a first corrosion stop layer;

[0062] S102, forming a second corrosion stop layer on the first corrosion stop layer;

[0063] S103, forming an NPN transistor array on the second etching stop layer;

[0064] S104, forming an emitter contact layer on the NPN transistor array;

[0065] S105 , forming an electrode layer on the emitter region contact layer, wherein the electrode layer connects the emitter region contact layer and the indium column array.

[0066] It can be understood that the detector manufactured using the detector manufacturing method provided by the embodiment of the present invention adopts an NPN transistor array structure, which can achieve high-gain optical signal detection at a low operating voltage. By preparing a first corrosion stop layer and a second corrosion stop layer, the first corrosion stop layer can be used as a stop layer for etching and removing the substrate, and the second corrosion stop layer can be used as a stop layer for etching and removing the film layer on the side of the contact layer close to the emission area, thereby removing the substrate and avoiding high absorption of visible light (400nm-900nm) in the non-absorption area, thereby achieving high-sensitivity detection in a wide spectral range from visible light to short-wave infrared.

[0067] In some embodiments, before forming the first corrosion stop layer, the manufacturing method further includes:

[0068] forming a buffer layer on the substrate;

[0069] The forming of the first corrosion stop layer comprises:

[0070] forming a first corrosion stop layer on a surface of the buffer layer away from the substrate;

[0071] After connecting the detector array chip and the readout circuit via the indium pillar array, the manufacturing method further includes:

[0072] The substrate and the buffer layer are removed.

[0073] It can be understood that during the manufacturing process of the detector provided in this embodiment, it is necessary to first make a substrate and a buffer layer, and then make a first corrosion cutoff layer on the buffer layer. After the detector array chip and the readout circuit are flip-chip soldered, the substrate and buffer layer are removed to avoid the substrate and buffer layer from absorbing visible light.

[0074] In some embodiments, the electrode layer includes an array electrode and a common electrode, and forming the electrode layer on the emitter region contact layer includes:

[0075] forming an array electrode on the emitter region contact layer, wherein the array electrode connects the emitter region contact layer and corresponding indium pillars in the indium pillar array;

[0076] forming a contact hole, wherein the contact hole extends from the emitter region contact layer to a surface of the second etching stop layer away from the first etching stop layer;

[0077] A common electrode is formed on the emitter region contact layer, and the common electrode is connected to the second etching stop layer and the corresponding indium pillars in the indium pillar array through the contact hole.

[0078] It should be noted that during the manufacturing process of the detector provided in this embodiment, the epitaxial structure of the detector needs to be manufactured first. For details, please refer to Figure 4 , is a schematic diagram of the epitaxial structure of a detector according to an embodiment of the present invention. First, a buffer layer 2 is prepared on a substrate 1. The buffer layer 2 is used to block impurities and defects in the substrate 1 to avoid affecting the quality of the epitaxial structure. The material of the substrate 1 is, for example, InP, the material of the buffer layer 2 is, for example, InP, the thickness of the buffer layer 2 is, for example, 0.5 microns, the doping type of the buffer layer 2 is N-type, and the doping concentration of the buffer layer 2 is, for example, 2×10 18 per cubic centimeter.

[0079] Since the InP substrate 1 and the InP buffer layer 2 will cause a large amount of signal loss in the wavelength range of 400nm-900nm when incident from the back, it is necessary to completely remove the substrate 1 and the buffer layer 2. In this embodiment, a 0.1 micron thick and 1×10 18 N-type In per cubic centimeter 0.53 Ga 0.47 As first corrosion stop layer 3, a layer with a thickness of 0.05 μm and a doping concentration of 1×10 18 The N-type InGaAsP second etching stop layer 4 is formed per cubic centimeter, wherein the first etching stop layer 3 is used as a stop layer for removing the back InP substrate 1 and the InP buffer layer 2 by a wet etching process, and the second etching stop layer 4 is used as a stop layer for removing the film layer located on the surface of the second etching stop layer 4 on the front side by a wet etching process, thereby being able to remove the substrate 1 and the buffer layer 2, avoiding loss caused by absorption of visible light, and improving device performance. The second etching stop layer 4 is also used as a contact layer for the collection area, ensuring the contact stability of the collection area electrode, and there is no back photolithography process, which reduces the process difficulty.

[0080] Then, an In layer with a thickness of 0.05 μm is prepared on the second etching stop layer 4. 0.53 Ga 0.47 As first transition layer 5, to achieve the doping concentration transition between the second etching stop layer 4 and the first N electrode layer 6. Then prepare a 1.5 μm thick and 1×10 15 per cubic centimeter of the first N-electrode layer 6 (In 0.53 Ga 0.47 As) as the collection area. Then, a 0.1 μm thick and 2×10 17 Each cubic centimeter of the P electrode layer 7 (In 0.53 Ga 0.47 As) as the base region.

[0081] Next, a second transition layer 8 (intrinsic InGaAsP) with a thickness of 0.025 μm is prepared on the P electrode layer 7, and then a second transition layer 8 with a thickness of 0.2 μm and a doping concentration of 1×10 16 The second N electrode layer 9 (InP) per cubic centimeter is used as the emitter region. Then, a 0.045 micron thick and 1×10 16 The third transition layer 10 (N-type InGaAsP) is prepared per cubic centimeter. Finally, a 0.3 micron thick and 1×10 doping concentration is prepared on the third transition layer 10. 19 per cubic centimeter of emitter contact layer 11 (N-type In 0.53 Ga 0.47As), at this point, the epitaxial structure of the detector is completed. Among them, the second transition layer 8 and the third transition layer 10 are used to adjust the quaternary material components to achieve energy band transition.

[0082] It should be noted that after the epitaxial structure is manufactured, the epitaxial structure needs to be etched to form the NPN transistor array 100. Figure 4 and Figure 1 First, standard photolithography and inductive plasma etching (ICP) methods are used to Figure 4 A plurality of first via holes 101 are etched on the epitaxial structure, with an etching depth of, for example, 0.675 microns, from the emitter contact layer 11 to the surface of the first N-electrode layer 6 on one side close to the P-electrode layer 7; then, standard photolithography and inductive plasma etching (ICP) methods are used to etch second via holes 102 on the basis of the first via holes 101, that is, the second via holes 102 are connected to the first via holes 101, and the etching depth of the second via holes 102 is, for example, 1.5 microns. The second via holes 102 penetrate the first N-electrode layer 6, thereby obtaining an NPN transistor array 100.

[0083] Next, the array electrode 131 and common electrode 132 are fabricated separately. Benzocyclobutene 12 (BCB) is first deposited on the emitter contact layer 11. The BCB fills the second via 102 and the first via 101. Excess BCB is then etched away until the emitter contact layer 11 is exposed, achieving planarization. Ti / Pt / Au is then deposited on the emitter contact layer 11 corresponding to the NPN transistor array 100 using electron beam evaporation to form the array electrode 131. Then, a dry etching process is used to form a portion of the contact hole 103 around the array electrode 131. The depth of the portion of the contact hole 103 is, for example, 2.175 microns, that is, etching from the emitter contact layer 11 to the surface of the first transition layer 5 close to the first N-electrode layer 6. Then, a wet etching process is used to remove the first transition layer 5 to form a complete contact hole 103, so that the contact hole 103 extends from the emitter contact layer 11 to the surface of the second etching stop layer 4 away from the first etching stop layer 3. The second etching stop layer 4 serves as both an etching stop layer for the first transition layer 5 and a collector contact layer. Then, a magnetron sputtering process is used to deposit Ti / Pt / Au to form a common electrode 132. The common electrode 132 connects the second etching stop layer 4 and the corresponding emitter contact layer 11 (such as Figure 1 The common electrode 132 is climbed, and the preparation of the detector array chip 10 is completed.

[0084] Next, standard photolithography, electron beam evaporation and lift-off processes are used to prepare indium column arrays 20 on the detector array chip 10 and the readout circuit 30, respectively, and interconnected by flip-chip bonding. Resin 14 is used to fill the gap between the detector array chip 10 and the readout circuit 30 except for the indium columns 201.

[0085] Finally, the detector welded to the readout circuit 30 is loaded onto a mechanical grinding and polishing machine, and the InP substrate 1 is thinned to about 10 microns by mechanical grinding and polishing. The thinned and polished device is then placed in a mixed solution of HCl, H3PO4, and H2O. A wet etching process is used to completely remove the InP substrate 1 and the InP buffer layer 2 (a total thickness of about 10.5 microns), and the etching is stopped at the surface of the first corrosion stop layer 3 away from the second corrosion stop layer 4. The device is then cleaned with deionized water and dried to complete the preparation of the detector.

[0086] It is understandable that the detector provided by the present invention uses common III-V materials, and the structural design and manufacturing process are compatible with the existing InGaAs material epitaxial process and focal plane detector preparation process.

[0087] The above describes embodiments of the present invention. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present invention. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present invention.

Claims

1. A detector, characterized in that: The device comprises a detector array chip, an indium column array, and a readout circuit. The detector array chip is connected to the readout circuit via the indium column array. The detector array chip comprises: a first etching stop layer, located on a side of the indium column array away from the readout circuit; a second corrosion stop layer, located on a side of the first corrosion stop layer close to the indium column array; An NPN transistor array is located on a side of the second etching stop layer close to the indium column array; an emitter region contact layer, located on a side of the NPN transistor array close to the indium column array; The electrode layer connects the emitter contact layer and the indium column array.

2. The detector according to claim 1, characterized in that The NPN transistor array comprises: a first N-electrode layer, located between the second etching stop layer and the emitter region contact layer; A P-electrode layer, located between the first N-electrode layer and the emitter region contact layer; The second N-electrode layer is located between the P-electrode layer and the emitter region contact layer.

3. The detector according to claim 2, characterized in that The detector array chip further includes a first transition layer, which is located between the second corrosion stop layer and the first N-electrode layer.

4. The detector according to claim 2, characterized in that The detector array chip further includes a second transition layer and a third transition layer. The second transition layer is located between the P electrode layer and the second N electrode layer. The third transition layer is located between the second N electrode layer and the emitter contact layer.

5. The detector according to claim 1, characterized in that The detector array chip further includes a contact hole, wherein the contact hole extends from the emitter region contact layer to a surface of the second corrosion stop layer away from the first corrosion stop layer; The electrode layer includes an array electrode and a common electrode. The array electrode connects the emitter contact layer and the corresponding indium pillars in the indium pillar array. The common electrode connects the second corrosion stop layer and the corresponding indium pillars in the indium pillar array through the contact hole.

6. The detector according to claim 1, characterized in that The thickness of the first corrosion stop layer is greater than or equal to 0.05 micrometers and less than or equal to 0.5 micrometers; the doping type of the first corrosion stop layer is N-type doping, and the doping concentration of the first corrosion stop layer is greater than or equal to 1×10 17 per cubic centimeter and less than or equal to 2×10 19 per cubic centimeter.

7. The detector according to claim 1, characterized in that The thickness of the second corrosion stop layer is greater than or equal to 0.02 microns and less than or equal to 0.2 microns; the doping type of the second corrosion stop layer is N-type doping, and the doping concentration of the second corrosion stop layer is greater than or equal to 1×10 17 per cubic centimeter and less than or equal to 2×10 19 per cubic centimeter.

8. A method for manufacturing a detector, characterized in that: include: forming a detector array chip; preparing indium column arrays on the detector array chip and the readout circuit respectively; Connecting the detector array chip and the readout circuit via the indium column array; Wherein, forming the detector array chip comprises: forming a first corrosion stop layer; forming a second etch stop layer on the first etch stop layer; forming an NPN transistor array on the second etching stop layer; forming an emitter contact layer on the NPN transistor array; An electrode layer is formed on the emitter contact layer, wherein the electrode layer connects the emitter contact layer and the indium column array.

9. The production method according to claim 8, characterized in that: Before forming the first corrosion stop layer, the manufacturing method further includes: forming a buffer layer on the substrate; The forming of the first corrosion stop layer comprises: forming a first corrosion stop layer on a surface of the buffer layer away from the substrate; After connecting the detector array chip and the readout circuit via the indium pillar array, the manufacturing method further includes: The substrate and the buffer layer are removed.

10. The manufacturing method according to claim 8, characterized in that: The electrode layer includes an array electrode and a common electrode, and the electrode layer is formed on the emitter region contact layer, including: forming an array electrode on the emitter region contact layer, wherein the array electrode connects the emitter region contact layer and corresponding indium pillars in the indium pillar array; forming a contact hole, wherein the contact hole extends from the emitter region contact layer to a surface of the second etching stop layer away from the first etching stop layer; A common electrode is formed on the emitter region contact layer, and the common electrode is connected to the second etching stop layer and the corresponding indium pillars in the indium pillar array through the contact hole.

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