Solar cell and photovoltaic module

Abstract

The invention discloses a solar cell and a photovoltaic module. The solar cell includes a semiconductor substrate having a first semiconductor layer on a first surface; the passivation layer at least covers one side, deviating from the semiconductor substrate, of the first semiconductor layer; a first seed layer electrically connected to the first semiconductor layer through the passivation layer; the first seed layer comprises a plurality of first metal particles and a plurality of second metal particles stacked on at least local surfaces of the first metal particles, the particle size of the first metal particles is a, the particle size of the second metal particles is b, and a-b is greater than or equal to 40nm and / or a is greater than or equal to 1.5 b. The surface roughness of the first seed layer can be increased, so that the specific surface area of the first seed layer is increased, more metal contact points exist between the first seed layer and the first grid line, more metal contact is formed, the contact resistance between the first seed layer and the first grid line is reduced, and the power generation efficiency of the battery is improved; meanwhile, the adhesive force of the first grid lines is improved, and the first grid lines can be prevented from falling off.

Description

Technical Field

[0001] The present application relates to the field of photovoltaic technology, and in particular to a solar cell and a photovoltaic module. Background Art

[0002] A solar cell is a device that converts sunlight into electrical energy. Specifically, when a solar cell is in operation, sunlight strikes the pn junction of the solar cell's semiconductor, forming new hole-electron pairs. Under the influence of the built-in electric field within the pn junction, the photogenerated holes flow to the p region, and the photogenerated electrons flow to the n region. Once the circuit is connected, current is generated.

[0003] As the photovoltaic industry's market and production capacity continue to expand, the industry's demand for silver paste has also surged. The price of silver paste has risen accordingly, costs have continued to rise, and profit margins have been increasingly squeezed. Summary of the Invention

[0004] The purpose of the present application is to provide a solar cell and a photovoltaic module, so as to reduce the manufacturing cost of the solar cell while reducing the current transmission loss and improving the adhesion of the grid line.

[0005] In order to achieve the above objectives, this application provides the following technical solutions:

[0006] A solar cell comprising:

[0007] A semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to each other, the first surface having a first semiconductor layer;

[0008] a passivation layer covering at least a side of the first semiconductor layer facing away from the semiconductor substrate;

[0009] a first seed layer, the first seed layer being electrically connected to the first semiconductor layer through the passivation layer; the first seed layer comprising a plurality of first metal particles and a plurality of second metal particles deposited on at least a portion of the surface of the first metal particles, wherein the first metal particles have a particle size a, the second metal particles have a particle size b, and ab ≥ 40 nm and / or a ≥ 1.5 b;

[0010] A plurality of first gate lines extend along the first direction and are spaced apart along the second direction. At least a portion of the first gate lines is disposed on a side of the first seed layer away from the semiconductor substrate.

[0011] The second direction is orthogonal to the first direction. When the first direction is the length direction of the battery body, the second direction is the width direction of the battery body; when the first direction is the width direction of the battery body, the second direction is the length direction of the battery body.

[0012] Using this technical solution, a first seed layer is first formed, and then the first grid lines are formed on the first seed layer. This first seed layer can be made of a variety of metals, such as one or more of Al, Zn, Fe, Co, Mg, Ag, Ni, and their alloys. The first grid lines can be formed from a base metal paste. Compared to the existing technique of burning silver paste through the passivation layer to form the entire silver electrode, this can significantly reduce the amount of silver paste required to produce the entire electrode structure of the solar cell, thereby reducing the production cost of the entire electrode structure.

[0013] Furthermore, the first seed layer includes a plurality of first metal particles, and the plurality of first metal particles are stacked together; and a plurality of second metal particles are stacked and arranged on at least a partial surface of the first metal particles, and the particle size a of the first metal particles and the particle size b of the second metal particles differ by at least 40 nm, and / or, a≥1.5b. With this technical solution, the particle size of the first metal particles is relatively large, and the plurality of first metal particles are stacked together, so that there is a height difference between the plurality of first metal particles located on the surface of the first seed layer. At the same time, a plurality of second particles are arranged on the upper side of the first metal particles, so that the surface undulations of the first seed layer increase, thereby facilitating an increase in the surface roughness of the first seed layer, thereby increasing the specific surface area of ​​the surface of the first seed layer. After the first grid line contacts the first seed layer, more metal contact points can be provided between the first seed layer and the first grid line, thereby forming more metal contacts, reducing the contact resistance between the first seed layer and the first grid line, and improving the power generation efficiency of the battery; at the same time, the adhesion of the first grid line is improved, which can prevent the first grid line from falling off. Moreover, when multiple second metal particles are arranged around the first metal particles, the second metal particles have a smaller particle size and are suitable for being placed between the first metal particles to reduce the current transmission loss between adjacent first metal particles, improve the current transmission efficiency between adjacent first metal particles, and further improve the power generation efficiency of the battery.

[0014] In one implementation, 100 nm ≥ a ≥ 1000 nm; and / or, 10 nm ≥ b ≥ 60 nm; and / or, ab ≤ 990 nm; and / or, a ≤ 100 b.

[0015] In one implementation, the first metal particles and / or the second metal particles are uniformly distributed inside and on the surface of the first seed layer.

[0016] In one implementation, at least some of the first metal particles are independent spherical particles; and / or at least two or more first metal particles are adhered together.

[0017] In one implementation, the series resistance of the solar cell is 0.005Ω to 0.01Ω.

[0018] In one implementation, the solar cell further includes a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer;

[0019] The second semiconductor layer is disposed on the second surface;

[0020] Alternatively, the second semiconductor layer is disposed on the first surface, and the first semiconductor layer and the second semiconductor layer are alternately distributed along the second direction.

[0021] In one embodiment, the passivation layer also covers the side of the second semiconductor layer facing away from the semiconductor substrate; the solar cell also includes a second seed layer, which is electrically connected to the first semiconductor layer through the passivation layer; the second seed layer includes a plurality of first metal particles and a plurality of second metal particles stacked on at least a partial surface of the first metal particles.

[0022] In one implementation, the particle size of the first metal particles of the second seed layer is different from that of the first metal particles of the first seed layer; and / or the particle size of the second metal particles of the second seed layer is different from that of the second metal particles of the first seed layer.

[0023] In one implementation, the first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer; the particle size of the first metal particles of the first seed layer is a1, and the particle size of the second metal particles of the first seed layer is b1; the particle size of the first metal particles of the second seed layer is a2, and the particle size of the second metal particles of the first seed layer is b2;

[0024] a1≥a2; and / or, b1≥b2; and / or, the number of first metal particles contained in the first seed layer is greater than the number of first metal particles contained in the second seed layer; and / or, the number of second metal particles contained in the first seed layer is greater than the number of second metal particles contained in the second seed layer.

[0025] In one implementation, the passivation layer has a plurality of first openings exposing the first semiconductor layer;

[0026] The first seed layer includes a portion arranged corresponding to the first opening and an overflow portion located on a side of the passivation layer away from the semiconductor substrate.

[0027] Using the above technical solution, the first seed layer also includes an overflow portion located on a surface facing away from the semiconductor substrate. The formation of the overflow portion increases the contact area between the first seed layer and the first gridline, thereby improving the adhesion between the first gridline and the first seed layer, preventing the first gridline from falling off, and thus improving the performance stability of the solar cell. Furthermore, when the overflow portion is electrically connected to the portion of the first seed layer corresponding to the first opening, the electrical conductivity between the first seed layer and the first gridline is improved, transmission losses are reduced, and current transmission efficiency is improved.

[0028] In one implementation, the overflow portions around at least two adjacent first openings are at least partially connected.

[0029] In one implementation, the overflow portion is dispersedly disposed around the first opening.

[0030] In one implementation, the overflow portion around the first opening extends along the first direction.

[0031] In one implementation, the first seed layer is formed of a base metal paste.

[0032] In one implementation, along the second direction, the width of the first opening is 3 μm to 30 μm.

[0033] In one implementation, the first semiconductor layer is an N-type semiconductor layer, and the width of the first opening is 3 μm to 20 μm; or, the first semiconductor layer is a P-type semiconductor layer, and the width of the first opening is 5 μm to 30 μm.

[0034] In one implementation, the first openings are arranged in multiple groups, each group of first openings is distributed in at least one row, and each row includes at least two first openings spaced apart along the first direction.

[0035] In one implementation, the plurality of first openings in the same group do not overlap or partially overlap; and / or the first openings include circular holes, elliptical holes and / or polygonal holes.

[0036] In one implementation, the orthographic projection area of ​​the first seed layer on the first surface is 4% to 70% of the orthographic projection area of ​​the first grid line on the first surface.

[0037] In one implementation, the second semiconductor layer is provided on the second surface, the passivation layer further covers a side of the second semiconductor layer facing away from the semiconductor substrate, and the passivation layer has a plurality of second openings exposing the second semiconductor layer;

[0038] The solar cell further includes a second seed layer and second grid lines. A plurality of second grid lines extend along the first direction and are spaced apart along the second direction. At least a portion of the second grid lines is disposed on a side of the first seed layer away from the semiconductor substrate.

[0039] A photovoltaic module comprises a plurality of solar cells as described above and at least one interconnecting element, wherein the interconnecting element connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, the interconnecting element is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell, wherein the polarity of the second grid line is opposite to that of the first grid line.

[0040] Compared with the prior art, the beneficial effects of the photovoltaic module provided by the embodiment of the present application are the same as the beneficial effects of the above-mentioned solar cell and the method for manufacturing the solar cell, and are not described in detail here. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0042] Figure 1 A partial cross-sectional SEM image of a solar cell provided in an embodiment of the present application;

[0043] Figure 2 This is an SEM image of the first seed layer provided in an embodiment of the present application;

[0044] Figure 3 A cross-sectional SEM image of the first seed layer provided in an embodiment of the present application;

[0045] Figure 4 A top-down SEM image of the first seed layer provided in an embodiment of the present application;

[0046] Figure 5 A schematic diagram of an N-region seed layer provided in an embodiment of the present application;

[0047] Figure 6 A schematic diagram of a P-region seed layer provided in an embodiment of the present application;

[0048] Figure 7 A partial cross-sectional view of a solar cell provided in another embodiment of the present application;

[0049] Figure 8 A top-view SEM image of an opening in the passivation layer of a solar cell provided in an embodiment of the present application;

[0050] Figure 9 A partial top-view SEM image of a solar cell provided in an embodiment of the present application;

[0051] Figure 10 A schematic diagram of a partial top view of a solar cell provided in an embodiment of the present application;

[0052] Figure 11 A partial top view schematic diagram of a solar cell provided in another embodiment of the present application;

[0053] Figure 12 A partial cross-sectional schematic diagram of a solar cell provided in an embodiment of the present application;

[0054] Figure 13 A partial top view schematic diagram of a solar cell provided in another embodiment of the present application;

[0055] Figure 14 A partial top view SEM image of a solar cell provided in another embodiment of the present application;

[0056] Figure 15 A partial top view schematic diagram of a solar cell provided in another embodiment of the present application;

[0057] Figure 16 A partial cross-sectional schematic diagram of a solar cell provided in another embodiment of the present application;

[0058] Figure 17 A partial top view SEM image of a solar cell provided in another embodiment of the present application;

[0059] Figure 18 A partial top view schematic diagram of a solar cell provided in another embodiment of the present application;

[0060] Figure 19 A schematic diagram of the first opening provided in an embodiment of the present application.

[0061] Reference numerals:

[0062] 1-semiconductor substrate, 2-first semiconductor layer, 3-passivation layer, 301-first opening, 4-first seed layer, 401-overflow portion, 402-first metal particles, 403-second metal particles, 5-first interface layer, 6-first gate line, 7-second semiconductor layer, 8-second seed layer, 9-second gate line. DETAILED DESCRIPTION

[0063] In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not intended to limit this application.

[0064] It should be noted that when an element is referred to as being “fixed on” or “disposed on” another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being “connected to” another element, it may be directly connected to the other element or indirectly connected to the other element.

[0065] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0066] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", etc., indicating directions or positional relationships, are based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limitations on this application.

[0067] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal communication between two components or the interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0068] On the one hand, the present application provides a solar cell to reduce the manufacturing cost of the solar cell while reducing the current transmission loss and improving the adhesion of the grid line.

[0069] See also Figure 1 The solar cell provided in the embodiment of the present application includes a semiconductor substrate 1, a first semiconductor layer 2, a passivation layer 3, a first seed layer 4, and a first gate line 6. The semiconductor substrate 1 includes a first surface and a second surface that are opposite to each other along the thickness direction of the semiconductor substrate 1. The first surface can correspond to the backlight side of the solar cell, and the second surface can correspond to the light-facing side of the solar cell; alternatively, the first surface can correspond to the light-facing side of the solar cell, and the second surface can correspond to the backlight side of the solar cell.

[0070] The first surface has a first semiconductor layer 2. Specifically, the first semiconductor layer 2 can be disposed on the first surface in its entirety or in part. When the first semiconductor layer 2 is disposed partially on the first surface, the first semiconductor layer 2 can be arranged in strips or in a "F" shape at intervals on the first surface; there is an isolation region between adjacent first semiconductor layers 2. When the current transmission capacity of the first semiconductor layer 2 itself is high, removing a portion of the first semiconductor layer 2 has no effect on the performance of the solar cell, and the passivation effect in the area where the first semiconductor layer 2 is removed is better and there is no parasitic absorption, which is beneficial to improving the power generation efficiency. The first semiconductor layer 2 can be additionally formed on the semiconductor substrate 1 by a deposition technique, or can be formed within the semiconductor substrate 1 by diffusion, ion implantation, or the like.

[0071] The passivation layer 3 covers at least one side of the first semiconductor layer 2 facing away from the semiconductor substrate 1. The passivation layer 3 can protect the surface of the cell and prevent water vapor or oxygen from penetrating into the interior of the cell, thereby avoiding performance degradation of the cell due to oxidation or hydrolysis. In addition, the provision of the passivation layer 3 can reduce the surface recombination rate of the cell, thereby improving the photoelectric conversion efficiency of the cell. The passivation layer 3 can be a single-layer structure; alternatively, the passivation layer 3 can also be a multi-layer structure. Specifically, the passivation layer 3 is at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, and an aluminum oxide layer, or a composite film formed by stacking them. Exemplarily, the passivation layer 3 can be a double-layer structure, comprising an aluminum oxide layer and a silicon nitride layer, and the aluminum oxide layer is located on the side of the silicon nitride layer close to the semiconductor substrate 1.

[0072] The first seed layer 4 is electrically connected to the first semiconductor layer 2 through the passivation layer 3, that is, the carriers collected by the first semiconductor layer 2 are conducted out through the first seed layer 4. Figure 2 As shown, the first seed layer 4 includes a plurality of first metal particles 402 and a plurality of second metal particles 403 stacked on at least a portion of the surface of the first metal particles 402. Specifically, the second metal particles 403 can be attached to the surface of the first metal particles 402; or, a portion of the second metal particles 403 is attached to the surface of the first metal particles 402, and another portion of the second metal particles 403 is filled in the gap between two adjacent first metal particles 402. The particle size of the first metal particles 402 is a, and the particle size of the second metal particles 403 is b, where ab ≥ 40nm and / or a ≥ 1.5b. The particle size of the first metal particles 402 can be the equivalent diameter of the first metal particles 402. The particle size of the second metal particles 403 can be the equivalent diameter of the second metal particles 403. Specifically, the equivalent diameter can be a screening equivalent diameter, a volume equivalent diameter, or a surface area equivalent diameter.

[0073] Using the above technical solution, a first seed layer 4 is first formed, and then a first grid line 6 is formed on the first seed layer 4. The first seed layer 4 can be made of a variety of metals, such as one or more of Al, Zn, Fe, Co, Mg, Ag, Ni, and alloys thereof. The first grid line 6 can be formed from a base metal slurry. Compared to the prior art method of burning silver paste through the passivation layer 3 to form the entire silver electrode, this method can significantly reduce the amount of silver paste required to produce the entire electrode structure of the solar cell, thereby reducing the production cost of the entire electrode structure.

[0074] Furthermore, the first seed layer 4 includes a plurality of first metal particles 402, and the plurality of first metal particles 402 are stacked together; and a plurality of second metal particles 403 are stacked on at least a partial surface of the first metal particles 402, and the particle size a of the first metal particles 402 and the particle size b of the second metal particles 403 differ by at least 40 nm, and / or a≥1.5b. With this technical solution, the first metal particles 402 have a larger particle size, and multiple first metal particles 402 are stacked together, resulting in a height difference between the multiple first metal particles 402 located on the surface of the first seed layer 4. At the same time, when multiple second metal particles 403 are arranged on the upper side of the first metal particles 402, the surface undulations of the first seed layer 4 increase, thereby increasing the surface roughness of the first seed layer 4 and the specific surface area of ​​the first seed layer 4. After the first gate line contacts the first seed layer 4, there are more metal contact points between the first seed layer 4 and the first gate line, thereby forming more metal contacts, reducing the contact resistance between the first seed layer 4 and the first gate line, and improving the power generation efficiency of the battery. At the same time, the adhesion of the first gate line is improved, which can prevent the first gate line from falling off. In addition, the multiple second metal particles 403 are arranged around the first metal particles 402. The smaller particle size of the second metal particles 403 is suitable for being between the first metal particles 402, thereby reducing the current transmission loss between adjacent first metal particles 402 and improving the current transmission efficiency between adjacent first metal particles 402, further improving the power generation efficiency of the battery.

[0075] Alternatively, ab≥50nm, or ab≥80nm, or ab≥100nm, or ab≥200nm, etc. For example, the difference ab between the particle size a of the first metal particles 402 and the particle size b of the second metal particles 403 may be 40nm, 42nm, 45nm, 46nm, 48nm, 49nm, 50nm, 52nm, 55nm, 58nm, 60nm, 62nm, 65nm, 68nm, 70nm, 80nm, 90nm, 100nm, 150nm, 200nm, 250nm, 300nm, 350nm, 400nm, 450nm, 500nm, 550nm, 600nm, 650nm, 700nm, 750nm, 800nm, 850nm, 900nm, 950nm, or 990nm. In order to avoid a large difference between the particle size a of the first metal particles 402 and the particle size b of the second metal particles 403, ab is made ≤ 990 nm to prevent the contact area between the second metal particles 403 and the first metal particles 402 from being too small, thereby ensuring a lower current transmission loss between the second metal particles 403 and the first metal particles 402, and further improving the power generation efficiency of the battery.

[0076] Alternatively, a≥2b, or a≥5b, or a≥10b, or a≥30b, etc. For example, the particle size a of the first metal particles 402 may be 1.5b, 1.7b, 1.8b, 2b, 2.2b, 2.5b, 2.8b, 3b, 3.2b, 3.5b, 3.8b, or 4b, 5b, 6b, 7b, 8b, 9b, 10b, 15b, 20b, 25b, 30b, 35b, 40b, 45b, 50b, 55b, 60b, 65b, 70b, 75b, 80b, 85b, 90b, 95b, or 100b, etc. In order to avoid a large difference between the particle size a of the first metal particles 402 and the particle size b of the second metal particles 403, a is set to ≤ 100b, so as to prevent the contact area between the second metal particles 403 and the first metal particles 402 from being too small, thereby ensuring a lower current transmission loss between the second metal particles 403 and the first metal particles 402, and further improving the power generation efficiency of the battery.

[0077] The inventors of this application analyzed and compared the two situations where the first seed layer 4 includes the first metal particles 402 and the second metal particles 403 and the first seed layer 4 has a smooth surface and obtained the following table:

[0078]

[0079]

[0080] As can be seen from the table above, when the first seed layer 4 includes first metal particles 402 and second metal particles 403, the series resistance of the solar cell is significantly reduced, and the power generation efficiency is significantly improved. When ab ≥ 40nm or a ≥ 1.5b, the series resistance of the solar cell is significantly lower than when ab < 40nm or a < 1.5b; and the power generation efficiency of the solar cell is significantly higher than when ab < 40nm or a < 1.5b.

[0081] The series resistance of the solar cell is 0.005Ω to 0.01Ω, so as to ensure that the solar cell has a low series resistance and a high power generation efficiency. For example, the series resistance of the solar cell is 0.005Ω, 0.006Ω, 0.007Ω, 0.008Ω, 0.009Ω or 0.01Ω.

[0082] In some embodiments, as Figure 4 As shown, if the particle size a of the first metal particles 402 is too large, the transmission resistance of the first seed layer 4 itself will be large, resulting in high current transmission loss; if the particle size a of the first metal particles 402 is too small, the roughness of the surface of the first seed layer 4 will be reduced, resulting in a reduced contact area between the first seed layer 4 and the first gate line, an increase in contact resistance, and an increase in transmission loss between the first seed layer 4 and the first gate line. In view of the above two situations, in this technical solution, the particle size a of the first metal particles 402 is set within a reasonable range of 100nm≥a≥1000nm to ensure that the transmission resistance of the first seed layer 4 itself is low while increasing the roughness of the surface of the first seed layer 4, thereby reducing the transmission loss between the first seed layer 4 and the first gate line. Illustratively, the particle size a of the first metal particles 402 may be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, or 1000 nm.

[0083] In some embodiments, as Figure 3As shown, if the particle size b of the second metal particles 403 is too large, the transmission resistance between adjacent first metal particles 402 will increase, resulting in an increase in the current transmission loss of the first seed layer 4 itself; if the particle size b of the second metal particles 403 is too small, the content of organic matter in the gaps between the metal particles will decrease, resulting in a decrease in the adhesion of the first seed layer 4 and easy falling off. In order to balance the above two aspects, in this application, the particle size b of the second metal particles 403 is set within a reasonable range of 10nm≥b≥60nm, so as to ensure that the transmission resistance of the first seed layer 4 itself is low while increasing the content of organic matter in the gaps between the metal particles, thereby improving the adhesion of the first seed layer 4. Exemplarily, the particle size b of the second metal particles 403 can be 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm or 60nm, etc.

[0084] In some embodiments, the first metal particles 402 are evenly distributed inside and on the surface of the first seed layer 4, that is, the first metal particles 402 are deposited on the surface and inside of the first seed layer 4. This arrangement helps reduce the current transmission differences at various locations on the first seed layer 4, ensuring that the current transmission efficiency differences at various locations on the first seed layer 4 are small, preventing local current from being too high or too low, and avoiding local overheating or large local current transmission losses.

[0085] In some embodiments, the second metal particles 403 are evenly distributed inside and on the surface of the first seed layer 4, thereby utilizing the second metal particles 403 to ensure that the transmission resistance of each position of the first seed layer 4 is low, thereby helping to reduce the current transmission difference at each position of the first seed layer 4, and also preventing the current from being too large or too small.

[0086] In some embodiments, at least some of the first metal particles 402 are independent, quasi-spherical in shape; that is, some of the first metal particles 402 are independent particles that are not connected to the remaining first metal particles 402. The independent first metal particles 402 are quasi-spherical, such as ellipsoidal or spherical. In this technical solution, the independent first metal particles 402 are more conducive to increasing the surface undulations of the first seed layer 4, thereby increasing the specific surface area of ​​the first seed layer 4, providing more metal contact points between the first seed layer 4 and the first gate line, thereby forming more metal contacts and reducing the contact resistance between the first seed layer 4 and the first gate line.

[0087] In some embodiments, at least two first metal particles 402 are bonded together, that is, at least two of all first metal particles 402 are bonded together. Among the bonded first metal particles 402, two adjacent first metal particles 402 are at least partially in contact with each other. This reduces transmission loss between the bonded first metal particles 402, further improving power generation efficiency.

[0088] The solar cell provided in the present application also includes a second semiconductor layer 7. The second semiconductor layer 7 has a conductivity type opposite to that of the first semiconductor layer 2, so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent. The second semiconductor layer 7 can be provided on the second surface, in which case the solar cell is a bifacial cell. Specifically, the second semiconductor layer 7 can be provided on the second surface in its entirety or in a portion thereof. When the second semiconductor layer 7 is provided on the second surface in a portion thereof, the second semiconductor layer 7 can be arranged in strips or a "F"-like pattern at intervals on the second surface, with isolation regions between adjacent second semiconductor layers 7.

[0089] Alternatively, the second semiconductor layer 7 is provided on the first surface, and the first semiconductor layer 2 and the second semiconductor layer 7 are alternately distributed along the second direction. In this case, the solar cell is a back-contact cell.

[0090] In some embodiments, the passivation layer 3 also covers the side of the second semiconductor layer 7 facing away from the semiconductor substrate 1. The solar cell also includes a second seed layer 8 and a second grid line 9, a plurality of second grid lines 9 extending along the first direction and spaced apart along the second direction, and at least part of the second grid line 9 is arranged on the side of the first seed layer 4 facing away from the semiconductor substrate 1. The second seed layer includes a plurality of first metal particles 402 and a plurality of second metal particles 403 stacked and arranged on at least a partial surface of the first metal particles 402. The technical features of the first metal particles 402 and the second metal particles 403 here can be referred to above and will not be repeated here. By adopting this technical solution, more metal contact points can be provided between the second seed layer and the second grid line, thereby forming more metal contacts, reducing the contact resistance between the second seed layer and the second grid line, and improving the power generation efficiency of the battery. In addition, multiple second metal particles 403 are arranged around the first metal particles 402. The second metal particles 403 have a smaller particle size and are suitable for being placed between the first metal particles 402 to reduce the current transmission loss between adjacent first metal particles 402, improve the current transmission efficiency between adjacent first metal particles 402, and further improve the power generation efficiency of the battery.

[0091] In some embodiments, the materials of the first metal particles 402 and the second metal particles 403 can be the same or different. The first metal particles 402 can be made of one or more of Al, Zn, Fe, Co, Mg, Ag, Ni, and alloys thereof. The second metal particles 403 can be made of one or more of Al, Zn, Fe, Co, Mg, Ag, Ni, and alloys thereof.

[0092] In some embodiments, the particle size of the first metal particles 402 of the second seed layer 8 is different from the particle size of the first metal particles 402 of the first seed layer 4. The particle size of the second metal particles 403 of the second seed layer 8 is different from the particle size of the second metal particles 403 of the first seed layer 4. In this way, the particle size of the first metal particles 402 of the second seed layer 8 and the particle size of the second metal particles 403 of the second seed layer 8 can be set according to the actual conductive efficiency of the first seed layer 4 and the second seed layer 8, so that the particle size of the first metal particles 402 of the second seed layer 8 and the particle size of the second metal particles 403 of the second seed layer 8 are more compatible with the conductive efficiency of the second seed layer 8; and the particle size of the first metal particles 402 of the first seed layer 4 and the particle size of the second metal particles 403 of the first seed layer 4 are set so that the particle size of the first metal particles 402 of the first seed layer 4 and the particle size of the second metal particles 403 of the first seed layer 4 are more compatible with the conductive efficiency of the first seed layer 4.

[0093] In some embodiments, the first semiconductor layer 2 is an N-type semiconductor layer, that is, the first semiconductor layer 2 is doped with group V elements or group VI elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc. The first semiconductor layer 2 is a P-type semiconductor layer, doped with group III elements, such as boron (B), aluminum (Al), gallium (Ga), etc. In this technical solution, the particle size of the first metal particles 402 of the first seed layer 4 is a1, and the particle size of the second metal particles 403 of the first seed layer 4 is b1; the particle size of the first metal particles 402 of the second seed layer is a2, and the particle size of the second metal particles 403 of the first seed layer 4 is b2. Figure 5 and Figure 6As shown, a1 ≥ a2; and / or b1 ≥ b2; and / or the number of first metal particles 402 contained in the first seed layer 4 is greater than the number of first metal particles 402 contained in the second seed layer; and / or the number of second metal particles 403 contained in the first seed layer 4 is greater than the number of second metal particles 403 contained in the second seed layer. That is, the particle size of the first metal particles 402 contained in the seed layer in the N region is greater than the particle size of the first metal particles 402 contained in the seed layer in the P region; and / or the particle size of the second metal particles 403 contained in the seed layer in the N region is greater than the particle size of the second metal particles 403 contained in the seed layer in the P region; and / or the number of first metal particles 402 contained in the seed layer in the N region is greater than the number of first metal particles 402 contained in the seed layer in the P region; and / or the number of second metal particles 403 contained in the seed layer in the N region is greater than the number of second metal particles 403 contained in the seed layer in the P region. With this arrangement, when the solar cell is operating normally, electrons in the N region can more efficiently transmit to the paste layer through the numerous pathways formed by the surface structure of the larger number of larger-particle-size metal particles, thereby reducing electron transmission obstacles. In contrast, the P region, with its relatively small number and smaller metal particles, is more stable in terms of hole transport. The PN regions work synergistically, stabilizing hole transport in the P region and enhancing electron transport in the N region. This improves the separation and transport efficiency of photogenerated carriers, thereby increasing the battery's short-circuit current density and ultimately the battery's photoelectric conversion efficiency.

[0094] In some embodiments, the first metal particles 402 may be spherical or ellipsoidal. The second metal particles 403 may be spherical or ellipsoidal. Spherical or ellipsoidal shapes have a larger contact area with organic matter, which is beneficial for the formation of the seed layer.

[0095] On the other hand, an embodiment of the present invention further provides a method for manufacturing a solar cell, which can be used to prepare the solar cell described in any of the above embodiments. The method for manufacturing a solar cell includes the following steps:

[0096] S100 : providing a semiconductor substrate 1 , wherein the semiconductor substrate 1 has a first surface and a second surface opposite to each other.

[0097] Prior to this step, in some embodiments, the semiconductor substrate 1 may be placed in a polishing and cleaning machine to remove the damaged layer of the semiconductor substrate 1 using a polishing liquid. Furthermore, in this step, the morphology of the first and second surfaces of the semiconductor substrate 1 after polishing and cleaning may be adjusted by controlling parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0098] S200: forming a first semiconductor layer 2 on the first surface.

[0099] In this step, the first semiconductor layer 2 can be formed entirely or partially on the first surface. The first semiconductor layer 2 can be additionally formed on the first surface of the semiconductor substrate 1 by deposition technology, or formed within the semiconductor substrate 1 by diffusion, ion implantation, etc.

[0100] S300 : forming a full-layer passivation layer 3 on the first surface, wherein the passivation layer 3 covers the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1 .

[0101] Specifically, the passivation layer 3 may be formed by deposition or the like. The material and structure of the passivation layer 3 may be referred to above and will not be described in detail here.

[0102] S400: Forming a first seed layer 4, which is electrically connected to the first semiconductor layer through the passivation layer. The first seed layer 4 includes a plurality of first metal particles 402 and a plurality of second metal particles 403 deposited on at least a portion of the surface of the first metal particles 402. The particle size of the first metal particles 402 is a, and the particle size of the second metal particles 403 is b, where ab ≥ 40 nm and / or a ≥ 1.5 b.

[0103] S500 : forming first gate lines 6 , extending along the first direction and spaced apart along the second direction, wherein at least a portion of the first gate lines 6 is disposed on a side of the first seed layer 4 facing away from the semiconductor substrate 1 .

[0104] Compared with the prior art, the manufacturing method of the solar cell has the same beneficial effects as the above-mentioned solar cell, which will not be described in detail here.

[0105] On the other hand, the present application also provides a solar cell comprising a semiconductor substrate 1, a first semiconductor layer 2, a passivation layer 3, a first seed layer 4, and a first gate line 6. The technical features of the semiconductor substrate 1, the first semiconductor layer 2, and the passivation layer 3 can be referred to above and will not be repeated here.

[0106] like Figure 8 As shown, the passivation layer 3 has a plurality of first openings 301 exposing the first semiconductor layer 2. The plurality of first openings 301 can be arranged in multiple groups. A first seed layer 4 is first formed within the first openings 301 of the passivation layer 3, and then a first gate line 6 is formed on the first seed layer 4. The metal process of the first seed layer 4 and the first gate line 6 can be made using a low-temperature process, which reduces the manufacturing difficulty, saves energy consumption, and further reduces production costs.

[0107] The first seed layer 4 includes a portion arranged corresponding to the first opening 301 and an overflow portion 401 located on the side of the passivation layer 3 away from the semiconductor substrate 1. That is, a portion of the first seed layer 4 is arranged corresponding to the first opening 301, and the portion of the first seed layer 4 corresponding to the first opening 301 is electrically connected to the first semiconductor. The other portion of the first seed layer 4 is located on the surface of the passivation layer 3 away from the semiconductor substrate 1. Among them, the portion of the first seed layer 4 located on the surface of the passivation layer 3 away from the semiconductor substrate 1 is the overflow portion 401. The overflow portion 401 and the portion of the first seed layer 4 corresponding to the first opening 301 can be arranged continuously or discontinuously, that is, the overflow portion 401 and the portion of the first seed layer 4 corresponding to the first opening 301 can be conductive or non-conductive. There are multiple first seed layers 4, and a first seed layer 4 is arranged corresponding to each first opening 301. The first seed layer 4 can be formed by processes such as screen printing, electroplating, sputtering or evaporation.

[0108] The first gate line 6 extends along the first direction, that is, the length of the first gate line 6 is set along the first direction. Multiple first gate lines 6 are spaced apart along the second direction. At least part of the first gate line 6 is set on the side of the first seed layer 4 facing away from the semiconductor substrate 1. Each first gate line 6 can be electrically connected to the first seed layer 4 corresponding to a group of first openings 301, that is, the first seed layer 4 corresponding to the first openings 301 in the same group is electrically connected to the same first gate line 6, so as to utilize the first gate line 6 and the first seed layer 4 to guide the carriers collected by the first semiconductor layer 2. The first gate line 6 can be formed by base metal slurry, which is a non-burn-through slurry. The base metal slurry can be considered as a slurry with a base metal content greater than 50%, such as copper slurry, aluminum slurry, silver-clad copper and other relatively inexpensive conductive metals. The first gate line 6 can be formed by processes such as screen printing, electroplating, sputtering or evaporation.

[0109] Using the above technical solution, the first seed layer 4 also includes an overflow portion 401 located on a surface facing away from the semiconductor substrate 1. The formation of the overflow portion 401 increases the contact area between the first seed layer 4 and the first grid line 6, thereby improving the adhesion between the first grid line 6 and the first seed layer 4, preventing the first grid line 6 from falling off, and thus improving the performance stability of the solar cell. Furthermore, when the overflow portion 401 is electrically connected to the portion of the first seed layer 4 corresponding to the first opening 301, the electrical conductivity between the first seed layer 4 and the first grid line 6 is improved, thereby reducing transmission losses and improving current transmission efficiency.

[0110] It can be understood that, from a microscopic perspective, the first seed layer includes first metal particles 402 and second metal particles 403. From a macroscopic perspective, the first seed layer includes a portion corresponding to the first opening 301 and an overflow portion 401 located on the side of the passivation layer 3 away from the semiconductor substrate 1. The overflow portion 401 and the portion of the first seed layer corresponding to the first opening 301 both include first metal particles 402 and second metal particles 403.

[0111] In some embodiments, the overflow portions around at least two adjacent first openings 301 are partially connected, that is, the overflow portions around adjacent first openings 301 extend to be partially connected, further increasing the conductive area and contact area between the first seed layer 4 and the first gate line 6, and can simultaneously improve the conductive performance between the first seed layer 4 and the first gate line 6 and the adhesion of the first gate line 6.

[0112] In some embodiments, as Figures 9-12 As shown, there is discontinuity between the overflow portions 401 around at least two adjacent first openings 301. That is, the overflow portion 401 of the first seed layer 4 corresponding to one first opening 301 is spaced and discontinuous from the overflow portion 401 of the first seed layer 4 corresponding to another adjacent first opening 301. The overflow portion 401 can be formed by extending the first opening 301 in any direction. Specifically, one end of the overflow portion 401 can be connected to the portion of the first seed layer 4 corresponding to the first opening 301, and the other end of the overflow portion 401 can be oriented in any direction. In this way, the overflow portion 401 is conductively connected to the portion of the first seed layer 4 corresponding to the first opening 301, which increases the conductive area and contact area between the first seed layer 4 and the first grid line 6, and can simultaneously improve the conductive performance between the first seed layer 4 and the first grid line 6 and the adhesion of the first grid line 6; it can also reduce the use of raw materials for the first seed layer 4, reduce manufacturing costs, and avoid waste of raw materials for the first seed layer 4.

[0113] In some embodiments, as Figure 13-16 As shown, the overflow portion 401 around at least two adjacent first openings 301 is connected and continuous. Specifically, the overflow portion 401 of the first seed layer 4 corresponding to one first opening 301 is connected to the overflow portion 401 of the first seed layer 4 corresponding to another adjacent first opening 301, that is, the overflow portion 401 is continuous and uninterrupted between the two adjacent first openings 301. Using this technical solution, the conductive area and contact area between the first seed layer 4 and the first gate line 6 can be further increased, thereby further improving the conductive performance between the first seed layer 4 and the first gate line 6 and the adhesion of the first gate line 6.

[0114] In some embodiments, as Figure 17-18As shown, the overflow portion 401 can also be dispersedly arranged around the first opening 301. That is, the dispersed overflow portion 401 is in the form of dispersed points, and the dispersed overflow portion 401 can be conductively connected to the portion of the first seed layer 4 corresponding to the first opening 301 or not. Such a configuration helps save the raw materials of the first seed layer 4 while ensuring battery performance. At the same time, the dispersed overflow portion 401 also helps increase the contact area between the first seed layer 4 and the first grid line 6, thereby helping to increase the adhesion of the first grid line 6 and prevent the first grid line 6 from falling off.

[0115] In some embodiments, the overflow portion 401 around the first opening 301 can extend along the first direction, so that the extension direction of the overflow portion 401 is the same as the extension direction of the first gate line 6, which can further increase the contact area between the first seed layer 4 and the first gate line 6 and further improve the adhesion of the first gate line 6.

[0116] In some embodiments, as Figure 9 、 Figure 11 as well as Figure 14 As shown, the overflow portion 401 around at least two adjacent first openings 301 extends discontinuously along the first direction. Specifically, the overflow portion 401 can be formed by extending from the first opening 301 along the first direction, that is, the length direction of the overflow portion 401 extends along the first direction. Since the first grid line 6 also extends along the first direction, this technical solution is adopted to make the length direction of the overflow portion 401 consistent with the length direction of the first grid line 6, which is beneficial to further increase the contact area between the first grid line 6 and the first seed layer 4, and further improve the adhesion of the first grid line 6. In addition, when the solar cell is a back-contact cell, the overflow portion 401 can be prevented from extending along the second direction to the isolation area or the area with opposite polarity, thereby avoiding the occurrence of leakage.

[0117] In some embodiments, as Figure 14-16 As shown, the overflow portions 401 around at least two adjacent first openings 301 are connected and continuous along the first direction. The overflow portion 401 can be formed by extending from the first opening 301 along the first direction. In this technical solution, the overflow portions 401 of multiple first seed layers 4 are connected in sequence along the first direction, and the first grid line 6 is also continuously extended along the first direction, which is conducive to further increasing the contact area between the first grid line 6 and the first seed layer 4, and further improving the adhesion of the first grid line 6. In addition, when the solar cell is a back-contact cell, the overflow portion 401 can be prevented from extending along the second direction to the isolation area or the area with opposite polarity, thereby avoiding the occurrence of leakage.

[0118] The following is a comparison of the above situations:

[0119] Spot plating status Corresponding adhesion performance Corresponding series resistance Rs Corresponding efficiency No overflow 20% shedding 0.00091Ω 27.04 Overflow 15% shedding 0.00075Ω 28.05 The overflow part is discontinuous 16% shedding 0.00089Ω 28.25 The overflow part is scattered 18% shedding 0.00090Ω 27.5

[0120] As can be seen from the table above, when the first seed layer 4 includes the overflow portion 401, the adhesion of the first grid line 6 is higher and the rate of detachment is significantly lower. When the overflow portion 401 between two adjacent first openings 301 is connected, the rate of detachment of the first grid line 6 is the lowest, the series resistance is the lowest, and the power generation efficiency is the highest.

[0121] In some embodiments, along the second direction, the width of the first opening 301 is 3μm to 30μm. The width of the first opening 301 refers to the distance between the two edges that are farthest apart. If the width of the first opening 301 is too small, the contact resistance between the first semiconductor layer 2 and the first seed layer 4 increases, increasing the current loss; if the width of the first opening 301 is too large, the battery is easily damaged during the laser opening process, and the more the first semiconductor layer 2 is exposed, the easier it is to recombine. In view of the above situation, along the second direction, the width of the first opening 301 is 3μm to 30μm, which makes the width of the first opening 301 more matched with the conductivity of the first semiconductor layer 2, reduces the contact resistance between the first semiconductor layer 2 and the first seed layer 4, and reduces the current loss; at the same time, it avoids easy damage to the battery during the laser opening process and reduces recombination. For example, the width of the first opening 301 may be 3 μm, 5 μm, 8 μm, 10 μm, 12 μm, 15 μm, 18 μm, 20 μm, 22 μm, 25 μm, 28 μm or 30 μm.

[0122] In some embodiments, the first semiconductor layer 2 is an N-type semiconductor layer, that is, the first semiconductor layer 2 is doped with group V elements or group VI elements, such as phosphorus (P), arsenic (As), antimony (Sb), etc. In this technical solution, the N-type semiconductor layer collects fewer carriers than the P-type semiconductor layer, so the width of the first opening 301 can be 3μm to 20μm to match the efficiency of the N-type semiconductor layer in collecting carriers, ensuring the carrier transmission efficiency of the N-type semiconductor layer while avoiding the width of the first opening 301 being too large to reduce recombination. Exemplarily, the width of the first opening 301 can be 3μm, 5μm, 8μm, 10μm, 12μm, 15μm, 18μm or 20μm, etc. The contact resistance between the N-type semiconductor layer and the first seed layer 4 is less than or equal to 0.1mΩ*cm 2 .

[0123] In other embodiments, the first semiconductor layer 2 is a P-type semiconductor layer doped with group III elements, such as boron (B), aluminum (Al), gallium (Ga), etc. In this technical solution, the P-type semiconductor layer collects more carriers than the N-type semiconductor layer, so the width of the first opening 301 can be 5μm to 30μm, to match the efficiency of the P-type semiconductor layer in collecting carriers, to ensure the carrier transmission efficiency of the P-type semiconductor layer, while avoiding a large width of the first opening 301 and reducing recombination. Exemplarily, the width of the first opening 301 can be 5μm, 8μm, 10μm, 12μm, 15μm, 18μm, 20μm, 22μm, 25μm, 28μm or 30μm, etc. The contact resistance between the P-type semiconductor layer and the first seed layer 4 is less than or equal to 0.8mΩ*cm 2 .

[0124] In some embodiments, as Figure 19 As shown, the first openings 301 of the same group corresponding to the same first gate line 6 can be distributed in at least one row, and each row of first openings 301 is arranged along the first direction. Specifically, each row includes a plurality of first openings 301 spaced apart along the first direction extending direction. When each group of first openings 301 is provided with only one row, the plurality of first openings 301 of the same group can be arranged in sequence along the first direction; when a group of first openings 301 is provided in multiple rows, the plurality of first openings 301 of the same group can be distributed in multiple rows and each row of first openings 301 can be arranged in sequence along the first direction. For example, the plurality of first openings 301 can be distributed in two rows, three rows or more rows. In this way, the plurality of first openings 301 are more evenly distributed, and the positions where the first gate line 6 is electrically connected to the first seed layer 4 corresponding to the plurality of first openings 301 are more evenly distributed, which is beneficial for the first gate line 6 to promptly derive the current at each position of the first semiconductor layer 2 to avoid local overheating.

[0125] When a group of first openings 301 are arranged in multiple rows, two adjacent rows of first openings 301 do not overlap or partially overlap, that is, two adjacent rows of first openings 301 may overlap or not overlap; along the first direction, two adjacent first openings 301 may overlap or not overlap, which can be determined according to actual conditions.

[0126] Of course, the shape of the first opening 301 may include a circular hole, an elliptical hole and / or a polygonal hole, which is not limited here.

[0127] In order to ensure that the contact area between the first seed layer 4 and the first gate line 6 is within a reasonable range, so that the transmission resistance between the first seed layer 4 and the first gate line 6 is low and the transmission loss is small. In this technical solution, the orthographic projection area of ​​the first seed layer 4 on the first surface is 4% to 70% of the orthographic projection area of ​​the first gate line 6 on the first surface, so that the contact resistance between the first seed layer 4 and the first gate line 6 is small, and at the same time, the volume of the first seed layer 4 is small and the cost is low. Optionally, the orthographic projection of the first seed layer 4 on the first surface is located inside the orthographic projection of the first gate line 6 on the first surface. Alternatively, the orthographic projection of the first seed layer 4 on the first surface partially overlaps with the orthographic projection of the first gate line 6 on the first surface.

[0128] Exemplarily, the orthographic projection area of ​​the first seed layer 4 on the first surface is 4%, 5%, 10%, 15%, 20%, 25%, 30%, 35%, 40%, 45%, 50%, 65% or 70% of the orthographic projection area of ​​the first gate line 6 on the first surface.

[0129] When the solar cell provided in the present application further includes a second semiconductor layer 7, the second semiconductor layer 7 has a conductivity type opposite to that of the first semiconductor layer 2, so as to collect and conduct electrons and holes respectively, thereby facilitating the formation of photocurrent. The second semiconductor layer 7 can be provided on the second surface, in which case the solar cell is a bifacial cell. Specifically, the second semiconductor layer 7 can be provided on the second surface in its entirety or in a portion thereof. When the second semiconductor layer 7 is provided on the second surface in a portion thereof, the second semiconductor layer 7 can be arranged in strips or in a "F"-like pattern at intervals on the second surface, with isolation regions between adjacent second semiconductor layers 7.

[0130] Alternatively, the second semiconductor layer 7 is provided on the first surface, and the first semiconductor layer 2 and the second semiconductor layer 7 are alternately distributed along the second direction. In this case, the solar cell is a back-contact cell.

[0131] In some embodiments, the passivation layer 3 further covers the side of the second semiconductor layer 7 facing away from the semiconductor substrate 1, and the passivation layer 3 has multiple second openings exposing the second semiconductor layer 7. The solar cell also includes a second seed layer 8 and second grid lines 9. The multiple second grid lines 9 extend along the first direction and are spaced apart along the second direction. At least a portion of the second grid lines 9 is disposed on the side of the first seed layer 4 facing away from the semiconductor substrate 1. The material, structure, and other characteristics of the second seed layer 8 and the second grid lines 9 can be referred to the description of the first seed layer 4 and the first grid lines 6, and will not be repeated here.

[0132] In actual application, the material of the semiconductor substrate 1 can be selected from materials such as silicon (Si) or germanium (Ge) or materials such as gallium arsenide (GaAs). Obviously, in terms of conductivity type, the semiconductor substrate 1 can be an intrinsic conductive substrate, an n-type conductive substrate or a p-type conductive substrate. Optionally, the semiconductor substrate 1 is a p-type conductive substrate or an n-type conductive substrate. Compared with the intrinsic conductive substrate, the p-type conductive substrate or the n-type conductive substrate has better conductivity, so that the final solar cell has a lower body resistivity, thereby improving the efficiency of the solar cell.

[0133] For example, the semiconductor substrate 1 can be a p-type substrate or an n-type substrate. The n-type substrate has the advantages of long minority carrier lifetime, no light decay, and good weak light performance.

[0134] The first semiconductor layer 2 may include doped polycrystalline silicon. Doped polycrystalline silicon layers have enhanced carrier transport properties. Therefore, when the first semiconductor layer 2 is a doped polycrystalline silicon layer, the carrier transport efficiency is higher, which helps improve the photoelectric conversion efficiency of the solar cell. Of course, the first semiconductor layer 2 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0135] The second semiconductor layer 7 may include doped polycrystalline silicon, or the second semiconductor layer 7 may also be one or more of doped amorphous silicon, doped microcrystalline silicon, and doped nanocrystalline silicon.

[0136] In some embodiments, a first interface layer 5 is provided between the first semiconductor layer 2 and the semiconductor substrate 1, and a second interface layer is provided between the second semiconductor layer 7 and the semiconductor substrate 1. The passivation contact structure composed of the interface layer and the semiconductor layer has an excellent interface passivation effect and can achieve selective collection of carriers, reduce the carrier recombination rate in the region where the semiconductor layer is formed on the surface of the semiconductor substrate 1, and further improve the photoelectric conversion efficiency of the solar cell. The material and thickness of the first interface layer 5 can be set according to the material of the first semiconductor layer 2 and actual requirements, and the material and thickness of the second interface layer can be set according to the material of the second semiconductor layer 7 and actual requirements, and are not specifically limited here.

[0137] For example, the first semiconductor layer 2 may be a doped polysilicon layer, the first interface layer 5 may be a tunneling oxide layer, the second semiconductor layer 7 may be a doped polysilicon layer, and the second interface layer may be a tunneling oxide layer.

[0138] An embodiment of the present invention further provides a method for manufacturing a solar cell. The method can be used to prepare the solar cell described in any of the above embodiments. The method for manufacturing a solar cell comprises the following steps:

[0139] S101 : providing a semiconductor substrate 1 , wherein the semiconductor substrate 1 has a first surface and a second surface opposite to each other.

[0140] Prior to this step, in some embodiments, the semiconductor substrate 1 may be placed in a polishing and cleaning machine to remove the damaged layer of the semiconductor substrate 1 using a polishing liquid. Furthermore, in this step, the morphology of the first and second surfaces of the semiconductor substrate 1 after polishing and cleaning may be adjusted by controlling parameters such as temperature, time, cleaning liquid type, and cleaning liquid concentration. It should be noted that in some examples, the polishing and cleaning step may be omitted.

[0141] S201: forming a first semiconductor layer 2 on a first surface.

[0142] In this step, the first semiconductor layer 2 can be formed entirely or partially on the first surface. The first semiconductor layer 2 can be additionally formed on the first surface of the semiconductor substrate 1 by deposition technology, or formed within the semiconductor substrate 1 by diffusion, ion implantation, etc.

[0143] S301 : forming a full-layer passivation layer 3 on the first surface, wherein the passivation layer 3 covers the side of the first semiconductor layer 2 facing away from the semiconductor substrate 1 .

[0144] Specifically, the passivation layer 3 may be formed by deposition or the like. The material and structure of the passivation layer 3 may be referred to above and will not be described in detail here.

[0145] S401 : opening a plurality of first openings 301 in the passivation layer 3 to expose the first semiconductor layer 2 .

[0146] Specifically, a laser grooving process may be used to form a plurality of first openings 301 on the passivation layer 3. In some embodiments, after this step, the cell may be cleaned to remove dust particles generated during the grooving process.

[0147] S501 : forming a first seed layer 4 , the first seed layer 4 including a portion arranged corresponding to the first opening 301 and an overflow portion 401 located on a side of the passivation layer 3 away from the semiconductor substrate 1 .

[0148] The portion of the first seed layer 4 located on the surface of the passivation layer 3 facing away from the semiconductor substrate 1 is the overflow portion 401. The first seed layer 4 can be formed by screen printing, electroplating, sputtering or evaporation.

[0149] S600 : forming first gate lines 6 , extending along the first direction and spaced apart along the second direction, wherein at least a portion of the first gate lines 6 is disposed on a side of the first seed layer 4 facing away from the semiconductor substrate 1 .

[0150] The first gate lines 6 can be formed from a base metal paste, which is a non-burn-through paste. Base metal paste can be considered to contain more than 50% base metal, such as copper paste, aluminum paste, silver-clad copper, or other relatively inexpensive conductive metals. The first gate lines 6 can be formed using processes such as screen printing, electroplating, sputtering, or evaporation.

[0151] In the solar cell formed using the above-described manufacturing method, the formation of the overflow portion 401 of the first seed layer 4 increases the contact area between the first seed layer 4 and the first grid line 6, which helps to improve the adhesion between the first grid line 6 and the first seed layer 4, prevents the first grid line 6 from falling off, and thus improves the performance stability of the solar cell. At the same time, the first seed layer 4 is first formed in the first opening 301 of the passivation layer 3, and then the first grid line 6 is formed on the first seed layer 4. The first grid line 6 can be formed from a base metal slurry. Compared with the prior art in which silver paste burns through the passivation layer 3 to form a silver electrode as a whole, the amount of silver paste required to manufacture the overall electrode structure of the solar cell can be greatly reduced, thereby reducing the manufacturing cost of the overall electrode structure.

[0152] In addition, the present application also provides a photovoltaic assembly, which includes a plurality of solar cells provided in any of the above embodiments and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel. Specifically, the two adjacent solar cells are a first solar cell and a second solar cell, and the interconnecting member connects a first grid line 6 of the first solar cell and extends to a second grid line 9 of the second solar cell. Similarly, the interconnecting member is analogous to form an interconnection of multiple solar cells.

[0153] Compared to the prior art, the beneficial effects of the photovoltaic module provided by the embodiments of the present application are the same as the beneficial effects of the aforementioned solar cell and solar cell manufacturing method, and are not further described here. Furthermore, in the solar cell used in the photovoltaic module, the plurality of first metal particles 402 on the surface of the first seed layer 4 have a height difference, which helps to improve the adhesion between the first grid line and the first seed layer 4, as well as the adhesion between the soldering ribbon and the first grid line.

[0154] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in an appropriate manner in any one or more embodiments or examples.

[0155] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A solar cell, characterized in that: include: a semiconductor substrate comprising a first surface and a second surface opposite to each other, wherein the first surface has a first semiconductor layer; a passivation layer, covering at least a side of the first semiconductor layer facing away from the semiconductor substrate; a first seed layer, the first seed layer passing through the passivation layer and electrically connected to the first semiconductor layer; the first seed layer comprising a plurality of first metal particles and a plurality of second metal particles deposited on at least a portion of the surface of the first metal particles, the first metal particles having a particle size a, the second metal particles having a particle size b, and ab ≥ 40 nm and / or a ≥ 1.5 b; A plurality of first gate lines extend along the first direction and are spaced apart along the second direction. At least a portion of the first gate lines is disposed on a side of the first seed layer away from the semiconductor substrate.

2. The solar cell according to claim 1, wherein 100nm≥a≥1000nm; and / or, 10nm≥b≥60nm; and / or, ab≤990nm; and / or, a≤100b.

3. The solar cell according to claim 1, wherein The first metal particles and / or the second metal particles are distributed inside and on the surface of the first seed layer.

4. The solar cell according to claim 1, wherein At least some of the first metal particles are spherical; and / or at least two or more of the first metal particles are adhered together.

5. The solar cell according to claim 1, wherein The series resistance of the solar cell is 0.005Ω to 0.01Ω.

6. The solar cell according to claim 1, wherein The solar cell further comprises a second semiconductor layer having a conductivity type opposite to that of the first semiconductor layer; The second semiconductor layer is provided on the second surface; Alternatively, the second semiconductor layer is provided on the first surface, and the first semiconductor layer and the second semiconductor layer are alternately distributed along the second direction.

7. The solar cell according to claim 6, characterized in that The passivation layer also covers the side of the second semiconductor layer facing away from the semiconductor substrate; the solar cell also includes a second seed layer, which is electrically connected to the first semiconductor layer through the passivation layer; the second seed layer includes a plurality of first metal particles and a plurality of second metal particles stacked on at least a partial surface of the first metal particles.

8. The solar cell according to claim 7, characterized in that The particle size of the first metal particles of the second seed layer is different from that of the first metal particles of the first seed layer; and / or the particle size of the second metal particles of the second seed layer is different from that of the second metal particles of the first seed layer.

9. The solar cell according to claim 8, characterized in that The first semiconductor layer is an N-type semiconductor layer, and the second semiconductor layer is a P-type semiconductor layer; the particle size of the first metal particles of the first seed layer is a1, and the particle size of the second metal particles of the first seed layer is b1; the particle size of the first metal particles of the second seed layer is a2, and the particle size of the second metal particles of the first seed layer is b2; a1≥a2; and / or, b1≥b2; and / or, the number of first metal particles contained in the first seed layer is greater than the number of first metal particles contained in the second seed layer; and / or, the number of second metal particles contained in the first seed layer is greater than the number of second metal particles contained in the second seed layer.

10. The solar cell according to claim 1, wherein The passivation layer has a plurality of first openings exposing the first semiconductor layer; The first seed layer includes a portion arranged corresponding to the first opening and an overflow portion located on a side of the passivation layer away from the semiconductor substrate.

11. The solar cell according to claim 10, characterized in that The overflow portions around at least two adjacent first openings are at least partially connected.

12. The solar cell according to claim 10, characterized in that The overflow parts are dispersedly arranged around the first opening.

13. The solar cell according to claim 10, characterized in that The overflow portion around the first opening extends along a first direction.

14. The solar cell according to claim 10, characterized in that The width of the first opening is 3 μm to 30 μm.

15. The solar cell according to claim 10, wherein The first semiconductor layer is an N-type semiconductor layer, and the width of the first opening is 3 μm to 20 μm; or, the first semiconductor layer is a P-type semiconductor layer, and the width of the first opening is 5 μm to 30 μm.

16. The solar cell according to claim 10, wherein The first openings are arranged in multiple groups, each group of first openings is distributed in at least one row, and each row includes at least two first openings spaced apart along the first direction.

17. A photovoltaic module, characterized in that: The invention comprises a plurality of solar cells according to any one of claims 1 to 16 and at least one interconnecting member, wherein the interconnecting member connects two adjacent solar cells in series or in parallel; the two adjacent solar cells are respectively a first solar cell and a second solar cell, the interconnecting member is electrically connected to a first grid line of the first solar cell and extends to be electrically connected to a second grid line of the second solar cell, and the polarity of the second grid line is opposite to that of the first grid line.

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