Solar cell and manufacturing method thereof, cell module and photovoltaic system

Abstract

The invention provides a solar cell, a manufacturing method thereof, a cell module and a photovoltaic system. The solar cell comprises a silicon substrate and a passivation structure. The passivation structure comprises a dielectric layer, a first polycrystalline silicon layer arranged on one side, back to the silicon substrate, of the dielectric layer, and at least one second polycrystalline silicon layer; wherein the first polycrystalline silicon layers are nitrogen-doped polycrystalline silicon layers, the nitrogen concentration of at least one first polycrystalline silicon layer is larger than that of any second polycrystalline silicon layer, and the nitrogen concentration of at least one first polycrystalline silicon layer ranges from 0.3 at.% to 35 at.%. According to the solar cell, the nitrogen-doped first polycrystalline silicon layer is introduced into the passivation structure of the solar cell, so that the polycrystalline silicon layer has a stress buffering function, the interface stress of the dielectric layer in the high-temperature passivation process can be effectively reduced, the risk that the dielectric layer in the solar cell has a notch is reduced, and the performance of the solar cell is improved. Therefore, the passivation effect of the solar cell can be improved.

Description

Technical Field

[0001] The present invention relates to the field of photovoltaic technology, and in particular to a solar cell and a manufacturing method thereof, a cell assembly and a photovoltaic system. Background Art

[0002] Solar energy has attracted more and more attention due to its easy availability. In recent years, the solar cell industry has developed rapidly and the application scope of solar cells has become increasingly wide.

[0003] Tunnel Oxide Passivated Contact (TOPCon) is a stacked structure consisting of a heavily doped polysilicon layer, an ultra-thin silicon oxide tunneling layer, and a doped single-crystal silicon base. This structure can simultaneously achieve excellent passivation performance and low contact resistivity, and has therefore been widely studied and applied in academia and industry. However, the passivation level of the n-type TOPCon structure is often restricted by a variety of factors. Studies have shown that after undergoing a high-temperature annealing process, the tunneling oxide layer is prone to form defects (i.e., "notches") on its surface or edge. This phenomenon is particularly significant on velvet silicon substrates, which in turn leads to an increase in the interface defect state density and a decrease in passivation performance.

[0004] Based on this, how to improve the passivation effect of solar cells has become an urgent problem to be solved. Summary of the Invention

[0005] The present invention provides a solar cell and a manufacturing method thereof, a cell assembly and a photovoltaic system, so as to solve the technical problem of how to improve the passivation effect of the solar cell.

[0006] An embodiment of the present invention is implemented as follows: the present invention provides a solar cell and a method for manufacturing the same, a solar cell assembly, and a photovoltaic system. The solar cell includes a silicon substrate and a passivation structure disposed on at least one side of the silicon substrate; the passivation structure includes: a dielectric layer, a first polysilicon layer disposed on a side of the dielectric layer facing away from the silicon substrate, and at least one second polysilicon layer disposed on a side of the first polysilicon layer facing away from the dielectric layer; wherein the first polysilicon layer is a polysilicon layer containing nitrogen, the nitrogen concentration of at least one location in the first polysilicon layer being greater than the nitrogen concentration of any of the second polysilicon layers, and the nitrogen concentration of at least one location in the first polysilicon layer being between 0.3 at.% and 35 at.%.

[0007] Furthermore, the nitrogen concentration of at least one portion of the first polysilicon layer is 0.5 at. % to 25 at. %.

[0008] Furthermore, the thickness of the dielectric layer is 1 nm to 4 nm.

[0009] Furthermore, the thickness of the dielectric layer is 1.5 nm to 2.5 nm.

[0010] Furthermore, the thickness of the first polysilicon layer is 3 nm to 60 nm.

[0011] Furthermore, the thickness of the first polysilicon layer is 5 nm to 40 nm.

[0012] Furthermore, the thickness of the second polysilicon layer is greater than 15 nm.

[0013] Furthermore, the thickness of the second polysilicon layer is greater than 30 nm.

[0014] Furthermore, the phosphorus doping concentration of at least one of the first polysilicon layers is lower than the phosphorus doping concentration of any of the second polysilicon layers.

[0015] Furthermore, the doping concentration of the N-type main element in at least one of the first polysilicon layers is 1.5×10 18 cm -3 to 8×10 20 cm -3 .

[0016] Furthermore, the doping concentration of the N-type main element in at least one of the first polysilicon layers is 5×10 18 cm -3 to 3×10 20 cm -3 .

[0017] Furthermore, the doping concentration of the N-type main element in at least one of the second polysilicon layers is 1.5×10 20 cm -3 to 1×10 21 cm -3 .

[0018] Furthermore, the doping concentration of the N-type main element in at least one of the second polysilicon layers is 1×10 20 cm -3 to 0.8×10 21 cm -3 .

[0019] Furthermore, the nitrogen concentration of the second polysilicon layer is 0.001 at.% to 10 at.%.

[0020] Furthermore, the nitrogen concentration of the second polysilicon layer is 0.001 at.% to 0.2 at.%.

[0021] Furthermore, the nitrogen concentration of the second polysilicon layer is 0.

[0022] Furthermore, the dielectric layer is a silicon oxide dielectric layer, a hydrogenated silicon oxide dielectric layer, a silicon oxynitride dielectric layer or a silicon oxycarbide dielectric layer.

[0023] Furthermore, the dielectric layer includes a plurality of notches, and the number of the notches per unit area in at least one location of the dielectric layer is 10 / μm. 2 Up to 5000 pieces / μm 2 .

[0024] Furthermore, the number of the notches per unit area in at least one location of the dielectric layer is 50 / μm. 2 Up to 2000 / μm 2 .

[0025] Furthermore, the notch is at least located on the side or surface of the dielectric layer.

[0026] Furthermore, the passivation structure is provided in the N-type doping region of the silicon substrate.

[0027] An embodiment of the present invention also provides a method for preparing the solar cell described above, comprising the steps of: S1, preparing a silicon substrate; S2, depositing a dielectric layer on at least one side of the silicon substrate; S3, depositing a nitrogen-containing polysilicon film on the surface of the dielectric layer to form a first polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is 0.3 at.% to 35 at.%; S4, depositing at least one layer of polysilicon film on the surface of the first polysilicon layer to form at least one second polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is greater than the nitrogen concentration of any second polysilicon layer; and S5, doping the first polysilicon layer and the second polysilicon layer with an N-type main element.

[0028] Furthermore, in step S2, a dielectric layer is deposited on the surface of at least one side of the silicon substrate by PECVD, LPCVD, wet oxidation, or ozone oxidation; and / or, in step S3, a nitrogen-containing polycrystalline silicon film is deposited on the surface of the dielectric layer by PECVD, LPCVD, Sputtering, or E-Beam; and / or, in step S4, at least one layer of polycrystalline silicon film is deposited on the surface of the first polycrystalline silicon layer by PECVD, LPCVD, Sputtering, or E-Beam.

[0029] Furthermore, the preparation method further includes the steps of: S6, depositing an aluminum oxide film on the surface of the outermost second polysilicon layer, and then performing annealing to form a first dielectric film; S7, depositing a silicon nitride film on the surface of the first dielectric film, and then performing annealing to form a second dielectric film; S8, preparing electrodes on the surface of the second dielectric film to obtain a solar cell; S9, testing the prepared solar cell.

[0030] An embodiment of the present invention further provides a battery assembly, which includes the solar cell as described above or a solar cell prepared by the method for preparing a solar cell as described above.

[0031] An embodiment of the present invention further provides a photovoltaic system, which includes the battery assembly described above.

[0032] The solar cell in the embodiment of the present invention introduces a nitrogen-doped first polysilicon layer into its passivation structure, so that the polysilicon layer has a stress buffering function, which can effectively reduce the interfacial stress of the dielectric layer during the high-temperature passivation process and reduce the risk of gaps in the dielectric layer in the solar cell, thereby improving the passivation effect of the solar cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0034] Figure 1 is a module schematic diagram of a photovoltaic system provided by one embodiment of the present invention;

[0035] Figure 2 is a schematic diagram of a module of a battery assembly provided by one embodiment of the present invention;

[0036] Figure 3 1 is a schematic diagram of a partial structure of a solar cell provided by an embodiment of the present invention, wherein the solar cell has a second polysilicon layer;

[0037] Figure 4 It is a partial structural diagram of a solar cell provided by another embodiment of the present invention. The solar cell has multiple second polysilicon layers.

[0038] Figure 5 is a partial structural diagram of a solar cell provided by another embodiment of the present invention;

[0039] Figure 6 It is a schematic diagram of a partial structure of a dielectric layer in a solar cell provided by one embodiment of the present invention.

[0040] Figure 7 The present invention is a flowchart of a method for preparing a solar cell according to an embodiment of the present invention.

[0041] Explanation of main component symbols: 1000, photovoltaic system; 1001, battery assembly; 100, solar cell; 10, silicon substrate; 20, passivation structure; 21, dielectric layer; 22, first polysilicon layer; 23, second polysilicon layer; 30, first dielectric film; 40, second dielectric film. DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below with reference to the accompanying drawings and examples. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0043] In the description of the present invention, it should be understood that the terms "length", "width", "up", "down", "top", "bottom", "horizontal", "longitudinal", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0044] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, features defined as "first" or "second" may explicitly or implicitly include one or more of the described features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0045] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or mutual communication; direct connections or indirect connections through an intermediate medium; and internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0046] In the present invention, unless otherwise expressly specified or limited, a first feature being "above" or "below" a second feature may include the first and second features being in direct contact, or may include the first and second features being in contact not directly but through another feature between them. Furthermore, a first feature being "above," "above," and "above" a second feature may include the first feature being directly above or obliquely above the second feature, or may simply mean that the first feature is higher in level than the second feature. A first feature being "below," "below," and "below" a second feature may include the first feature being directly below or obliquely below the second feature, or may simply mean that the first feature is lower in level than the second feature.

[0047] The disclosure below provides many different embodiments or examples for realizing different structures of the present invention. In order to simplify the disclosure of the present invention, the components and settings of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. In addition, the present invention may repeat reference numbers and / or reference letters in different examples. Such repetition is for the purpose of simplicity and clarity and does not in itself indicate the relationship between the various embodiments and / or settings discussed. In addition, the present invention provides examples of various specific processes and materials, but a person of ordinary skill in the art will recognize the application of other processes and / or the use scenarios of other materials.

[0048] See also Figure 1 and Figure 2 The photovoltaic system 1000 in the embodiment of the present invention may include a battery assembly 1001 in the embodiment of the present invention. The battery assembly 1001 in the embodiment of the present invention may include a plurality of solar cells 100. The plurality of solar cells 100 may be connected in series via connectors to form a battery string. The battery strings in the battery assembly 1001 may be connected in series, in parallel, or in a combination of series and parallel to achieve current bus output. For example, bus bars may be used to connect the battery strings.

[0049] The accompanying drawings provided in this application are schematic diagrams, and some elements are not shown. This is for the purpose of clearly describing the technical solution and highlighting the key points of the invention. It is not intended to limit the technical solution to exclude these unshown elements. In other words, the accompanying drawings are merely illustrative and do not limit the specific form of battery assembly 1001.

[0050] like Figures 3 to 6As shown, the solar cell 100 in the embodiment of the present invention includes a silicon substrate 10 and a passivation structure 20 provided on at least one side of the silicon substrate 10. The passivation structure 20 includes: a dielectric layer 21, a first polysilicon layer 22 provided on the side of the dielectric layer 21 facing away from the silicon substrate 10, and at least one second polysilicon layer 23 provided on the side of the first polysilicon layer 22 facing away from the dielectric layer 21; wherein the first polysilicon layer 22 is a polysilicon layer containing nitrogen, the nitrogen concentration of at least one portion of the first polysilicon layer 22 is greater than the nitrogen concentration of any of the second polysilicon layers 23, and the nitrogen concentration of at least one portion of the first polysilicon layer 22 is in a range of 0.3 at.% to 35 at.%.

[0051] In this way, the solar cell 100 in the embodiment of the present invention introduces a nitrogen-doped first polysilicon layer 22 into its passivation structure 20, so that the first polysilicon layer 22 has a stress buffering function, which can effectively reduce the interfacial stress of the dielectric layer 21 during the high-temperature passivation process, reduce the risk of gaps 211 appearing in the dielectric layer 21 in the solar cell 100, and thus improve the passivation effect of the solar cell 100.

[0052] Furthermore, the solar cell 100 in the embodiment of the present invention can form a nitrogen content gradient design from the first polysilicon layer 22 to the second polysilicon layer 23 in the passivation structure 20 by setting the nitrogen concentration of the first polysilicon layer 22 to be greater than the nitrogen concentration of any second polysilicon layer 23. The nitrogen element can serve as a diffusion barrier structure to inhibit excessive penetration of the main dopant atoms in the polysilicon layer into the dielectric layer 21, thereby reducing the doping-induced interface defect density.

[0053] Specifically, the silicon substrate 10 has a front side and a back side facing each other. The surface of the silicon substrate 10 may have a velvet structure, and further may have a pyramid velvet structure. In this way, the silicon substrate 10 can have a light trapping effect, thereby improving the photoelectric conversion efficiency of the solar cell 100. The silicon substrate 10 of the solar cell 100 can have a single-sided velvet structure or a double-sided velvet structure, which is not limited here.

[0054] Furthermore, in the solar cell 100 of the present invention, the front and / or back surface of the silicon substrate 10 may have a pyramid velvet surface. The silicon substrate 10 may be a P-type silicon substrate 10 or an N-type silicon substrate 10, without limitation. In the embodiment of the present invention, the silicon substrate 10 is described as an N-type silicon substrate 10.

[0055] like Figure 5As shown, the solar cell 100 of the present invention further includes a first dielectric film 30 disposed on the surface of the second polysilicon layer 23, and a second dielectric film 40 disposed on the surface of the first dielectric film 30. The provision of the first dielectric film 30 can passivate the recombination centers on the silicon surface, thereby reducing the surface recombination rate, increasing the open circuit voltage of the solar cell 100, and thus improving the efficiency of the solar cell 100.

[0056] Furthermore, the second dielectric film 40 can provide an additional passivation effect on the basis of the first dielectric film 30, thereby improving the passivation effect of the solar cell 100. Furthermore, the second dielectric film 40 can also serve as an anti-reflection layer for the solar cell 100, thereby improving the light absorption rate of the solar cell 100 and further improving the photoelectric conversion efficiency of the solar cell 100.

[0057] The passivation structure 20 of the solar cell 100 can be provided on the front surface of the silicon substrate 10. Alternatively, the passivation structure 20 of the solar cell 100 can also be provided on the back surface of the silicon substrate 10. Alternatively, the passivation structure 20 of the solar cell 100 can also be provided on both the front and back surfaces of the silicon substrate 10, which is not limited here. Specifically, the passivation structure 20 of the solar cell 100 can be provided on the pyramid velvet surface of the silicon substrate 10 by deposition.

[0058] Furthermore, the thickness of the silicon substrate 10 may be 120 μm to 200 μm, for example, 120 μm, 130 μm, 140 μm, 150 μm, 160 μm, 170 μm, 180 μm, 190 μm, or 200 μm.

[0059] Furthermore, the resistivity of the silicon substrate 10 may be 1 Ω·cm to 7 Ω·cm, for example, 1 Ω·cm, 2 Ω·cm, 3 Ω·cm, 4 Ω·cm, 5 Ω·cm, 6 Ω·cm, or 7 Ω·cm.

[0060] The types of solar cells 100 in the embodiments of the present application include, but are not limited to, Passivated Emitter Rear Cell (PERC), Tunnel Oxide Passivated Contact (TOPCon), Heterojunction with Intrinsic Thin-layer (HIT), Back Contact (BC), Perovskite Solar Cells (PSC), etc. The types of solar cells 100 in the present embodiment are not specifically limited.

[0061] Specifically, the solar cell 100 in the embodiment of the present application can be a sliced ​​cell. A sliced ​​cell refers to a cell formed by a complete whole cell through a cutting process. The cutting process includes: laser grooving + cutting (Linear Spectral Clustering, LSC) process and thermal stress cell separation (TMC) process. In some embodiments, the sliced ​​cell can be a half-cell cell, and a half-cell cell can also be understood as a half-cell or a two-cell cell. In some embodiments, the solar cell 100 can be a 2-cell cell, a 3-cell cell, a 4-cell cell or an 8-cell cell, etc.

[0062] It is understandable that in the prior art, the high-temperature annealing process accompanying the polysilicon deposition process induces interfacial stress in the single-crystal silicon / silicon oxide / polysilicon structure, which can cause cracks in the dielectric layer 21 and form notches 211 defects in the dielectric layer 21. Furthermore, EBIC characterization confirms that the interfacial notches 211 defects in the dielectric layer 21 can trigger significant carrier recombination effects, forming characteristic dark areas and significantly reducing the effective passivation area on the surface of the silicon substrate 10.

[0063] It can be understood that "interface stress" refers to the intrinsic mechanical stress generated during the manufacturing or working process at the interface between two or more different materials due to the differences in thermal expansion coefficient, lattice structure or mechanical properties between the materials. In the polysilicon deposition process, because the thermal expansion coefficients of the polysilicon layer and the dielectric layer 21 are different, the materials of the polysilicon layer and the dielectric layer 21 shrink asynchronously during the annealing and cooling process, and then stress concentration is generated at the interface between the polysilicon layer and the dielectric layer 21, forming "interface stress". This stress may cause microstructural changes at the interface between the polysilicon layer and the dielectric layer 21, such as cracks on the surface of the dielectric layer 21 and the formation of gaps 211, thereby weakening the passivation effect of the solar cell 100, increasing carrier recombination, and affecting the overall performance stability and conversion efficiency of the solar cell 100.

[0064] Based on the above technical problems, the solar cell 100 of the present application introduces a first polysilicon layer 22 into its passivation structure 20, introduces nitrogen into the first polysilicon layer 22, and sets the nitrogen concentration of at least one first polysilicon layer 22 to be greater than the nitrogen atoms in any second polysilicon layer 23. The introduction of nitrogen atoms can effectively adjust the internal stress distribution of the polysilicon layer, alleviate the interface stress generated on the surface of the dielectric layer 21 due to thermal expansion differences during the passivation process, thereby reducing the risk of cracks or gaps 211 in the dielectric layer 21, improving the stability of the surface structure of the dielectric layer 21, and ultimately effectively improving the passivation effect and overall performance of the solar cell 100. The nitrogen element can also act as a diffusion barrier structure to inhibit the excessive penetration of the main dopant atoms in the polysilicon layer into the dielectric layer 21, thereby reducing the density of doping-induced interface defects.

[0065] It can be understood that the radius of a nitrogen atom is smaller than that of a silicon atom. In the first polysilicon layer 22, nitrogen atoms will enter the gaps or replace the silicon lattice. The nitrogen element significantly reduces the interface between the dielectric layer 21 and the first polysilicon layer 22, as well as defects such as dangling bonds and vacancies in the first polysilicon layer 22, by replacing silicon atoms in the silicon lattice or filling grain boundary defects, thereby reducing the interface defect density.

[0066] Furthermore, nitrogen acts as a diffusion barrier, effectively inhibiting excessive penetration of the main dopant atoms in the polysilicon layer into the dielectric layer 21, thereby preventing excessive accumulation and uneven concentration of dopant elements at the interface between the dielectric layer 21 and the polysilicon layer. This control helps reduce the generation of doping-induced interface defects, such as lattice distortion and carrier recombination centers caused by impurity aggregation, thereby significantly reducing interface defect density, improving the quality of the passivation layer, and improving the performance stability of the solar cell 100.

[0067] Moreover, nitrogen atoms can also change the lattice constant and internal stress state of the polysilicon layer, so that the first polysilicon layer 22 has a more uniform stress distribution, thereby playing a buffering role when the temperature suddenly changes or the stress is concentrated, reducing the stress impact on the dielectric layer 21, thereby reducing the risk of cracks or gaps 211 in the dielectric layer 21, improving the stability of the surface structure of the dielectric layer 21, and ultimately effectively improving the passivation effect and overall performance of the solar cell 100.

[0068] In addition, after nitrogen atoms are doped into the first polysilicon layer 22, the nitrogen atoms can inhibit the growth of polysilicon grains, allowing the first polysilicon layer 22 to form a denser and more uniform microstructure, thereby improving the mechanical flexibility and toughness of the first polysilicon layer 22, thereby enhancing its ability to absorb and release thermal stress or interface stress. This can further reduce the interface stress generated by the first polysilicon layer 22 on the surface of the dielectric layer 21 during the passivation process, further reduce the risk of cracks or gaps 211 in the dielectric layer 21, further improve the stability of the surface structure of the dielectric layer 21, and ultimately effectively improve the passivation effect and overall performance of the solar cell 100.

[0069] Furthermore, the nitrogen concentration of at least one portion of the first polysilicon layer 22 is 0.3 at.% to 35 at.%, for example, 0.3 at.%, 0.5 at.%, 0.8 at.%, 0.9 at.%, 1 at.%, 1.5 at.%, 5 at.%, 10 at.%, 15 at.%, 20 at.%, 25 at.%, 30 at.%, or 35 at.%.

[0070] In this way, the interfacial stress at the interface of the first polysilicon layer 22 can be effectively reduced while ensuring the conductivity of the first polysilicon layer 22. It is understood that when the nitrogen concentration of the first polysilicon layer 22 is less than 0.3 at.%, the amount of nitrogen element is insufficient, and it cannot effectively serve as a diffusion barrier structure to inhibit excessive penetration of the main dopant atoms in the polysilicon layer into the dielectric layer 21, thereby making it impossible to effectively reduce the interfacial stress at the interface between the dielectric layer 21 and the first polysilicon layer 22. When the nitrogen concentration of the first polysilicon layer 22 is greater than 35 at.%, the doping concentration of the main dopant atoms (such as phosphorus or boron) in the first polysilicon layer 22 is insufficient, thereby affecting the carrier concentration and conductivity of the first polysilicon layer 22.

[0071] Therefore, the passivation structure 20 of the solar cell 100 of the present application is configured such that the first polysilicon layer 22 is a polysilicon layer containing nitrogen. The nitrogen concentration of at least one portion of the first polysilicon layer 22 is greater than the nitrogen concentration of any of the second polysilicon layers 23. The nitrogen concentration of at least one portion of the first polysilicon layer 22 is between 0.3 at.% and 35 at.%. The surface recombination current density of the improved solar cell 100 of the present application was reduced to 0.7 fA / cm3 using a Sinton minority carrier lifetime tester. 2 Up to 9.5 fA / cm 2 Compared with the surface recombination current density of the conventional solar cell 100 (23.0fA / cm 2 Up to 29.5 fA / cm 2 ), the solar cell 100 in the present application greatly reduces the surface recombination current density, thereby greatly improving the passivation level of the solar cell 100, making the passivation index of the suede structure of the solar cell 100 equivalent to the planar passivation index.

[0072] like Figures 3 to 5 As shown, in one possible embodiment, the nitrogen concentration of at least one first polysilicon layer 22 is 0.5 at.% to 25 at.%. For example, it is 0.5 at.%, 0.8 at.%, 0.9 at.%, 1 at.%, 1.5 at.%, 5 at.%, 10 at.%, 15 at.%, 20 at.%, and 25 at.%. On the one hand, the nitrogen content within this concentration range is sufficient to fill the grain boundaries and passivate dangling bonds in the first polysilicon layer 22, thereby reducing the interface defect density. On the other hand, it avoids the inhibition of the doping efficiency of the main doping atoms (such as phosphorus) caused by excessive nitrogen content, ensuring that the first polysilicon layer 22 has good carrier concentration and conductivity. At the same time, this concentration range is conducive to constructing a reasonable nitrogen content gradient distribution, which not only improves the stress buffering capacity at the interface, but also enhances the diffusion inhibition effect on the main doping atoms, effectively improving the passivation effect of the solar cell 100, thereby improving the cell efficiency of the solar cell 100.

[0073] It is understood that the “nitrogen concentration of the first polysilicon layer 22 ” refers to the atomic ratio of nitrogen in the first polysilicon layer 22 , that is, the percentage of nitrogen atoms in all atoms in the first polysilicon layer 22 .

[0074] Furthermore, the overall structure of the solar cell 100 can be inspected using a scanning electron microscope (SEM). Furthermore, the element content of each layer of the passivation structure 20 in the solar cell 100 can be measured using secondary ion mass spectrometry, X-ray photoelectron spectroscopy, or energy dispersive spectroscopy (EDS).

[0075] In a possible embodiment, the passivation structure 20 is disposed in the N-type doping region of the silicon substrate 10 .

[0076] In one possible embodiment, the thickness of the dielectric layer 21 is 1 nm to 4 nm. For example, it is 1 nm, 1.5 nm, 2 nm, 3.5 nm, and 4 nm. In this way, while avoiding the dielectric layer 21 from having an excessively high resistivity, the dielectric layer 21 can effectively resist the film rupture caused by the deformation of the velvet base of the silicon substrate 10 during the high-temperature annealing process, thereby maintaining the structural integrity of the pyramid top. It is understandable that when the thickness of the dielectric layer 21 is greater than 4 nm, the resistivity of the dielectric layer 21 will be greater, thereby reducing the cell efficiency of the solar cell 100. When the thickness of the dielectric layer 21 is less than 1 nm, the dielectric layer 21 will not have sufficient mechanical strength, and thus will not be able to resist the film rupture that may be caused by the deformation of the silicon substrate 10 during the high-temperature annealing process.

[0077] Furthermore, the thickness of the dielectric layer 21 is 1.5 nm to 2.5 nm. For example, it is 1.5 nm, 2 nm, and 2.5 nm. In this way, the dielectric layer 21 can achieve an excellent balance between mechanical strength, electrical performance, and process feasibility. It is understandable that, on the one hand, when the thickness of the dielectric layer 21 is not less than 1.5 nm, the dielectric layer 21 can have basic structural continuity and mechanical strength, and can effectively resist the stress concentration and deformation generated by the pyramid velvet structure of the silicon substrate 10 during the high-temperature annealing process, thereby avoiding failure problems such as cracking and perforation of the dielectric layer 21 film, and ensuring the integrity and long-term reliability of the passivation structure 20. On the other hand, the thickness of the dielectric layer 21 does not exceed 2.5 nm, so that the dielectric layer 21 can still maintain high-quality tunneling performance, which is beneficial to the injection of carriers from the silicon substrate into the doped polysilicon, thereby reducing the contact resistance of the dielectric layer 21 and avoiding the dielectric layer 21 being too thick, resulting in an excessively high resistivity. In addition, if the thickness of the dielectric layer 21 is less than 1.5 nm, the dielectric layer 21 is very low. If the thickness of the dielectric layer 21 is greater than 2.5 nm, the material cost of the dielectric layer 21 will also increase.

[0078] In a possible embodiment, the dielectric layer 21 may be a silicon oxide (SiO) dielectric layer 21, a hydrogenated silicon oxide (SiO x :H) dielectric layer 21, silicon oxynitride (SiO x N γ ) dielectric layer 21 or silicon oxycarbide (SiO x C γ ) one of the dielectric layers 21.

[0079] Specifically, the material of the dielectric layer 21 can be silicon oxide, hydrogenated silicon oxide, silicon oxynitride, or silicon oxycarbide. The specific material of the dielectric layer 21 can be selected based on process compatibility, passivation effect, or interface stability, and is not limited here.

[0080] For example, the dielectric layer 21 made of silicon oxide has the characteristics of high thermal stability and low interface state density, which can enable the solar cell 100 to have a good passivation effect.

[0081] For example, the dielectric layer 21 made of hydrogenated silicon oxide has good flexibility, a certain stress buffering capability, and is more suitable for the textured silicon substrate 10 .

[0082] For example, the dielectric layer 21 made of silicon oxynitride has excellent thermal stability, and can improve the stability of the passivation structure 20 of the solar cell 100 .

[0083] For example, the dielectric layer 21 made of silicon oxycarbide has a certain resistance to moisture and heat, and can improve the stability of the passivation structure 20 of the solar cell 100 .

[0084] like Figures 3 to 5 As shown, in one possible embodiment, the thickness of the first polysilicon layer 22 is 3nm to 60nm. For example, 3nm, 5nm, 8nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, 40nm, 45nm, 50nm, 55nm, 60nm. In this way, the first polysilicon layer 22 can achieve coordinated optimization of stress buffering and conductivity. It is understandable that when the thickness of the first polysilicon layer 22 is greater than 60nm, the resistivity of the first polysilicon layer 22 will be larger, thereby reducing the battery efficiency of the solar cell 100. When the thickness of the first polysilicon layer 22 is less than 3nm, the nitrogen atoms in the first polysilicon layer 22 will not be able to effectively reduce the interface stress, thereby affecting the passivation effect and overall performance of the solar cell 100.

[0085] Furthermore, the thickness of the first polysilicon layer 22 is 5nm to 40nm. For example, it is 5nm, 8nm, 10nm, 15nm, 20nm, 25nm, 30nm, 35nm, and 40nm. In this way, the first polysilicon layer 22 can take into account both structural stability and the stability of conductive efficiency. On the one hand, the thickness of the first polysilicon layer 22 is not less than 5nm, which can ensure that the first polysilicon layer 22 forms a continuous and structurally complete stress buffer layer, effectively alleviating the thermal stress concentration caused by the pyramid velvet structure on the surface of the silicon substrate 10, and reducing the formation of defects such as local cracks or gaps 211 in the dielectric layer 21; on the other hand, the thickness of the first polysilicon layer 22 does not exceed 40nm, which can also avoid the widening of the carrier tunneling barrier caused by the excessive thickness of the polysilicon layer, thereby causing the contact resistance to increase, affecting the electrical performance of the solar cell 100.

[0086] In one possible embodiment, the thickness of the second polysilicon layer 23 is greater than 15 nm, such as 18 nm, 20 nm, 25 nm, 30 nm, 50 nm, 55 nm, 60 nm, or 70 nm. This helps improve the overall passivation effect of the solar cell 100, thereby increasing the efficiency of the solar cell 100.

[0087] Furthermore, the thickness of the second polysilicon layer 23 is greater than 30nm. For example, it is 35nm, 40nm, 45nm, 50nm, 55nm, 60nm, and 70nm. In this way, on the one hand, the thickness of the second polysilicon layer 23 is greater than 30nm, which can ensure that the second polysilicon layer 23 has a stable and continuous structure, which is conducive to improving the passivation quality of the passivation structure 20 and improving the overall stability and interface passivation effect of the passivation structure 20. Secondly, as a lateral conductive layer, the second polysilicon layer 23 needs to rely on the high carrier mobility of its material itself to achieve efficient lateral transport of carriers, thereby reducing the series resistance and improving the overall conductive efficiency; if the thickness of the second polysilicon layer 23 is too thin, it may cause current to accumulate in a local area, resulting in a current congestion effect, thereby causing hot spots, increased losses, and even device failure. Therefore, setting the thickness of the second polysilicon layer 23 to be greater than 30nm can effectively improve the efficiency of the solar cell 100.

[0088] Furthermore, if Figure 3 As shown, the number of the second polysilicon layer 23 can be one; or Figure 4 As shown, the number of the second polysilicon layers 23 may also be multiple, which is not limited here.

[0089] In one possible embodiment, the N-type main element concentration of at least one first polysilicon layer 22 is lower than the N-type main element concentration of any second polysilicon layer 23. Thus, in the technical solution of the present invention, by setting the N-type main dopant atom concentration of at least one first polysilicon layer 22 to be lower than the N-type main dopant atom concentration of any second polysilicon layer 23, it is helpful to achieve layered optimization of doping functions in the passivation structure 20: the first polysilicon layer 22, due to its lower N-type main element doping concentration, can effectively reduce the density of doping-induced interface defects, improve the interface passivation quality between the dielectric layer 21 and the silicon substrate 10, and reduce the penetration of main dopant atoms into the dielectric layer 21, thereby enhancing the stability of the passivation structure 20. Meanwhile, the second polysilicon layer 23, as the main lateral conductive layer, maintains a higher N-type main dopant atom concentration, providing sufficient carrier density and good conductivity, ensuring efficient lateral current transmission. This doping gradient design not only achieves a division of labor and synergy between the passivation and conductive functions, but also forms a moderate electric field in the vertical direction, which helps to accelerate carrier separation and transmission, thereby improving the overall efficiency of the solar cell 100.

[0090] Specifically, the N-type main element may be phosphorus, arsenic, antimony or other elements, which are not limited here. In the embodiment of the present invention, the N-type main element is described as phosphorus.

[0091] In a possible embodiment, the doping concentration of the N-type main element in at least one first polysilicon layer 22 is 1.5×10 18 cm-3 to 8×10 20 cm -3 For example, 1.5×10 18 cm -3 , 1.8×10 18 cm -3 , 2×10 18 cm -3 , 2.2×10 18 cm -3 , 2×10 19 cm -3 , 2.5×10 19 cm -3 , 3×10 19 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 3.5×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 , 8×10 20 cm -3 In this way, the first polysilicon layer 22 can have sufficient conductivity, so that the first polysilicon layer 22 can play a role in stress buffering and defect suppression while still having a certain charge transport capacity, thereby preventing the first polysilicon layer 22 from having an excessively high resistivity due to an excessively low N-type main element doping concentration, thereby affecting the overall electrical performance of the device.

[0092] Furthermore, the doping concentration of the N-type main element in at least one first polysilicon layer 22 is 5×10 18 cm -3 to 3×10 20 cm -3 For example, 1×10 18 cm -3 , 2×10 18 cm -3 , 3×10 18 cm -3 , 4×10 18 cm -3 , 5×10 18 cm -3 , 1×10 19 cm -3 , 1.1×10 19 cm -3 , 1.2×10 19cm -3 , 1.3×10 19 cm -3 , 1.4×10 19 cm -3 , 1.5×10 19 cm -3 , 1×10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 In this way, it is possible to further ensure that the first polysilicon layer 22 has a certain conductivity while effectively avoiding the problems of increased defect density and stress concentration caused by high doping.

[0093] In a possible embodiment, the doping concentration of the N-type main element in at least one second polysilicon layer 23 is 1.5×10 20 cm -3 to 1×10 21 cm -3 For example, 1.5×10 20 cm -3 , 1.8×10 20 cm -3 , 2×10 20 cm -3 , 2.2×10 20 cm -3 , 0.3×10 21 cm -3 , 0.5×10 21 cm -3 , 0.6×10 21 cm -3 , 0.7×10 21 cm -3 , 0.8×10 21 cm -3 , 1×10 21 cm -3 In this way, the second polysilicon layer 23 can have sufficient conductivity and passivation capabilities.

[0094] Furthermore, the doping concentration of the N-type main element in at least one second polysilicon layer 23 is 1×10 20 cm -3 to 0.8×10 21 cm -3 For example, 1×10 20 cm -3 , 1.1×10 20 cm -3 , 1.2×10 20 cm-3 , 1.5×10 20 cm -3 , 1.6×10 20 cm -3 , 2×10 20 cm -3 , 0.4×10 21 cm -3 , 0.5×10 21 cm -3 , 0.8×10 21 cm -3 . In this way, it helps to significantly improve the conductive properties of the second polysilicon layer 23, so that the second polysilicon layer 23 has a lower resistivity when used as the main conductive layer, thereby effectively realizing the rapid lateral transmission of carriers. It can be understood that a higher concentration of N-type main element (such as phosphorus, arsenic or antimony) doping can form a stable high free carrier density in the second polysilicon layer 23, reduce the ohmic contact resistance, and enhance the function of the second polysilicon layer 23 as a charge selection layer and current collection channel. In addition, the second polysilicon layer 23 is farther away from the dielectric layer 21 than the first polysilicon layer 22, and the high concentration of N-type main element in the second polysilicon layer 23 will not significantly affect the defect density of the passivation interface, thereby ensuring the conductivity of the second polysilicon layer 23 while not affecting the passivation effect of the solar cell 100.

[0095] In one possible embodiment, the nitrogen concentration of the second polysilicon layer 23 is 0.001 at.% to 10 at.%, for example, 0.001 at.%, 0.005 at.%, 0.01 at.%, 0.05 at.%, 0.08 at.%, 0.1 at.%, 0.2 at.%, 0.5 at.%, 0.8 at.%, 1 at.%, 1.2 at.%, 1.5 at.%, 1.8 at.%, 2 at.%, 5 at.%, 8 at.%, or 10 at.%.

[0096] For example, the content of nitrogen is 0, 0.05 at.%, 0.08 at.%, 0.1 at.%, 0.12 at.%, 0.15 at.%, 0.18 at.%, and 0.2 at.%. In this way, a moderate improvement in structural stability can be achieved while ensuring the crystal quality and conductivity of the second polysilicon layer 23. Specifically, a relatively low content of nitrogen can act as a lattice stabilizer, thereby suppressing grain boundary migration and stress concentration to a certain extent, reducing lattice defects in the second polysilicon layer 23, and will not significantly reduce the doping concentration of the N-type main element in the second polysilicon layer 23, thereby helping to improve the thermal stability and density of the second polysilicon layer 23.

[0097] It can be understood that by doping appropriate nitrogen elements into the second polysilicon layer 23, the gain of nitrogen elements as a lattice stabilizer on the second polysilicon layer 23 can compensate for the defects caused by the reduction of the N-type main element in the second polysilicon layer 23 after the second polysilicon layer 23 is doped with nitrogen elements.

[0098] Preferably, the nitrogen concentration of the second polysilicon layer 23 is 0.001 at.% to 0.2 at.%. This can further reduce lattice defects in the second polysilicon layer 23 without excessively reducing the doping concentration of the N-type main element in the second polysilicon layer 23, thereby affecting the conductivity of the second polysilicon layer 23 and improving the thermal stability and density of the second polysilicon layer 23.

[0099] It is understood that the “nitrogen concentration of the second polysilicon layer 23 ” refers to the atomic ratio of nitrogen in the second polysilicon layer 23 , that is, the percentage of nitrogen atoms in all atoms in the second polysilicon layer 23 .

[0100] In one possible embodiment, the nitrogen concentration of the second polysilicon layer 23 is 0. Thus, when the nitrogen concentration of the second polysilicon layer 23 is 0, the doping concentration of the N-type main element in the second polysilicon layer 23 can be increased, thereby improving the conductive effect of the second polysilicon layer 23.

[0101] Specifically, for each second polysilicon layer 23 , the second polysilicon layer 23 may be a conventional polysilicon thin film that does not contain nitrogen, or the second polysilicon layer 23 may also be a polysilicon thin film that contains nitrogen, which is not limited here.

[0102] Please refer to Figure 6 In one possible embodiment, the dielectric layer 21 includes a plurality of notches 211 , and the number of notches 211 per unit area in at least one location of the dielectric layer 21 is 10 / μm 2 Up to 5000 pieces / μm 2 For example, 10 / μm 2 , 20 / μm 2 , 30 / μm 2 , 50 / μm 2 , 100 / μm 2 , 500 / μm 2 , 800 / μm 2 , 1000 / μm 2 , 1500 / μm 2 , 1800 / μm 2 , 2000 / μm 2 , 2500 / μm 2 , 3000 / μm 2 , 3500 / μm 2, 4000 / μm 2 , 4500 / μm 2 , 5000 / μm 2 In this way, the structural stability of the dielectric layer can be improved, thereby improving the passivation effect of the dielectric layer, increasing the carrier transmission capacity, and thus improving the cell efficiency of the solar cell. Furthermore, the notch 211 is at least located on the side or surface of the dielectric layer 21.

[0103] In addition, the dielectric layer 21 can be subjected to surface testing and cross-sectional testing by means of SEM (Scanning Electron Microscope), secondary ion mass spectrometry, X-ray photoelectron spectroscopy, energy dispersive spectrometer (EDS) testing, or silicon wafer pinhole and surface defect testing instruments, thereby qualitatively or quantitatively detecting the number of notches 211 in the dielectric layer 21.

[0104] It is understandable that the notch 211 in the dielectric layer 21 may refer to a through notch 211 of the dielectric layer or a non-through notch 211 of the dielectric layer, which is not limited herein.

[0105] It can be understood that the notch 211 of the dielectric layer 21 may specifically include a structural fracture formed by a physical fracture of the dielectric layer 21 at a macro or micro scale; the notch 211 of the dielectric layer 21 may specifically include a surface damage formed by local peeling or scratching on the surface or side of the dielectric layer 21; the notch 211 of the dielectric layer 21 may specifically include a pinhole, which may specifically be cylindrical or funnel-shaped.

[0106] Furthermore, the equivalent circular area diameter of the notch 211 is 0.05 nm to 10 nm, for example, 0.05 nm, 0.1 nm, 0.5 nm, 0.8 nm, 1 nm, 2 nm, 5 nm, 8 nm, or 10 nm. It is understood that the equivalent circular area diameter of the notch 211 refers to the diameter of a circle having the same area as the projection image of the notch 211.

[0107] Furthermore, the number of the notches 211 per unit area of ​​at least one of the dielectric layer 21 is 50 / μm. 2 Up to 2000 / μm 2 For example, 50 pieces / μm 2 , 100 / μm 2 , 500 / μm 2 , 800 / μm 2 , 1000 / μm 2 , 1500 / μm 2 , 1800 / μm 2 , 2000 / μm 2 .

[0108] Please refer to Figure 7 The embodiment of the present invention also provides a method for preparing the solar cell 100 described above. The method for preparing the solar cell 100 includes the following steps: S1, preparing a silicon substrate; S2, depositing a dielectric layer on at least one side of the silicon substrate; S3, depositing a nitrogen-containing polysilicon thin film on the surface of the dielectric layer to form a first polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is 0.3 at.% to 35 at.%; S4, depositing at least one polysilicon thin film on the surface of the first polysilicon layer to form at least one second polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is greater than the nitrogen concentration of any second polysilicon layer; S5, phosphorus-doping the first polysilicon layer and the second polysilicon layer.

[0109] Thus, the method for preparing the solar cell 100 provided in an embodiment of the present invention forms the first polysilicon layer 22 by depositing a nitrogen-containing polysilicon film on the surface of the dielectric layer 21, so that the first polysilicon layer 22 has a stress buffering function, thereby reducing the interfacial stress on the surface of the dielectric layer 21 during the passivation process of the solar cell 100, reducing the risk of the dielectric layer 21 in the solar cell 100 breaking and forming a gap 211, thereby improving the passivation effect of the solar cell 100.

[0110] like Figures 3 to 7 As shown, the method for preparing solar cell 100 includes step S1, preparing a silicon substrate. Specifically, silicon substrate 10 can be an N-type substrate or a P-type substrate, and at least one side of silicon substrate 10 has a pyramid velvet surface. During the preparation of silicon substrate 10, silicon substrate 10 can be cleaned, specifically by using a standard RCA cleaning method to clean silicon substrate 10.

[0111] The method for preparing the solar cell 100 further includes step S2 , depositing a dielectric layer on at least one side of the silicon substrate.

[0112] Specifically, after the silicon substrate 10 is prepared, a dielectric layer 21 may be deposited on the pyramid surface of the silicon substrate 10 .

[0113] The dielectric layer 21 can be deposited on at least one side of the silicon substrate 10 by PECVD (Plasma-Enhanced Chemical Vapor Deposition), LPCVD (Low-Pressure Chemical Vapor Deposition), wet oxidation, or ozone oxidation in an oxygen atmosphere. Dielectric layer 21 can be made of materials such as silicon oxide, hydrogenated silicon oxide, silicon oxynitride, or silicon oxycarbide to provide excellent interface passivation and tunneling performance, while maintaining structural stability during subsequent high-temperature processes.

[0114] For example, when the user deposits the dielectric layer 21 in a PECVD manner, the silicon substrate 10 may be placed in an environment with a temperature of 200° C. to 400° C. for low-temperature deposition.

[0115] For example, when the user deposits the dielectric layer 21 in a LPCVD manner, the silicon substrate 10 may be placed in an environment with a temperature of 400° C. to 1000° C. for medium-high temperature deposition.

[0116] like Figures 3 to 7 As shown, the method for preparing the solar cell 100 further includes step S3, depositing a nitrogen-containing polysilicon film on the surface of the dielectric layer to form a first polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is 0.3 at.% to 35 at.%.

[0117] Specifically, after preparing the dielectric layer 21, a nitrogen-containing polysilicon film can be deposited on the surface of the dielectric layer 21 by PECVD, LPCVD, sputtering, or E-Beam to form the first polysilicon layer 22. The nitrogen concentration in the first polysilicon layer 22 is controlled within a range of 0.3 at.% to 35 at.%. Thus, the introduction of nitrogen can effectively inhibit the diffusion of primary dopant atoms (such as phosphorus or boron) into the dielectric layer 21, reduce the density of doping-induced interface defects, and enhance the passivation effect of the solar cell 100.

[0118] Furthermore, when depositing the first polysilicon layer 22, SiH2Cl2 and NH3 may be used as source gases.

[0119] Alternatively, SiH 4 and N 2 O may be used as source gases, so that the nitrogen-rich first polysilicon layer 22 may be deposited on the surface of the dielectric layer 21 .

[0120] For example, when the user deposits the first polysilicon layer 22 in a PECVD manner, the silicon substrate 10 may be placed in an environment with a temperature of 200° C. to 600° C. for low-temperature deposition.

[0121] For example, when the user deposits the first polysilicon layer 22 in a LPCVD manner, the silicon substrate 10 may be placed in an environment with a temperature of 400° C. to 700° C. for medium-high temperature deposition.

[0122] The method for preparing the solar cell 100 further includes step S4, depositing at least one polysilicon thin film on the surface of the first polysilicon layer to form at least one second polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is greater than the nitrogen concentration of any second polysilicon layer.

[0123] Specifically, after preparing the first polysilicon layer 22, at least one layer of polysilicon thin film may be deposited on the surface of the first polysilicon layer 22 by PECVD, LPCVD, Sputtering, or E-Beam to form at least one second polysilicon layer 23. Furthermore, the nitrogen concentration of the first polysilicon layer 22 is greater than the nitrogen concentration of any second polysilicon layer 23. The second polysilicon layer 23 may be configured to have a lower nitrogen content or no nitrogen content, thereby ensuring the lateral conductivity of the second polysilicon layer 23 and improving the overall carrier collection efficiency of the solar cell 100.

[0124] For example, when depositing the second polysilicon layer 23 , SiH 4 may be used as a source gas, so that the second polysilicon layer 23 not containing nitrogen may be deposited on the surface of the first polysilicon layer 22 .

[0125] For example, when depositing the second polysilicon layer 23 , SiH 2 Cl 2 and NH 3 may be used as source gases, or SiH 4 and N 2 O may be used as source gases, so that the nitrogen-rich second polysilicon layer 23 may be deposited on the surface of the first polysilicon layer 22 .

[0126] Furthermore, when the user deposits the second polysilicon layer 23 by PECVD, the silicon substrate 10 can be placed in an environment with a temperature of 200°C to 600°C for low-temperature deposition. Alternatively, when the user deposits the second polysilicon layer 23 by LPCVD, the silicon substrate 10 can be placed in an environment with a temperature of 400°C to 700°C for medium-high-temperature deposition.

[0127] like Figures 3 to 7 As shown, the method for preparing the solar cell 100 further includes step S5 , doping the first polysilicon layer and the second polysilicon layer with phosphorus.

[0128] Specifically, after the second polysilicon layer 23 is prepared, the first polysilicon layer 22 and the second polysilicon layer 23 may be doped with an N-type main element. The N-type main element may specifically be phosphorus, arsenic, or antimony. In the embodiment of the present invention, phosphorus doping of the first polysilicon layer 22 and the second polysilicon layer 23 is described.

[0129] Furthermore, N-type main elements may be introduced into the first polysilicon layer 22 and the second polysilicon layer 23 by ion implantation or diffusion, so that the first polysilicon layer 22 and the second polysilicon layer 23 have good conductivity and carrier selectivity.

[0130] Furthermore, when the first polysilicon layer 22 and the second polysilicon layer 23 are doped with N-type main elements, the silicon substrate 10 on which the first polysilicon layer 22 and the second polysilicon layer 23 are deposited can be transferred to a tubular diffusion furnace, and POCl3, AsH or SbH can be used as dopants to perform N-type main element diffusion in a temperature environment of 700°C to 1000°C.

[0131] For example, POCl 3 may be used as a dopant to diffuse phosphorus.

[0132] For example, AsH may be used as a dopant to perform arsenic diffusion.

[0133] For example, SbH may be used as a dopant to perform antimony element diffusion.

[0134] like Figures 3 to 7 As shown, the method for preparing the solar cell 100 further includes the following steps: S6, depositing an aluminum oxide film on the surface of the outermost second polysilicon layer, and then performing an annealing treatment to form a first dielectric film; S7, depositing a silicon nitride film on the surface of the first dielectric film, and then performing an annealing treatment to form a second dielectric film; S8, preparing an electrode on the surface of the second dielectric film to obtain a solar cell; and S9, testing the prepared solar cell.

[0135] like Figures 3 to 7 As shown, the method for preparing the solar cell 100 further includes the step: S6, depositing an aluminum oxide film on the surface of the outermost second polysilicon layer, and then performing an annealing process to form a first dielectric film.

[0136] Specifically, after the first polysilicon layer 22 and the second polysilicon layer 23 are doped with an N-type main element, an aluminum oxide film may be deposited on the surface of the outermost second polysilicon layer 23 and then annealed to form the first dielectric film 30 .

[0137] Furthermore, when depositing the aluminum oxide film, ALD, PECVD, or LPCVD can be used. The silicon substrate 10 with the aluminum oxide film deposited thereon is then placed in a tube furnace and annealed at 300° C. to 450° C. for 20 to 50 minutes, thereby growing the first dielectric film 30 on the surface of the outermost second polysilicon layer 23.

[0138] Furthermore, the thickness of the first dielectric film 30 can be controlled within a range of 5 nm to 20 nm. The provision of the first dielectric film 30 can passivate the recombination centers on the silicon surface, thereby reducing the surface recombination rate and increasing the open circuit voltage of the solar cell 100, thereby improving the efficiency of the solar cell 100.

[0139] The method for manufacturing the solar cell 100 further includes the step: S7 , depositing a silicon nitride thin film on the surface of the first dielectric film, and then performing an annealing process to form a second dielectric film.

[0140] Specifically, after the first dielectric film 30 is prepared, a silicon nitride film may be deposited on the surface of the first dielectric film 30 , and then annealed to form the second dielectric film 40 .

[0141] Furthermore, when depositing the aluminum oxide film, the silicon nitride film can be deposited using ALD, PECVD, or LPCVD. The silicon substrate 10 with the silicon nitride film deposited thereon is then placed in a tube furnace and annealed in a nitrogen and hydrogen mixed gas atmosphere at 300° C. to 450° C. for 50 to 70 minutes, thereby growing the second dielectric film 40 on the growth surface of the first dielectric film 30.

[0142] Furthermore, the thickness of the second dielectric film 40 can be controlled within a range of 60 nm to 100 nm. The second dielectric film 40 can provide an additional passivation effect on top of the first dielectric film 30, thereby improving the passivation effect of the solar cell 100. Furthermore, the second dielectric film 40 can also serve as an anti-reflection layer for the solar cell 100, thereby increasing the light absorption rate of the solar cell 100 and, in turn, the photoelectric conversion efficiency of the solar cell 100.

[0143] like Figures 3 to 7 As shown, the method for preparing the solar cell 100 further includes the step: S8, preparing an electrode on the surface of the second dielectric film to obtain a solar cell.

[0144] Specifically, after the second dielectric film 40 is prepared, an electrode may be prepared on the surface of the second dielectric film 40 . Finally, after the second dielectric film 40 is prepared, the solar cell 100 may be cleaned to obtain a complete solar cell 100 .

[0145] Furthermore, the electrode formed on the surface of the second dielectric film 40 may be a main gate and / or a fine gate, which is not limited here.

[0146] like Figures 3 to 7 As shown, the method for preparing the solar cell 100 further includes the step: S9, testing the prepared solar cell.

[0147] Specifically, after the solar cell 100 is prepared, the solar cell 100 can be subjected to various tests such as electrical performance testing, optical performance testing, interface and structure characterization, etc., so as to comprehensively evaluate the overall performance of the solar cell 100 and provide data support for optimizing the process of the solar cell 100.

[0148] For example, a Sinton test may be performed on the solar cell 100 to test the single-side saturation current density of the solar cell 100 .

[0149] For example, an IV characteristic test may be performed on the solar cell 100 to test data such as the open circuit voltage, short circuit current, fill factor, and photoelectric conversion efficiency of the solar cell 100 .

[0150] Several specific examples of the method for preparing the solar cell 100 provided in the embodiments of the present invention are described below.

[0151] Example 1: An N-type silicon substrate 10 was prepared. The N-type silicon substrate 10 had a double-sided micronized pyramid texture with a thickness of 170 μm and a resistivity of 1 Ω cm to 7 Ω cm. After standard RCA cleaning, the silicon substrate 10 was placed in an LPCVD process. SiO x was deposited in an oxygen atmosphere to form a dielectric layer 21 on the surface of the silicon substrate 10. Subsequently, a nitrogen-rich polysilicon film (nitrogen content of 1 at %) was deposited by LPCVD at 900°C using SiH 2 Cl 2 and 1% NH 3 as source gases to form a first polysilicon layer 22. Subsequently, a nitrogen-free polysilicon film was deposited by LPCVD at 600°C using SiH 4 as source gas to form a second polysilicon layer 23. The silicon substrate 10 was then transferred to a tubular phosphorus diffusion furnace and phosphorus diffusion was performed at 850°C using POCl 3 as a dopant to dope the first and second polysilicon layers 22 and 23. Afterwards, AlOx was deposited by ALD and annealed at 450°C for 30 minutes in a tube furnace to form a first dielectric film 30. The silicon substrate 10 was then transferred to PECVD to deposit SiNx, and annealed at 400°C for 60 minutes in a tube furnace under a mixed gas atmosphere of nitrogen and hydrogen to form a second dielectric film 40. Finally, electrodes were prepared on the surface of the second dielectric film 40 to obtain a solar cell 100. A total of 10 solar cell 100 samples were prepared, and each solar cell 100 was subjected to a Sinton test. The test results showed that the single-side saturation current density of each solar cell 100 ranged from 0.7 fA / cm 2 Up to 2.3 fA / cm 2 .

[0152] Example 2: An N-type silicon substrate 10 was prepared. The N-type silicon substrate 10 had a double-sided micronized pyramid texture with a thickness of 170 μm and a resistivity of 1 Ω cm to 7 Ω cm. After standard RCA cleaning, the silicon substrate 10 was placed in an LPCVD process. SiO x was deposited in an oxygen atmosphere to form a dielectric layer 21 on the surface of the silicon substrate 10. Subsequently, a nitrogen-rich polysilicon film (nitrogen content: 5 at %) was deposited by LPCVD at 900°C using SiH 2 Cl 2 and 5% NH 3 as source gases to form a first polysilicon layer 22. Subsequently, a nitrogen-free polysilicon film was deposited by LPCVD at 600°C using SiH 4 as source gas to form a second polysilicon layer 23. The silicon substrate 10 was then transferred to a tubular phosphorus diffusion furnace and phosphorus diffusion was performed at 850°C using POCl 3 as a dopant to dope the first and second polysilicon layers 22 and 23. Afterwards, AlOx was deposited by ALD and annealed at 450°C for 30 minutes in a tube furnace to form a first dielectric film 30. The silicon substrate 10 was then transferred to PECVD to deposit SiNx, and annealed at 400°C for 60 minutes in a tube furnace under a mixed gas atmosphere of nitrogen and hydrogen to form a second dielectric film 40. Finally, electrodes were prepared on the surface of the second dielectric film 40 to obtain a solar cell 100. A total of 10 solar cell 100 samples were prepared, and each solar cell 100 was subjected to a Sinton test. The test results showed that the single-side saturation current density of each solar cell 100 ranged from 2.5 fA / cm 2 Up to 5fA / cm 2 .

[0153] Example 3: An N-type silicon substrate 10 was prepared. The N-type silicon substrate 10 had a double-sided micronized pyramid texture with a thickness of 170 μm and a resistivity of 1 Ω cm to 7 Ω cm. After standard RCA cleaning, the silicon substrate 10 was placed in a PECVD process. SiO x was deposited in an oxygen atmosphere to form a dielectric layer 21 on the surface of the silicon substrate 10. Subsequently, a nitrogen-rich polysilicon film (nitrogen content: 5 at %) was deposited by PECVD at a temperature of 500°C using SiH 2 Cl 2 and 5% NH 3 as source gases to form a first polysilicon layer 22. Subsequently, a nitrogen-free polysilicon film was deposited by PECVD at a temperature of 400°C using SiH 4 as a source gas to form a second polysilicon layer 23. The silicon substrate 10 was then transferred to a tubular phosphorus diffusion furnace and phosphorus diffusion was performed at 850°C using POCl 3 as a dopant to dope the first and second polysilicon layers 22 and 23. Afterwards, AlOx was deposited by ALD and annealed at 450°C for 30 minutes in a tube furnace to form a first dielectric film 30. The silicon substrate 10 was then transferred to PECVD to deposit SiNx, and annealed at 400°C for 60 minutes in a tube furnace under a mixed gas atmosphere of nitrogen and hydrogen to form a second dielectric film 40. Finally, electrodes were prepared on the surface of the second dielectric film 40 to obtain a solar cell 100. A total of 10 solar cell 100 samples were prepared, and each solar cell 100 was subjected to a Sinton test. The test results showed that the single-side saturation current density of each solar cell 100 ranged from 2.5 fA / cm 2 Up to 5fA / cm 2 .

[0154] Example 4: An N-type silicon substrate 10 was prepared. The N-type silicon substrate 10 had a double-sided micronized pyramid texture with a thickness of 170 μm and a resistivity of 1 Ω cm to 7 Ω cm. After standard RCA cleaning, the silicon substrate 10 was placed in a PECVD process. SiO x was deposited in an oxygen atmosphere to form a dielectric layer 21 on the surface of the silicon substrate 10. Subsequently, a nitrogen-rich polysilicon film (nitrogen content of 15 at %) was deposited by LPCVD at a temperature of 500°C using SiH 2 Cl 2 and NH 3 (15%) as source gases to form a first polysilicon layer 22. Subsequently, a nitrogen-free polysilicon film was deposited by PECVD at a temperature of 400°C using SiH 4 as a source gas to form a second polysilicon layer 23. The silicon substrate 10 was then transferred to a tubular phosphorus diffusion furnace and phosphorus diffusion was performed at 850°C using POCl 3 as a dopant to dope the first and second polysilicon layers 22 and 23. Afterwards, AlOx was deposited by ALD and annealed at 450°C for 30 minutes in a tube furnace to form a first dielectric film 30. The silicon substrate 10 was then transferred to PECVD to deposit SiNx, and annealed at 400°C for 60 minutes in a tube furnace under a mixed gas atmosphere of nitrogen and hydrogen to form a second dielectric film 40. Finally, electrodes were prepared on the surface of the second dielectric film 40 to obtain a solar cell 100. A total of 10 solar cell 100 samples were prepared, and each solar cell 100 was subjected to a Sinton test. The test results showed that the single-side saturation current density of each solar cell 100 ranged from 4.5 fA / cm 2 Up to 9.5 fA / cm 2 .

[0155] Example 5: An N-type silicon substrate 10 was prepared. The N-type silicon substrate 10 had a double-sided micronized pyramid texture with a thickness of 170 μm and a resistivity of 1 Ω cm to 7 Ω cm. After standard RCA cleaning, the silicon substrate 10 was placed in an LPCVD process. SiO x was deposited in an oxygen atmosphere to form a dielectric layer 21 on the surface of the silicon substrate 10. Subsequently, a nitrogen-rich polysilicon film (nitrogen content of 15 at %) was deposited by LPCVD at 900°C using SiH 2 Cl 2 and NH 3 (15%) as source gases to form a first polysilicon layer 22. Subsequently, a nitrogen-free polysilicon film was deposited by LPCVD at 600°C using SiH 4 as source gas to form a second polysilicon layer 23. The silicon substrate 10 was then transferred to a tubular phosphorus diffusion furnace and phosphorus diffusion was performed at 850°C using POCl 3 as a dopant to dope the first and second polysilicon layers 22 and 23. Afterwards, AlOx was deposited by ALD and annealed at 450°C for 30 minutes in a tube furnace to form a first dielectric film 30. The silicon substrate 10 was then transferred to PECVD to deposit SiNx, and annealed at 400°C for 60 minutes in a tube furnace under a mixed gas atmosphere of nitrogen and hydrogen to form a second dielectric film 40. Finally, electrodes were prepared on the surface of the second dielectric film 40 to obtain a solar cell 100. A total of 10 solar cell 100 samples were prepared, and each solar cell 100 was subjected to a Sinton test. The test results showed that the single-side saturation current density of each solar cell 100 ranged from 4.5 fA / cm 2 Up to 9.5 fA / cm 2 .

[0156] Example 6: An N-type silicon substrate 10 was prepared. The N-type silicon substrate 10 had a double-sided micronized pyramid texture with a thickness of 170 μm and a resistivity of 1 Ω cm to 7 Ω cm. After standard RCA cleaning, the silicon substrate 10 was placed in an LPCVD process. SiO x was deposited in an oxygen atmosphere to form a dielectric layer 21 on the surface of the silicon substrate 10. Subsequently, a nitrogen-rich polysilicon film (nitrogen content of 1 at %) was deposited by LPCVD at a temperature of 900°C using SiH 4 and N 2 O (1%) as source gases to form a first polysilicon layer 22. Subsequently, a nitrogen-free polysilicon film was deposited by LPCVD at a temperature of 600°C using SiH 4 as the source gas to form a second polysilicon layer 23. The silicon substrate 10 was then transferred to a tubular phosphorus diffusion furnace and phosphorus diffusion was performed at 850°C using POCl 3 as a dopant to dope the first and second polysilicon layers 22 and 23. Afterwards, AlOx was deposited by ALD and annealed at 450°C for 30 minutes in a tube furnace to form a first dielectric film 30. The silicon substrate 10 was then transferred to PECVD to deposit SiNx, and annealed at 400°C for 60 minutes in a tube furnace under a mixed gas atmosphere of nitrogen and hydrogen to form a second dielectric film 40. Finally, electrodes were prepared on the surface of the second dielectric film 40 to obtain a solar cell 100. A total of 10 solar cell 100 samples were prepared, and each solar cell 100 was subjected to the Sinton test. The test results showed that the single-side saturation current density of each solar cell 100 ranged from 2.1 fA / cm 2 Up to 4 fA / cm 2 .

[0157] Therefore, in summary, the method for preparing the solar cell 100 provided in the embodiment of the present invention can reduce the gap 211 of the dielectric layer 21 in the prepared solar cell 100, and can also significantly reduce the surface recombination current density of the solar cell 100, thereby improving the passivation effect of the solar cell 100.

[0158] It is understood that the battery assembly 1001 in such an embodiment may further include a frame, a front plate, a back plate, photovoltaic glass, and a film. The film may be filled between the front and back surfaces of the solar cell 100, the photovoltaic glass, adjacent solar cells 100, etc. As a filler, it may be a transparent colloid with good light transmittance and aging resistance. For example, the film may be EVA film or POE film. The specific selection may be based on actual conditions and is not limited here.

[0159] Photovoltaic glass can cover the adhesive film on the front of solar cell 100. The photovoltaic glass can be ultra-clear glass, which has high light transmittance, high transparency, and excellent physical, mechanical, and optical properties. For example, ultra-clear glass can have a light transmittance of over 92%, protecting solar cell 100 while minimizing its efficiency. The adhesive film also bonds the photovoltaic glass and solar cell 100 together, providing sealing, insulation, and waterproofing for solar cell 100.

[0160] The backsheet can be attached to the film on the back of the solar cell 100. The backsheet provides protection and support for the solar cell 100, and has reliable insulation, water resistance, and aging resistance. There are multiple options for the backsheet, typically tempered glass, organic glass, aluminum alloy TPT composite film, etc. The specific configuration can be determined based on the specific situation and is not limited here. The entire assembly consisting of the backsheet, solar cells, film, and photovoltaic glass can be mounted on a frame. The frame serves as the primary external support structure for the entire battery assembly 1001 and provides stable support and installation for the battery assembly 1001. For example, the battery assembly 1001 can be installed in the desired location using the frame.

[0161] Throughout this specification, reference to terms such as "some embodiments," "illustrative embodiments," "examples," "specific examples," or "some examples" means that a specific feature, structure, material, or characteristic described in conjunction with an embodiment or example is included in at least one embodiment or example of the present application. In this specification, the illustrative use of the above terms does not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

[0162] In addition, the above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A solar cell, characterized in that: The invention comprises a silicon substrate and a passivation structure provided on at least one side of the silicon substrate; The passivation structure includes: a dielectric layer, a first polysilicon layer provided on a side of the dielectric layer facing away from the silicon substrate, and at least one second polysilicon layer provided on a side of the first polysilicon layer facing away from the dielectric layer; The first polysilicon layer is a polysilicon layer containing nitrogen, the nitrogen concentration of at least one of the first polysilicon layers is greater than the nitrogen concentration of any of the second polysilicon layers, and the nitrogen concentration of at least one of the first polysilicon layers is 0.3 at.% to 35 at.%.

2. The solar cell according to claim 1, wherein The nitrogen concentration of at least one portion of the first polysilicon layer is 0.5 at. % to 25 at. %.

3. The solar cell according to claim 1, wherein The thickness of the dielectric layer is 1 nm to 4 nm.

4. The solar cell according to claim 3, characterized in that The thickness of the dielectric layer is 1.5 nm to 2.5 nm.

5. The solar cell according to claim 1, wherein The thickness of the first polysilicon layer is 3 nm to 60 nm.

6. The solar cell according to claim 5, characterized in that The thickness of the first polysilicon layer is 5 nm to 40 nm.

7. The solar cell according to claim 1, wherein The thickness of the second polysilicon layer is greater than 15 nm.

8. The solar cell according to claim 7, characterized in that The thickness of the second polysilicon layer is greater than 30 nm.

9. The solar cell according to claim 1, wherein The phosphorus doping concentration of at least one of the first polysilicon layers is lower than the phosphorus doping concentration of any of the second polysilicon layers.

10. The solar cell according to claim 1, wherein The doping concentration of the N-type main element in at least one of the first polysilicon layers is 1.5×10 18 cm -3 to 8×10 20 cm -3 .

11. The solar cell according to claim 8, characterized in that The doping concentration of the N-type main element in at least one of the first polysilicon layers is 5×10 18 cm -3 to 3×10 20 cm -3 .

12. The solar cell according to claim 1, wherein The doping concentration of the N-type main element in at least one of the second polysilicon layers is 1.5×10 20 cm -3 to 1×10 21 cm -3 .

13. The solar cell according to claim 10, characterized in that The doping concentration of the N-type main element in at least one of the second polysilicon layers is 1×10 20 cm -3 to 0.8×10 21 cm -3 .

14. The solar cell according to claim 1, wherein The nitrogen concentration of the second polysilicon layer is 0.001 at. % to 10 at. %.

15. The solar cell according to claim 14, characterized in that The nitrogen concentration of the second polysilicon layer is 0.001 at. % to 0.2 at. %.

16. The solar cell according to claim 1, wherein The nitrogen concentration of the second polysilicon layer is 0.

17. The solar cell according to claim 1, wherein The dielectric layer is a silicon oxide dielectric layer, a hydrogenated silicon oxide dielectric layer, a silicon oxynitride dielectric layer or a silicon oxycarbide dielectric layer.

18. The solar cell according to claim 1, wherein The dielectric layer includes a plurality of notches, and the number of notches per unit area in at least one location of the dielectric layer is 10 / μm. 2 Up to 5000 pieces / μm 2 .

19. The solar cell according to claim 18, characterized in that The number of the notches per unit area in at least one location of the dielectric layer is 50 / μm 2 Up to 2000 / μm 2 .

20. The solar cell according to claim 18, wherein The notch is at least located on the side or surface of the dielectric layer.

21. The solar cell according to claim 1, wherein The passivation structure is arranged in the N-type doping region of the silicon substrate.

22. A method for preparing a solar cell according to any one of claims 1 to 21, characterized in that: Including steps: S1. Prepare a silicon substrate; S2. Depositing a dielectric layer on at least one side of the silicon substrate; S3, depositing a nitrogen-containing polysilicon film on the surface of the dielectric layer to form a first polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is 0.3 at.% to 35 at.%; S4, depositing at least one polysilicon thin film on the surface of the first polysilicon layer to form at least one second polysilicon layer, wherein the nitrogen concentration of the first polysilicon layer is greater than the nitrogen concentration of any second polysilicon layer; S5. Doping the first polysilicon layer and the second polysilicon layer with an N-type main element.

23. The method for preparing a solar cell according to claim 22, wherein: In step S2, a dielectric layer is deposited on at least one surface of the silicon substrate by PECVD, LPCVD, wet oxidation, or ozone oxidation; and / or, In step S3, a nitrogen-containing polysilicon film is deposited on the surface of the dielectric layer by PECVD, LPCVD, Sputtering, or E-Beam; and / or, In step S4, at least one polysilicon thin film is deposited on the surface of the first polysilicon layer by PECVD, LPCVD, Sputtering, or E-Beam.

24. The method for preparing a solar cell according to claim 22, wherein: Also includes the steps: S6, depositing an aluminum oxide film on the surface of the outermost second polysilicon layer, and then performing an annealing process to form a first dielectric film; S7, depositing a silicon nitride film on the surface of the first dielectric film, and then performing an annealing process to form a second dielectric film; S8, preparing an electrode on the surface of the second dielectric film to obtain a solar cell; S9. Testing the prepared solar cell.

25. A battery assembly, characterized in that: A solar cell comprising the solar cell according to any one of claims 1 to 21 or a solar cell prepared by the method for preparing a solar cell according to any one of claims 22 to 24.

26. A photovoltaic system, characterized in that: Comprising the battery assembly as claimed in claim 25.

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