Multi-distribution noise simulation method and system based on logical operation

Abstract

The invention discloses a multi-distribution noise simulation method and system based on logical operation, and the method comprises the steps: carrying out the simulation of a chaos model, obtaining the value range of each data point in a chaos output sequence, setting the bit width of binary data obtained through the conversion of the chaos output sequence according to the value range, generating a chaos output sequence according to the chaos model, converting the chaos output sequence to obtain a binary sequence, then selecting multiple times from five preset basic gate circuit operations, selecting more than one operation arrangement each time to obtain a basic gate circuit conversion algorithm, and converting each binary number in the binary sequence by adopting each basic gate circuit conversion algorithm to obtain a binary number sequence; and performing inverse transformation on the binary sequences to obtain a plurality of noise sequences. According to the invention, the abundant attractor fractal structure of the chaos model can be realized through simple gate logic, so that the noise simulation of various distributions can be realized.

Description

Technical Field

[0001] The present invention belongs to the technical field of noise simulation, and more particularly, relates to a multi-distributed noise simulation method and system based on logic operations. Background Art

[0002] As a nonlinear dynamical system with a deterministic mathematical model, chaotic systems are the preferred method for implementing high-performance pseudo-random number generators due to their physical interpretability, initial sensitivity, inherent randomness, and repeatability. Chaotic systems can be divided into continuous chaotic systems and discrete chaotic mappings. Discrete chaotic mappings are favored by scholars in engineering applications due to their fixed model, simple implementation, and high stability. However, the implementation of discrete chaotic mappings is relatively complex. Obtaining rich attractor fractal structures requires changing initial values ​​or system parameters, or even changing the chaotic model, which often leads to significant inconveniences in hardware implementation. Summary of the Invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a multi-distribution noise simulation method and system based on logical operations, which can realize the rich attractor fractal structure of the chaotic model through simple gate logic to achieve noise simulation with multiple distributions.

[0004] In order to achieve the above-mentioned object of the invention, the multi-distributed noise simulation method based on logic operation of the present invention comprises the following steps:

[0005] S1: Set the chaos model according to the parameters set by the user:

[0006]

[0007] Where k represents the data point number, k = 1, 2, ..., x i,1 ,x i,2 ,...,x i,k ∈{x i}, {x i}, i=1,2,...,n represents the chaotic output sequence, n represents the chaotic output dimension, f i () represents the chaotic function;

[0008] S2: Simulate the chaotic model to obtain the chaotic output sequence {x i} for each data point x i,k The value range of p i ≤x i,k ≤q i ; For the chaotic output sequence {x i}The binary number sequence obtained by conversion is {N i}, let each binary number N i,k The bit width m i=a i +b i +c i ,in:

[0009] a i The width of the sign bit is 1;

[0010] b i is the integer bit width, b i The value of Among them O i =max{|p i |,|q i |}, floor() means rounding down;

[0011] c i is the decimal place width;

[0012] S3: Generate chaotic output sequence {x i} and convert it into a binary sequence {N i};

[0013] S4: Select one or more operations from the five preset basic gate circuit operations and arrange them to obtain a basic gate circuit transformation algorithm. Perform R selections to obtain R basic gate circuit transformation algorithms. The basic gate circuit operations include:

[0014] 1) Data segment exchange operation: arbitrarily select two D1-bit data segments from the current binary number, where D1 is the preset exchange data segment length, and exchange the two data segments;

[0015] 2) Inversion operation: randomly select a D2-bit data segment from the current binary number, where D2 is the preset inverted data segment length, and invert each bit of the data segment;

[0016] 3) AND-replace operation: arbitrarily select two D3-bit data segments from the current binary number, where D3 is the preset AND data segment length. After performing the AND operation on the two data segments, the resulting data segment replaces the first data segment.

[0017] 4) OR-replace operation: arbitrarily select two D4-bit data segments from the current binary number, where D4 is the preset OR data segment length. After performing an OR operation on the two data segments, the resulting data segment replaces the first data segment.

[0018] 5) Reordering operation: randomly select a D5-bit data segment from the current binary number, where D5 is the preset reordered data segment length, and randomly reorder the D5-bit binary number of the data segment according to the bit number, and replace the original data segment with the resulting data segment;

[0019] S5: For the binary sequence {N iEach m in i The binary number N i,k Each basic gate circuit transformation algorithm is used to process the binary number Thus we get R binary sequences r=1,2,…,R;

[0020] S6: For R binary sequences Perform inverse transform respectively to obtain R noise sequences

[0021] The present invention also provides a multi-distributed noise simulation system based on logic operations, comprising a host computer, a system controller, a chaos module, a multi-distributed sequence generation module and a multi-distributed noise generation module, wherein the system controller, the chaos module, the multi-distributed sequence generation module and the multi-distributed noise generation module are implemented in an FPGA;

[0022] The host computer is used to receive the chaos model parameters set by the user, 5 data segments of length D t and R basic gate circuit operation combination vector Z r ={z r,1 ,z r,2 ,z r,3 ,z r,4 ,z r,5}, where z r,t =1 indicates that the tth basic gate circuit in the multi-distributed sequence generation module is selected in the rth basic gate circuit operation combination, z r,t =0 means not selected, r=1,2,…,R, t=1,2,3,4,5; the host computer sets the chaos model according to the chaos model parameters:

[0023]

[0024] Where k represents the data point number, k = 1, 2, ..., x i,1 ,x i,2 ,...,x i,k ∈{x i}, {x i}, i=1,2,...,n represents the chaotic output sequence, n represents the chaotic output dimension, f i () represents the chaotic function;

[0025] The chaotic model is simulated to obtain the chaotic output sequence {x i} for each data point x i,k The value range of p i ≤x i,k ≤q i ; For the chaotic output sequence {x i}The converted binary sequence {Ni}, let each binary number N i,k Bit width m i =a i +b i +c i ,in:

[0026] a i The width of the sign bit is 1;

[0027] b i is the integer bit width, b i The value of Among them O i =max{|p i |,|q i |}, floor() means rounding down;

[0028] c i is the decimal place width;

[0029] The host computer sets the chaotic model parameters, each binary number N i,k Bit width m i , 5 data segment lengths D t and R basic gate circuit operation combination vector Z r sent to the system controller;

[0030] The system controller is used to send the chaotic model parameters to the chaotic module. Each binary number N i,k Bit width m i , 5 data segment lengths D t and R basic gate circuit operation combination vector Z r Send to the multi-distribution sequence generation module;

[0031] The chaotic system is used to generate a chaotic output sequence {x i}, and then converted into a binary number sequence {N i} and sent to the multi-distribution sequence generation module;

[0032] The multi-distributed sequence generation module is used to combine vector Z according to R basic gate circuit operations r And each binary number N i,k Bit width m i For the binary sequence {N i}Perform R processing to generate R binary sequences And sent to the multi-distributed noise generation module; the multi-distributed sequence generation module includes five basic gate circuits and a circuit control module. The basic gate circuits are a data segment exchange circuit, a negation circuit, an AND operation circuit, or a replacement operation circuit, wherein:

[0033] The data segment exchange circuit is used to arbitrarily select two D1-bit data segments from the current binary number, where D1 is the preset exchange data segment length, and exchange the two data segments;

[0034] The inversion circuit is used to randomly select a D2-bit data segment from the current binary number, where D2 is the preset inverted data segment length, and invert each bit of the data segment;

[0035] The AND replacement circuit is used to arbitrarily select two D3-bit data segments from the current binary number, where D3 is the preset AND data segment length, and after performing an AND operation on the two data segments, the obtained data segment replaces the first data segment;

[0036] The OR replacement circuit is used to arbitrarily select two D4-bit data segments from the current binary number, where D4 is the preset OR data segment length, perform an OR operation on the two data segments, and then replace the first data segment with the resulting data segment;

[0037] The reordering circuit randomly selects a D5-bit data segment from the current binary number, where D5 is the preset reordered data segment length, randomly reorders the D5-bit binary number of the data segment according to the bit number, and replaces the original data segment with the resulting data segment;

[0038] The circuit control module is used to combine vector Z according to R basic gate circuit operations r The five basic gate circuits are called in sequence, receiving the binary number output by the previous basic gate circuit and inputting it into the next basic gate circuit to generate R binary sequences.

[0039] The multi-distribution noise generation module is used to generate R binary sequences Perform inverse transform to obtain R noise sequences

[0040] The present invention is based on a multi-distributed noise simulation method and system for logical operations. The chaotic model is simulated to obtain a value range of each data point in a chaotic output sequence. The bit width of the binary data converted from the chaotic output sequence is then set according to the value range. The chaotic output sequence is generated according to the chaotic model and converted to obtain a binary sequence. Multiple selections are then made from five preset basic gate circuit operations, with one or more operations selected each time to obtain a basic gate circuit transformation algorithm. Each basic gate circuit transformation algorithm is used to transform each binary number in the binary sequence to obtain multiple binary sequences, which are then inversely transformed to obtain multiple noise sequences.

[0041] The present invention has the following beneficial effects:

[0042] 1) The binary sequence of the chaotic output sequence in the present invention uses fixed-point numbers, which have better precision than floating-point numbers. In addition, the FPGA implementation difficulty of performing logical operations on fixed-point numbers is lower, and the resource consumption of logical operations is small.

[0043] 2) The bit width of the binary number in the present invention is determined according to the value range of the chaotic output sequence, which is more flexible;

[0044] 3) The present invention adopts different basic gate circuit operation combinations to obtain multiple basic gate circuit transformation algorithms, and generates noise sequences with different distributions based on the same chaotic output sequence, thereby realizing rich attractor fractal structures through simple gate logic and reducing the complexity of engineering implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a flowchart of a specific implementation method of the multi-distributed noise simulation method based on logical operations of the present invention;

[0046] Figure 2 It is a structural diagram of a specific embodiment of the multi-distributed noise simulation system based on logic operations of the present invention;

[0047] Figure 3 is the phase trajectory diagram of the chaotic output sequence in this embodiment;

[0048] Figure 4 yes Figure 3 The histogram of two-dimensional signals of the chaotic output sequence shown;

[0049] Figure 5 is a noise statistics graph obtained after the first data segment exchange operation in this embodiment;

[0050] Figure 6 is a noise statistics graph obtained after the second data segment exchange operation in this embodiment;

[0051] Figure 7 is a noise statistics graph obtained after the third data segment swap operation in this embodiment;

[0052] Figure 8 is a noise statistical graph obtained after the inversion operation in this embodiment;

[0053] Figure 9 is the noise statistics obtained after the replacement operation in this embodiment;

[0054] Figure 10 is the noise statistics graph obtained after the second replacement operation in this embodiment;

[0055] Figure 11 is a noise statistics graph obtained in this embodiment or after replacing operation 1;

[0056] Figure 12is a noise statistics graph obtained in this embodiment or after replacing operation 2;

[0057] Figure 13 is a noise statistics graph obtained after the reordering operation in this embodiment. DETAILED DESCRIPTION

[0058] The following describes the specific embodiments of the present invention in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when detailed descriptions of known functions and designs may dilute the main content of the present invention, such descriptions will be omitted here.

[0059] Example

[0060] Figure 1 This is a flow chart of a specific implementation of the multi-distributed noise simulation method based on logical operations of the present invention. Figure 1 As shown, the specific steps of the multi-distributed noise simulation method based on logical operations of the present invention include:

[0061] S101: Setting up the Chaos Model:

[0062] Set the chaos model according to the parameters set by the user:

[0063]

[0064] Where k represents the data point number, k = 1, 2, ..., x i,1 ,x i,2 ,...,x i,k ∈{x i}, {x i}, i=1,2,...,n represents the chaotic output sequence, n represents the chaotic output dimension, f i () represents the chaotic function.

[0065] S102: Simulate and obtain chaotic output sequence parameters:

[0066] The chaotic model is simulated to obtain the chaotic output sequence {x i} for each data point x i,k The value range of p i ≤x i,k ≤q i For the chaotic output sequence {x i}The binary number sequence obtained by conversion {N i}, let each binary number N i,k Bit width m i =a i +b i +c i ,in:

[0067] a i The width of the sign bit is 1;

[0068] b i is the integer bit width, b i The value of Among them O i =max{|p i |,|q i |}, floor() means rounding down;

[0069] c i is the decimal place width, c i The value of should not be too small, and its preferred value range is c i ≥48-b i ,c i / b i ≥4.

[0070] It can be seen that the binary number of the present invention is a fixed-point number, and its processing accuracy is higher than that of floating-point numbers. Moreover, the data bit width in the present invention is determined according to the value range of the data points in the chaotic output sequence. The specific bit width can be determined according to actual needs, which is more flexible in engineering applications.

[0071] S103: Generate binary sequence:

[0072] According to the chaotic model, the chaotic output sequence {x i} and convert it into a binary sequence {N i}.

[0073] S104: Determine the basic gate circuit transformation algorithm:

[0074] Select one or more operations from the five preset basic gate circuit operations and arrange them to obtain a basic gate circuit transformation algorithm. Perform R selections to obtain R basic gate circuit transformation algorithms. Basic gate circuit operations include:

[0075] 1) Data segment exchange operation: arbitrarily select two D1-bit data segments from the current binary number, where D1 is the preset exchange data segment length, and exchange the two data segments.

[0076] 2) Inversion operation: randomly select a D2-bit data segment from the current binary number, where D2 is the preset inverted data segment length, and invert each bit of the data segment.

[0077] 3) AND replacement operation: arbitrarily select two D3-bit data segments from the current binary number, where D3 is the preset AND data segment length. After performing the AND operation on the two data segments, the obtained data segment replaces the first data segment.

[0078] 4) OR replacement operation: arbitrarily select two D4-bit data segments from the current binary number, where D4 is the preset OR data segment length. After performing an OR operation on the two data segments, the obtained data segment replaces the first data segment.

[0079] 5) Reordering: Randomly select a D5-bit segment from the current binary number, where D5 is the preset length of the reordered segment. Randomly reorder the D5-bit binary digits in this segment by bit number, and replace the original segment with the resulting segment. You can see that there are a total of D5! -1 = D5 × (D5-1) × (D5-1) × ... × 2 × 1-1 possible permutations.

[0080] In practical applications, to facilitate parameter setting, the lengths of the four data segments in the first four basic gate circuit operations can be set to D1 = D2 = D3 = D4 = D, and the length of the reordered data segment in the fifth basic gate circuit operation can be set to D5 = 2D, where D represents the preset unified data segment length. In order to ensure the distinctiveness of the generated noise sequence distribution, the unified data segment length D should not be too small, and the preferred value range is D ≥ m i / 4.

[0081] S105: Generate multi-distribution binary sequences:

[0082] For the binary sequence {N i Each m in i The binary number N i,k Each basic gate circuit transformation algorithm is used to process the binary number Thus we get R binary sequences r=1,2,…,R。

[0083] S106: Generate noise sequence:

[0084] Then for R binary sequences Perform inverse transform respectively to obtain R noise sequences

[0085] In order to facilitate engineering applications, the present invention also proposes a multi-distributed noise simulation system based on logic operations. Figure 2 This is a structural diagram of a specific embodiment of the multi-distributed noise simulation system based on logic operations of the present invention. Figure 2 As shown, the multi-distributed noise simulation system based on logical operations of the present invention includes a host computer 1, a system controller 2, a chaos module 3, a multi-distributed sequence generation module 4 and a multi-distributed noise generation module 5, wherein the system controller 2, the chaos module 3, the multi-distributed sequence generation module 4 and the multi-distributed noise generation module 5 are implemented in FPGA. Each module is described in detail below.

[0086] Host computer 1 is used to receive the chaos model parameters set by the user, and the length of the 4 data segments is D t and R basic gate circuit operation combination vector Z r ={z r,1 ,z r,2 ,z r,3 ,z r,4 ,z r,5}, where z r,t =1 indicates that the tth basic gate circuit in the multi-distributed sequence generation module 4 is selected in the rth basic gate circuit operation combination, z r,t =0 means not selected, r=1,2,…,R, t=1,2,3,4,5. The host computer 1 sets the chaos model according to the chaos model parameters:

[0087]

[0088] Where k represents the data point number, k = 1, 2, ..., x i,1 ,x i,2 ,...,x i,k ∈{x i}, {x i}, i=1,2,...,n represents the chaotic output sequence, n represents the chaotic output dimension, f i () represents the chaotic function.

[0089] The chaotic model is simulated to obtain the chaotic output sequence {x i} for each data point x i,k The value range of p i ≤x i,k ≤q i For the chaotic output sequence {x i}The converted binary sequence {N i}, let each binary number N i,k Bit width m i =a i +b i +c i ,in:

[0090] a i The width of the sign bit is 1;

[0091] b i is the integer bit width, b i The value of Among them O i =max{|p i |,|q i |}, floor() means rounding down;

[0092] c iThe decimal place width.

[0093] The host computer 1 sets the chaotic model parameters, each binary number N i,k Bit width m i , 5 data segment lengths D t and R basic gate circuit operation combination vector Z r Sent to system controller 2.

[0094] The system controller 2 is used to send the chaotic model parameters to the chaotic module 3, and each binary number N i,k Bit width m i , 5 data segment lengths D t and R basic gate circuit operation combination vector Z r Send to the multi-distribution sequence generation module 4.

[0095] Chaotic system 3 is used to generate chaotic output sequence {x i}, and then converted into a binary number sequence {N i} and sent to the multi-distribution sequence generation module 4.

[0096] The multi-distributed sequence generation module 4 is used to combine the vector Z according to the R basic gate circuit operations r And each binary number N i,k Bit width m i For the binary sequence {N i}Perform R processing to generate R binary sequences And sent to the multi-distributed noise generation module 5. The multi-distributed sequence generation module 4 includes five basic gate circuits and a circuit control module 46. The basic gate circuits are respectively a data segment exchange circuit 41, a negation circuit 42, an AND operation circuit 43, or a replacement operation circuit 44 and a reordering circuit 45, wherein:

[0097] The data segment exchange circuit 41 is used to arbitrarily select two D1-bit data segments from the current binary number, where D1 is a preset exchange data segment length, and exchange the two data segments.

[0098] The inversion circuit 42 is used to randomly select a D2-bit data segment from the current binary number, where D2 is a preset inverted data segment length, and invert each bit of the data segment.

[0099] The AND replacement circuit 43 is used to randomly select two D3-bit data segments from the current binary number, where D3 is a preset AND data segment length, perform an AND operation on the two data segments, and then replace the first data segment with the resulting data segment;

[0100] The OR replacement circuit 44 is used to arbitrarily select two D4-bit data segments from the current binary number, where D4 is a preset OR data segment length, perform an OR operation on the two data segments, and then replace the first data segment with the resulting data segment;

[0101] The reordering circuit 45 randomly selects a D5-bit data segment from the current binary number, where D5 is a preset reordered data segment length, randomly reorders the D5-bit binary number of the data segment according to the bit number, and replaces the original data segment with the obtained data segment.

[0102] The circuit control module 46 is used to combine the vector Z according to the R basic gate circuit operations. r The five basic gate circuits are called in sequence, receiving the binary number output by the previous basic gate circuit and inputting it into the next basic gate circuit to generate R binary sequences.

[0103] The multi-distribution noise generation module 5 is used to generate R binary sequences Perform inverse transform to obtain R noise sequences

[0104] In order to better illustrate the technical effects of the present invention, a specific example is used to experimentally verify the present invention. The chaos model used in this embodiment is as follows:

[0105]

[0106] It can be seen that the chaos model adopted in this embodiment generates a two-dimensional random signal.

[0107] Figure 3 It is a statistical diagram of the chaotic output sequence in this embodiment. Figure 4 yes Figure 3 The histogram of the two-dimensional signal of the chaotic output sequence shown.

[0108] To facilitate experimentation and comparison, only one basic gate circuit operation is used in each basic gate circuit transformation algorithm in this embodiment. First, an experiment is conducted on the data segment swapping operation. Three data segment swapping experiments are performed in this embodiment: swapping bits 2-5 with bits 6-9 in the binary data; swapping bits 2-5 with bits 10-13 in the binary data; and swapping bits 2-5 with bits 14-17 in the binary data. Figure 5 1 is a noise statistics graph obtained after the first data segment exchange operation in this embodiment. Figure 6 This is a noise statistics graph obtained after the second data segment exchange operation in this embodiment. Figure 7 is a noise statistics graph obtained after the third data segment exchange operation in this embodiment.

[0109] Next, experiments are conducted on the negation operation, the AND operation, the OR operation, and the reordering operation.

[0110] In this embodiment, bits 2-5 in the binary data are inverted. Figure 8 This is the noise statistics obtained after the inversion operation in this embodiment. Then, two AND-replace operations are performed: Bits 2-5 of the binary data are ANDed with the data segment of bits 6-9, and bits 2-5 of the resulting data segment are replaced; bits 2-5 of the binary data are ANDed with the data segment of bits 14-17, and bits 2-5 of the resulting data segment are replaced. Figure 9 ] is a noise statistics graph obtained after the replacement operation in this embodiment. Figure 10 This is a noise statistics graph obtained after the second replacement operation in this embodiment.

[0111] Two more OR replacement operations are performed, namely: performing an OR operation on the 2-5 bit and 6-9 bit data segments in the binary data, and then replacing the 2-5 bit with the obtained data segment; performing an OR operation on the 2-5 bit and 14-17 bit data segments in the binary data, and then replacing the 2-5 bit with the obtained data segment. Figure 11 It is a noise statistics diagram obtained in this embodiment or after the replacement operation 1. Figure 12 It is a noise statistics graph obtained in this embodiment or after replacing operation 2.

[0112] Finally, a reordering operation is performed to randomly sort the 2nd to 9th bits in the binary data, a total of 8 bits. In this embodiment, the original 2, 3, 4, 5, 6, 7, 8, 9 are reordered to 7, 4, 5, 8, 2, 3, 6, 9, and the remaining bits remain unchanged. Figure 13 is a noise statistics graph obtained after the reordering operation in this embodiment.

[0113] like Figures 3 to 13 As shown in the figure, by using different basic gate circuit transformation algorithms, the attractor fractal structures of the noise obtained according to the same chaotic output sequence are different. Therefore, based on a chaotic output sequence, rich attractor fractal structures can be realized through simple gate logic to simulate noises with different distributions.

[0114] Although the above describes the illustrative specific embodiments of the present invention to facilitate understanding of the present invention by those skilled in the art, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations using the concepts of the present invention are protected.

Claims

1. A multi-distributed noise simulation method based on logical operations, characterized in that: The following steps are involved: S1: Set the chaos model according to the parameters set by the user: Where k represents the data point number, k = 1, 2, ..., x i,1 ,x i,2 ,...,x i,k ∈{x i }, {x i }, i=1,2,...,n represents the chaotic output sequence, n represents the chaotic output dimension, f i () represents the chaotic function; S2: Simulate the chaotic model to obtain the chaotic output sequence {x i } for each data point x i,k The value range of p i ≤x i,k ≤q i ; For the chaotic output sequence {x i }The binary number sequence obtained by conversion {N i }, let each binary number N i,k Bit width m i =a i +b i +c i ,in: a i The width of the sign bit is 1; b i is the integer bit width, b i The value of Among them O i =max{|p i |,|q i |}, floor() means rounding down; c i is the decimal place width; S3: Generate chaotic output sequence {x i } and convert it into a binary sequence {N i }; S4: Select one or more operations from the five preset basic gate circuit operations and arrange them to obtain a basic gate circuit transformation algorithm. Perform R selections to obtain R basic gate circuit transformation algorithms. The basic gate circuit operations include: 1) Data segment exchange operation: arbitrarily select two D1-bit data segments from the current binary number, where D1 is the preset exchange data segment length, and exchange the two data segments; 2) Inversion operation: randomly select a D2-bit data segment from the current binary number, where D2 is the preset inverted data segment length, and invert each bit of the data segment; 3) AND-replace operation: arbitrarily select two D3-bit data segments from the current binary number, where D3 is the preset AND data segment length. After performing the AND operation on the two data segments, the resulting data segment replaces the first data segment. 4) OR-replace operation: arbitrarily select two D4-bit data segments from the current binary number, where D4 is the preset OR data segment length. After performing an OR operation on the two data segments, the resulting data segment replaces the first data segment. 5) Reordering operation: randomly select a D5-bit data segment from the current binary number, where D5 is the preset reordered data segment length, and randomly reorder the D5-bit binary number of the data segment according to the bit number, and replace the original data segment with the resulting data segment; S5: For the binary sequence {N i Each m in i The binary number N i,k Each basic gate circuit transformation algorithm is used to process the binary number Thus we get R binary sequences r=1,2,…,R; S6: For R binary sequences Perform inverse transform respectively to obtain R noise sequences 2. The multi-distribution noise simulation method according to claim 1, characterized in that: The decimal place width c i The preferred value range is c i ≥48-b i ,c i / b i ≥4.

3. The multi-distribution noise simulation method according to claim 1, characterized in that: In the first four basic gate circuit operations in step S4, the lengths of the four data segments are D1=D2=D3=D4=D, and the length of the data segment in the reordering operation is D5=2D, where D represents a preset unified data segment length.

4. The multi-distribution noise simulation method according to claim 3, characterized in that: The data segment length D≥m i / 4.

5. A multi-distributed noise simulation system based on logical operations, characterized in that: The system comprises a host computer, a system controller, a chaos module, a multi-distributed sequence generation module and a multi-distributed noise generation module, wherein the system controller, the chaos module, the multi-distributed sequence generation module and the multi-distributed noise generation module are implemented in FPGA; The host computer is used to receive the chaos model parameters set by the user, 5 data segments of length D t and R basic gate circuit operation combination vector Z r ={z r,1 ,z r,2 ,z r,3 ,z r,4 ,z r,5 }, where z r,t =1 indicates that the tth basic gate circuit in the multi-distributed sequence generation module is selected in the rth basic gate circuit operation combination, z r,t =0 means not selected, r=1,2,…,R, t=1,2,3,4,5; the host computer sets the chaos model according to the chaos model parameters: Where k represents the data point number, k = 1, 2, ..., x i,1 ,x i,2 ,...,x i,k ∈{x i }, {x i }, i=1,2,...,n represents the chaotic output sequence, n represents the chaotic output dimension, f i () represents the chaotic function; The chaotic model is simulated to obtain the chaotic output sequence {x i } for each data point x i,k The value range of p i ≤x i,k ≤q i ; For the chaotic output sequence {x i }The converted binary sequence {N i }, let each binary number N i,k Bit width m i =a i +b i +c i ,in: a i The width of the sign bit is 1; b i is the integer bit width, b i The value of Among them O i =max{|p i |,|q i |}, floor() means rounding down; c i is the decimal place width; The host computer sets the chaotic model parameters, each binary number N i,k Bit width m i , 5 data segment lengths D t and R basic gate circuit operation combination vector Z r sent to the system controller; The system controller is used to send the chaotic model parameters to the chaotic module. Each binary number N i,k Bit width m i , 5 data segment lengths D t and R basic gate circuit operation combination vector Z r Send to the multi-distribution sequence generation module; The chaotic system is used to generate a chaotic output sequence {x i }, and then converted into a binary number sequence {N i } and sent to the multi-distribution sequence generation module; The multi-distributed sequence generation module is used to combine vector Z according to R basic gate circuit operations r And each binary number N i,k Bit width m i For the binary sequence {N i }Perform R processing to generate R binary sequences And sent to the multi-distributed noise generation module; the multi-distributed sequence generation module includes five basic gate circuits and a circuit control module. The basic gate circuits are a data segment exchange circuit, a negation circuit, an AND operation circuit, or a replacement operation circuit and a reordering circuit, among which: The data segment exchange circuit is used to arbitrarily select two D1-bit data segments from the current binary number, where D1 is the preset exchange data segment length, and exchange the two data segments; The inversion circuit is used to randomly select a D2-bit data segment from the current binary number, where D2 is the preset inverted data segment length, and invert each bit of the data segment; The AND replacement circuit is used to arbitrarily select two D3-bit data segments from the current binary number, where D3 is the preset AND data segment length, and after performing an AND operation on the two data segments, the obtained data segment replaces the first data segment; The OR replacement circuit is used to arbitrarily select two D4-bit data segments from the current binary number, where D4 is the preset OR data segment length, perform an OR operation on the two data segments, and then replace the first data segment with the resulting data segment; The reordering circuit randomly selects a D5-bit data segment from the current binary number, where D5 is the preset reordered data segment length, randomly reorders the D5-bit binary number of the data segment according to the bit number, and replaces the original data segment with the resulting data segment; The circuit control module is used to combine vector Z according to R basic gate circuit operations r The five basic gate circuits are called in sequence, receiving the binary number output by the previous basic gate circuit and inputting it into the next basic gate circuit to generate R binary sequences. The multi-distribution noise generation module is used to generate R binary sequences Perform inverse transform to obtain R noise sequences 6. The multi-distribution noise simulation system according to claim 5, characterized in that: The decimal place width c i The preferred value range is c i ≥48-b i ,c i / b i ≥4.

7. The multi-distribution noise simulation system according to claim 5, characterized in that: The four data segment lengths of the first four basic gate circuits are D1=D2=D3=D4=D, and the data segment length of the reordered basic gate circuit is D5=2D, where D represents a preset unified data segment length.

8. The multi-distribution noise simulation method according to claim 7, characterized in that: The data segment length D≥m i / 4.

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