Memory address access control system for fast number-theory transformation
By introducing a combination of address mapping units and butterfly operation modules, the difficulties of the NTT architecture in flexibility and parallelism are solved, low-complexity control logic and efficient memory address access are achieved, and the requirements of different point numbers and parallelism are adapted.
Patent Information
- Application Number
- CN202510916396.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-03
- Publication Date
- 2025-10-10
AI Technical Summary
The existing NTT architecture has difficulties in achieving flexibility, parallelism and memory planning. Especially when supporting different numbers of points and parallelism, it cannot effectively avoid data access conflicts and the control logic is complex.
By introducing the address mapping unit to achieve equivalent memory redistribution, the initial address generation module and address mapping module are used, combined with the block random access memory and butterfly operation module to perform single or multi-parallel data reading and exchange, avoiding complex control logic.
It implements low-complexity control logic while ensuring flexibility and storage constraints, improves hardware utilization and parallelism, maintains consistency in operations at each stage, and adapts to requirements of different numbers of points and parallelism.
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Abstract
Description
Technical Field
[0001] The present invention relates to the field of computer technology, and in particular to a memory address access control system oriented to fast number theory transformation. Background Art
[0002] The rapid development of quantum computers poses a significant security threat to existing public-key cryptographic algorithms (such as RSA and ECC). To address this issue, various post-quantum cryptographic schemes designed to withstand quantum computer attacks have emerged. Among these, the lattice-based CRYSTALS-Kyber and CRYSTALS-Dilithium algorithms standardized by the National Institute of Standards and Technology (NIST) have garnered widespread attention and hold promising application prospects. Post-quantum cryptographic algorithms are significantly more complex than traditional ones, and their energy-efficient migration and deployment are critical challenges that urgently need to be addressed. Dedicated hardware implementation is currently the mainstream solution.
[0003] The core operator of the lattice-based CRYSTALS series of algorithms is polynomial multiplication. Directly calculating polynomial multiplication consumes a large amount of resources. For example, when the dimension of the polynomial is N, the NTT algorithm effectively reduces the computational complexity from [N] to [N]. Currently, various hardware implementations for NTT exist. Due to the characteristics of the NTT algorithm, all NTT architectures face complex memory planning challenges. Achieving more flexible NTT data access (supporting different numbers of points and degrees of parallelism) with smaller control logic, lower latency, and less memory capacity is a major challenge in NTT architecture design.
[0004] The most straightforward implementation involves serially reading, writing, and computing using a single memory block and a butterfly unit. This eliminates memory contention, but the degree of parallelism cannot be expanded, individual computations have long latency, and hardware utilization is low. Later, a dual-flounder unit and dual-port memory approach was adopted, doubling the degree of parallelism and improving hardware utilization. However, this solution cannot be configured to any other degree of parallelism, resulting in limited flexibility. Recently, a solution has been proposed that allows for arbitrary adjustment of parallelism without data access contention. This approach effectively resolves data contention by dividing the RAM into a larger number of blocks and using in-situ reads and staggered writes. This parallel solution simplifies memory allocation, but cannot maintain a relatively uniform structure across the different NTT stages, requiring more complex control logic to implement the different operations at each stage. This solution is currently the primary reference due to its superior flexibility and the lack of additional storage requirements. Summary of the Invention
[0005] The present application provides a memory address access control system for fast number theory transformation, which introduces an address mapping unit to achieve equivalent memory redistribution, thereby realizing low-complexity control logic while ensuring flexibility and storage constraints.
[0006] The system comprises:
[0007] an initial address generation module, wherein the initial address generation module is configured to generate initial address data;
[0008] an address mapping module, the address mapping module being configured to set an address mapping for the initial address data and generate actual address data;
[0009] A plurality of block random access memories, wherein the block random access memories store data required for NTT operation, and the data required for NTT operation corresponds to the actual address data;
[0010] A plurality of butterfly operation modules are configured to perform data reading in a single-parallel or multi-parallel manner on the data required for the NTT operation stored in the block random access memory in several stages according to the actual address data, and perform butterfly operation on the data required for the NTT operation read in each stage; the data reading process includes data exchange of the data required for the NTT operation between different block random access memories.
[0011] Preferably, the butterfly operation module is further configured to:
[0012] The data required for the NTT operation stored in all block random access memories are read in a single or multi-parallel manner in several stages in the form of data pairs; the data pair reading is to simultaneously read a pair of data required for the NTT operation from at least two of the block random access memories, and the pair of data required for the NTT operation consists of two same-sequence data read in the same order from the two corresponding block random access memories;
[0013] The butterfly operation module is further configured to:
[0014] A butterfly operation is performed on two of the same-sequence data in a pair of data required for NTT operations.
[0015] Preferably, the butterfly operation module is further configured to:
[0016] The data required for the NTT operation stored in all the block random access memories are read in single or multi-parallel in several stages in the form of data pairs and in a preset order; the preset order of each stage corresponds to the data required for the NTT operation required for the butterfly operation in each stage.
[0017] Preferably, the butterfly operation module is further configured to:
[0018] After the data reading required for one stage of the NTT operation is completed, the corresponding data read from the two block random access memories corresponding to each other are exchanged, and the new same sequence data in the two block random access memories corresponding to each other after the data exchange is the data required for the next stage to be read.
[0019] Preferably, the butterfly operation module is further configured to:
[0020] When the address data reading of one stage is completed and the reading order of the address data reading of the current stage is the target order, the current stage is marked as the exchange completion stage.
[0021] Preferably, the data exchange includes:
[0022] The data of even-numbered times of butterfly operation and the data of odd-numbered times of butterfly operation in the block random access memories corresponding to each other are exchanged, and the data of even-numbered times of butterfly operation is the data in the same block random access memory, and the data of odd-numbered times of butterfly operation is the data in the block random access memory corresponding to the block random access memory where the data of even-numbered times of butterfly operation is stored.
[0023] Preferably, the ratio of the number of points of data stored in all the block random access memories to the number of parallelisms is not less than 8, and the number of block random access memories and the number of parallelisms are both powers of 2.
[0024] Preferably, the butterfly operation module is further configured to:
[0025] When the number of block random access memories is 2, the data required for the NTT operation stored in all the block random access memories is read in single parallelism for several stages.
[0026] Preferably, the butterfly operation module is further configured to:
[0027] When the number of block random access memories is not less than 4, the data required for the NTT operation stored in all the block random access memories is read in multiple parallelism for several stages.
[0028] Preferably, when multiple parallelism reading is performed, the block random access memories at least include a first storage, a second storage, a third storage, and a fourth storage, and the butterfly operation module is further configured to:
[0029] When two parallelism reading is performed, all the data required for the NTT operation is sequentially stored in the first storage, the second storage, the third storage, and the fourth storage according to the order and address mapping.
[0030] The data in the first storage and the second storage, and the data in the third storage and the fourth storage are read simultaneously.
[0031] As can be seen from the above content, the present application provides a memory address access control system for fast number theory transformation, the system including an initial address generation module, the initial address generation module being configured to generate initial address data; an address mapping module, the address mapping module being configured to set an address mapping for the initial address data and generate actual address data; a plurality of block random access memories, the block random access memories storing data required for NTT operations, the data required for NTT operations corresponding to the actual address data; a plurality of butterfly operation modules, the butterfly operation modules being configured to read the data required for NTT operations stored in the block random access memories in a single-parallel or multi-parallel manner according to the actual address data, and to perform butterfly operations on the data required for NTT operations read in each stage; the data reading process includes data exchange of the data required for NTT operations between different block random access memories. The system provided by the present application is based on NTT memory address access logic based on data exchange, which avoids complex control logic through exchange without reducing the speed of the control logic. Address repartitioning is performed to address address conflicts caused by multiple parallel operations. This is achieved through an address mapping module, which consumes minimal resources. This address partitioning method allows for greater consistency in operations across all stages, without requiring excessive consideration of the specificities of each stage. This solution is flexible and configurable, enabling the creation of different circuits based on varying numbers of nodes and degrees of parallelism. BRIEF DESCRIPTION OF THE DRAWINGS
[0032] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0033] Figure 1 This application provides a memory address access control system for fast number theory transformation;
[0034] Figure 2 Data flow graph for the forward transformation of base 2 fast number theoretic transform;
[0035] Figure 3 Data flow graph for the inverse transform of base-2 fast number theoretic transform;
[0036] Figure 4 Schematic diagram of the position exchange method and reading order of 8-point NTT;
[0037] Figure 5 This is a schematic diagram of the single parallel 16-point NTT reading sequence;
[0038] Figure 6 This is a schematic diagram of the reading sequence of two parallel 16-point NTTs;
[0039] Figure 7 This is a schematic diagram of the reading sequence of two parallel 16-point NTTs;
[0040] Figure 8 It is a functional diagram of the address mapping module;
[0041] Figure 9 Schematic diagram of two parallel 16-point NTT address mapping modules;
[0042] Figure 10 Schematic diagram of the NTT address mapping module with P parallel nodes and N points. DETAILED DESCRIPTION
[0043] The following will provide a clear and complete description of the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0044] It should be noted that the brief descriptions of terms in this application are only for the purpose of facilitating the understanding of the embodiments described below, and are not intended to limit the embodiments of this application. Unless otherwise specified, these terms should be understood according to their ordinary and usual meanings.
[0045] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.
[0046] Figure 1 This application discloses a memory address access control system for fast number theory transformation.
[0047] See also Figure 1 It can be seen that this embodiment provides a memory address access control system for fast number theory transformation, the system comprising:
[0048] An initial address generation module is configured to generate initial address data.
[0049] Specifically, in this embodiment, the initial address generation module is used to generate initial address data and provide a data basis for subsequent generation of actual address data.
[0050] The system further comprises:
[0051] An address mapping module is configured to set an address mapping for the initial address data and generate actual address data.
[0052] Specifically, in this embodiment, the address mapping module is used to set address mapping for the data stored in the block random access memory. It can be understood that, for example, when storing block random access memory 1, block random access memory 2, block random access memory 3 and block random access memory 4, data 0 to 15 are stored in block random access memory 1, block random access memory 2, block random access memory 3 and block random access memory 4 respectively, then the data stored in block random access memory 1 on the surface layer is 0 to 3.
[0053] Taking data No. 2 stored in memory 1 as an example, the address mapping module can realize that the surface layer is No. 2, but the actual stored content is No. 5 in block random access memory 2.
[0054] The system further comprises:
[0055] A plurality of butterfly operation modules are configured to perform data reading in a single-parallel or multi-parallel manner on the data required for the NTT operation stored in the block random access memory in several stages according to the actual address data, and perform butterfly operation on the data required for the NTT operation read in each stage; the data reading process includes data exchange of the data required for the NTT operation between different block random access memories.
[0056] Specifically, in this embodiment, the butterfly operation module is a module that performs operations after data is read. The butterfly operation module performs butterfly operations on the read data required for the NTT operation, thereby realizing rapid encryption of the key.
[0057] The butterfly operation module can read data through single parallel or multi-parallel operations, and can achieve multiple times the efficiency of single parallel reading in one multi-parallel reading.
[0058] After the butterfly operation module completes the butterfly operation on two pairs of data required for the NTT operation, it exchanges the two pairs of data. The exchanged data is the data required for reading and calculation in the next stage. This process can be understood as: after completing the butterfly operation on two pairs of data required for the NTT operation, the calculation results are stored in the corresponding block random access memory, and the two pairs of data are exchanged.
[0059] It should be noted that data exchange is not carried out after the reading and calculation of one stage are completed. Data exchange can be carried out after the data to be exchanged is read and calculated. The remaining data that has not been read and calculated will continue to be read and calculated, and data exchange will be carried out again after the reading and calculation are completed.
[0060] It should be noted that the butterfly operation module adopts in-situ reading and writing, that is, reading and writing are both done in the same way. This embodiment is only introduced from the perspective of reading, but it is not limited to reading. Among them, this embodiment is about the data access method of fast number theory transformation, so first briefly introduce the fast number theory transformation. The formula of the number theory transformation based on negative wrapping convolution is as follows:
[0061] Forward transformation:
[0062] Inverse transform:
[0063] Then, by applying some techniques of fast Fourier transform (divide and conquer), we can get fast number theory transform. For the specific data flow of fast number theory transform, see Figure 2 and Figure 3 .
[0064] Figure 2 Data flow graph for the forward transform of base-2 fast number theoretic transform.
[0065] Figure 3 Data flow graph for the inverse transform of radix-2 fast number theoretic transform.
[0066] Figure 4 Schematic diagram of the position exchange method and reading order of the 8-point NTT.
[0067] See also Figure 2 、 Figure 3 as well as Figure 4It can be seen that in the first stage of the 8-point NTT, the 0th number and the 4th number, the 1st number and the 5th number, the 2nd number and the 6th number, and the 3rd number and the 7th number are paired in butterfly operations, that is, paired in the manner of (0, 4), (1, 5), (2, 6), and (3, 7). The two numbers in each group need to be sent to the butterfly operation unit in the same clock cycle, which means that this embodiment requires at least two different RAMs, and the two numbers in each group need to be stored in two different RAMs (the same RAM can only read and write one data in a single cycle). However, the pairing method in the second stage is (0, 2), (1, 3), (4, 6), (5, 7), and the pairing method in the third stage is (0, 1), (2, 3), (4, 5), (6, 7). The different pairing methods in each stage mean that if the data in each stage is directly stored back to the original address after the butterfly operation is completed, it will not be possible to ensure that all the paired two numbers in the next stage are stored in different RAMs. Therefore, this embodiment needs to add an additional step, that is, based on the in-situ reading and writing, the two data at different addresses are swapped according to a certain rule to ensure that the data has been arranged in order in the memory as required before the next stage.
[0068] First, the original sequence is stored sequentially in two BRAMs (0, 1, 2, 3 in BRAM 0, 4, 5, 6, 7 in BRAM 1). This allows the two inputs required for a butterfly operation to be directly read from a single address. After the first stage, data 2, 4, 3, and 5 are swapped, leaving BRAM 0 with data 0, 1, 4, 5, and BRAM 1 with data 2, 3, 6, 7, respectively. Similarly, after the second stage, data 1, 2, 5, and 6 are swapped, leaving the numbers at the same addresses in the two BRAMs paired. However, the addresses of the numbers to be swapped vary from stage to stage, requiring dedicated logic to control the swapping at each stage. It can be found that in each stage (except the last stage), the data with the same address in the two BRAMs needs to be exchanged only once. Therefore, the data in the memory can be directly read in a specific order to perform butterfly operations. After each two sets of butterfly operations are completed, the data in BRAM No. 0 that participates in the even-numbered butterfly operations are exchanged with the data in BRAM No. 1 that participates in the odd-numbered butterfly operations.
[0069] The final reading order of each stage is 0x0, 0x2, 0x1, 0x3, 0x0, 0x1, 0x2, 0x3, 0x0, 0x1, 0x2, 0x3. This can be summarized as the following formula (this reading exchange method is applicable to base 2 NTT with an integer power of 2, not just 8-point base 2 NTT):
[0070] (1)
[0071] The read address of even-numbered butterfly operations is 0 to (len is the number of butterfly operations in this stage. Here, "a group of butterfly operations" means butterfly operations with the same rotation factor) If the read address of an even number of butterfly operations is 0 to Add the read address of the odd number of butterfly operations To len-1 (ie 0 to len-1) is not enough to cover all addresses, then the read address of the even number of butterfly operations continues to expand and increase. Part (while odd number of butterfly operations read address increase to the 2len-1 part).
[0072] (2)
[0073] Among them, raddr odd is the read address of the odd number of butterfly operations, raddr even The read address of the even-numbered butterfly operation is the read address of the odd-numbered butterfly operation plus the read address of the even-numbered butterfly operation.
[0074] (3) waddr = raddr
[0075] Waddr is the write address, raddr is the read address, and the write address and read address are consistent (in-situ reading and writing).
[0076] According to the above three formulas, the initial address generation module can be obtained.
[0077] The above are all for single parallel NTT. If you want to increase the degree of parallelism (since it is for base 2 NTT, the degree of parallelism only considers integer times 2), you need to add additional modules and make certain modifications to the original initial address generator.
[0078] Figure 5 Schematic diagram of single parallel 16-point NTT reading sequence.
[0079] Figure 6 Schematic diagram of the reading sequence of two parallel 16-point NTTs.
[0080] See also Figure 5 and Figure 6 It can be seen that after the parallelism is increased, the 8-point NTT diagram can no longer clearly show the rules, so this embodiment considers 16-point NTT.
[0081] To change single parallelism to dual parallelism, a strategy of parallelism in the first half and the second half can be adopted, that is, the original reading order 0, 1, 2, 3, 4, 5, 6, 7 is changed to 0, 1, 2, 3, 0', 1', 2', 3'. The data that should have been read in the 4th cycle is read out in the 0th cycle together with the data originally read in the 0th cycle, and input into two different butterfly operation units respectively (there is only one butterfly operation unit in single parallelism). The data that should have been read in the 5th cycle is read out in the 1st cycle together with the data originally read in the 1st cycle, and so on. At the same time, the exchange method remains the same as in single parallelism, that is, the data in BRAM No. 1 that participates in the even number of butterfly operations is exchanged with the data in BRAM No. 0 that participates in the odd number of butterfly operations.
[0082] in, Figure 6 Memory addresses are not marked because, with increased parallelism, the number of BRAM blocks must also increase (only the number of blocks is increased; the total capacity remains unchanged) to accommodate the need to read more data simultaneously (for two parallel NTTs, four data items must be read simultaneously per cycle, requiring four BRAM blocks). Simply splitting the original two BRAM blocks in half (upper and lower) cannot meet data read requirements (there may still be situations where two data items that need to be read in a cycle are in the same BRAM block), so special memory partitioning is required.
[0083] Figure 7 Schematic diagram of the reading sequence of two parallel 16-point NTTs.
[0084] Figure 8 This is a functional diagram of the address mapping module.
[0085] See also Figure 7 and Figure 8 As can be seen, the re-address partitioning still maintains the symmetry between the left and right sides (two numbers are stored in the same address), so this embodiment still only focuses on the addresses on one side. The re-address partitioning actually divides the original BRAMs 0 and 1 into two parts: 0x0, 0x5, 0x6, 0x3 and 0x1, 0x2, 0x4, 0x7. In this way, the number of BRAMs is increased from 2 to 4 (the original BRAM 0 becomes BRAMs 0 and 1, and the original BRAM 1 becomes BRAMs 2 and 3). This re-partitioning operation can be implemented by the address mapping module.
[0086] Figure 9 Schematic diagram of two parallel 16-point NTT address mapping modules.
[0087] Figure 10 Schematic diagram of the NTT address mapping module with P parallel nodes and N points.
[0088] For more points and more parallelism, the address division method follows the same rules (at least it is necessary to ensure that the number of points / parallelism is greater than or equal to 8, but in fact, the number of points / parallelism less than 8 is already a very extreme case and is unlikely to occur under normal circumstances).
[0089] As mentioned above, for multi-parallel scenarios, the first half and the second half are parallelized. The two-parallel scenario has already been demonstrated. Quad-parallel scenarios build on this by continuing the first-half and second-half parallelization. The same applies to octal and higher parallel scenarios. Because the addresses of each parallel are somewhat similar, this solution first generates the address of one parallel and then uses it to derive the addresses of the other parallels. Compared to directly generating the addresses of each parallel, this solution significantly reduces the control logic area, and the increased latency caused by the increased fan-out does not affect the critical path.
[0090] This embodiment has the following advantages:
[0091] The NTT memory address access logic, based on data exchange, avoids complex control logic through exchange without sacrificing control logic speed. Address conflicts caused by multiple parallel operations are addressed through address repartitioning, which is implemented through an address mapping module that consumes minimal resources. This solution is flexible and configurable, allowing for different circuits to be created based on different node counts and degrees of parallelism.
[0092] For ease of explanation, the above description has been made in conjunction with specific embodiments. However, the above discussion of some embodiments is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Based on the above teachings, various modifications and variations can be obtained. The above embodiments are selected and described to better explain the content of this disclosure, thereby enabling those skilled in the art to better use the embodiments.
Claims
1. A memory address access control system for fast number theory transformation, characterized in that: The system comprises: an initial address generation module, wherein the initial address generation module is configured to generate initial address data; an address mapping module, the address mapping module being configured to set an address mapping for the initial address data and generate actual address data; A plurality of block random access memories, wherein the block random access memories store data required for NTT operation, and the data required for NTT operation corresponds to the actual address data; A plurality of butterfly operation modules are configured to perform data reading in a single-parallel or multi-parallel manner on the data required for the NTT operation stored in the block random access memory in several stages according to the actual address data, and perform butterfly operation on the data required for the NTT operation read in each stage; the data reading process includes data exchange of the data required for the NTT operation between different block random access memories.
2. A memory address access control system for fast number theory transformation according to claim 1, characterized in that: The butterfly operation module is further configured to: The data required for the NTT operation stored in all block random access memories are read in a single or multi-parallel manner in several stages in the form of data pairs; the data pair reading is to simultaneously read a pair of data required for the NTT operation from at least two of the block random access memories, and the pair of data required for the NTT operation consists of two same-sequence data read in the same order from the two corresponding block random access memories; The butterfly operation module is further configured to: A butterfly operation is performed on two of the same-sequence data in a pair of data required for NTT operations.
3. A memory address access control system for fast number theory transformation according to claim 2, characterized in that: The butterfly operation module is further configured to: The data required for the NTT operation stored in all the block random access memories are read in single or multi-parallel in several stages in the form of data pairs and in a preset order; the preset order of each stage corresponds to the data required for the NTT operation required for the butterfly operation in each stage.
4. A memory address access control system for fast number theory transformation according to claim 3, characterized in that: The butterfly operation module is further configured to: After completing the data reading required for the NTT operation in one stage, the corresponding data read and located in the two corresponding block random access memories are exchanged. After the data exchange, the new same-sequence data in the two corresponding block random access memories are the data that need to be read in the next stage.
5. A memory address access control system for fast number theory transformation according to claim 4, characterized in that: The butterfly operation module is further configured to: When the address data reading of a phase is completed and the reading order of the address data reading in this phase is the target order, this phase is marked as a swap completion phase.
6. A memory address access control system for fast number theory transformation according to claim 4, characterized in that: The data exchange includes: The data that completes the even number of butterfly operations and the data that completes the odd number of butterfly operations in the corresponding block random access memories are exchanged, and the data that completes the even number of butterfly operations is the data in the same block random access memory, and the data that completes the odd number of butterfly operations is the block random access memory corresponding to the block random access memory to which the data that completes the even number of butterfly operations belongs.
7. A memory address access control system for fast number theory transformation according to claim 6, characterized in that: The ratio of the number of points storing data in all the block random access memories to the parallel number is not less than 8, and the number of the block random access memories and the parallel number are both powers of 2.
8. The memory address access control system for fast number theory transformation according to claim 7, characterized in that: The butterfly operation module is further configured to: When the number of the block random access memories is 2, the data required for the NTT operation stored in all the block random access memories are read in parallel in several stages.
9. The memory address access control system for fast number theory transformation according to claim 7, characterized in that: The butterfly operation module is further configured to: When the number of the block random access memories is not less than 4, multiple parallel readings are performed on the data required for the NTT operation stored in all the block random access memories in several stages.
10. The memory address access control system for fast number theory transformation according to claim 2, characterized in that: When performing multi-parallel reading, the block random access memory includes at least a first storage, a second storage, a third storage, and a fourth storage, and the butterfly operation module is further configured to: When performing two parallel reads, all data required for the NTT operation are stored in the first storage, the second storage, the third storage, and the fourth storage in sequence according to the address mapping; The data in the first storage and the second storage, and the data in the third storage and the fourth storage are read simultaneously.