Delay unit and broadband multi-subband ring oscillator circuit

Abstract

The invention discloses a delay unit and a broadband multi-sub-band ring oscillator circuit, the delay unit is characterized in that a PM5, a PM7, a PM13 and a first current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM3, the first current limiting tube comprises a PM9, a PM11 and sub-band control switches CB2 and CB12, a PM6, a PM8, a PM14 and a second current limiting tube are connected in parallel between a source electrode and a drain electrode of a PM4, and the second current limiting tube comprises a PM10, a PM12 and sub-band control switches CB2 and CB12; switched capacitors C1-C4 are arranged between the VOP and the VON; the first group of switched capacitors and the second group of switched capacitors are connected in parallel between the VOP and the VON; the first group of switched capacitors comprises C1 and C2 which are connected in series and CB1 for controlling the switching of the C1 and C2, and the second group of switched capacitors comprises C3 and C4 which are connected in series and CB2 for controlling the switching of the C3 and C4; grid electrodes of the PM5 and the PM6 are connected with the sub-band control switch RB1, grid electrodes of the PM7 and the PM8 are connected with the RB2, grid electrodes of the PM9 and the PM10 are connected with the CB2, grid electrodes of the PM11 and the PM12 are connected with the CB12, and a control signal of the CB12 is generated by control signals of the CB1 and the CB2 through an AND gate.

Description

Technical Field

[0001] The present invention belongs to the field of circuit design and relates to an oscillator circuit, in particular to a delay unit and a broadband multi-subband ring oscillator circuit. Background Art

[0002] Phase-locked loop (PLL) circuits are widely used in various circuit systems. For example, in serial data transmission systems, PLLs provide high-frequency, high-quality reference clocks for high-speed serial circuits. This high-frequency clock is typically generated by an internal oscillator within the PLL. Therefore, low-jitter, wide-bandwidth oscillators are highly adaptable and widely used.

[0003] In the RF chip design industry, the mainstream oscillator designs are either capacitor-inductor resonant or ring oscillator based on delayed feedback of unit circuit signals. The former has a higher quality factor than the latter, and with similar power consumption and output frequency, the former offers better phase noise performance. However, inductors often occupy a large area and require process support, while ring oscillators are relatively small and easy to design and integrate, making them a preferred choice for some applications, including the present invention.

[0004] A ring oscillator is typically constructed by connecting k basic units in a ring. For single-ended units, k is an odd number ≥3, while for differential units, k is an integer ≥2. A single-ended unit refers to a delay unit that transmits CMOS signals and has only one input and output, while a differential unit refers to a delay unit that transmits differential signals and has a pair of differential inputs and a pair of differential outputs. To ensure successful ring oscillation, whether using single-ended or differential units, they must be connected to form a negative feedback circuit and must meet two Barkhausen criteria: first, the total phase shift of the loop must be 180°; second, the gain of the loop at a 180° phase shift must be ≥1. Taking into account variations in process and temperature conditions, this gain is typically at least >2. Defining the signal delay from the input to the output of a basic unit as T0, the oscillation period of the ring oscillator is 2kT0.

[0005] Phase noise (abbreviated as phase noise) is an important indicator for measuring oscillator performance. Generally, ring oscillators using differential units exhibit better phase noise performance than single-ended units. For ring oscillators with exactly the same structure, phase noise can be reduced by optimizing the transistor size, which usually increases power consumption. The oscillator forms a phase-locked loop, which requires adding a control voltage (VC) and circuit to tune the oscillation frequency. The jitter of VC directly affects the stability of the output frequency. Therefore, reducing the sensitivity of the output frequency to changes in VC, that is, the frequency gain Kvco, can improve the phase noise to a certain extent. However, a reduction in Kvco will significantly reduce the output frequency range, limiting its application. Therefore, differential units usually adopt a multi-subband design method to ensure a sufficient frequency range.

[0006] The existing multi-subband differential unit implementation methods include load resistance control type and load capacitance control type. Figure 1 As shown in the figure, it is a delay unit design of load resistance control type multi-subband ring voltage-controlled oscillator. M1 and M2 are N-type input pairs, and M3 and M4 form a cross-coupled pair to realize the reverse of the output end, so as to provide a larger differential output swing and a frequency tuning range. The adjustment of the subband is realized by controlling the gate voltage of M5-M12 to change the output load resistance, so as to change the final output frequency.

[0007] Figure 2 The output frequency curve of the load resistance control type, and the load capacitance type is realized by directly connecting a controllable capacitance array in parallel at the output node, Figure 3 The output frequency curve of the load resistance control type, and the load capacitance type is realized by directly connecting a controllable capacitance array in parallel at the output node, The difference between the two methods is that the frequency band is opposite, and the change of the load resistance is generally dense at high frequency and sparse at low frequency, while the change of the load capacitance is sparse at high frequency and dense at low frequency. SUMMARY

[0008] In view of the problems in the prior art, the purpose of the present application is to provide a delay unit and a wideband multi-subband ring oscillator circuit. The present application is based on the circuit architecture of controlling load resistance and switch capacitor, realizes a wideband, multi-frequency curve (subband) ring voltage-controlled oscillator circuit, which can solve the problem of phase noise performance deterioration caused by the excessive frequency gain of the classical ring voltage-controlled oscillator; on the other hand, it can reduce the difference between the frequency gains (Kvco) of each subband, and when the ring voltage-controlled oscillator is used as the core to form a phase-locked loop circuit, it can solve the problem of phase-locked loop performance deterioration and performance stability caused by the excessive difference of Kvco in the entire phase-locked loop frequency range.

[0009] The key point of the present application is to provide a wideband, capacitance and equivalent load resistance dual adjustment, multi-subband ring oscillator design scheme, which can solve the problem of uneven subband distribution and excessive frequency gain difference of the multi-subband ring oscillator in a wide output frequency range.

[0010] The technical scheme of the present application is as follows:

[0011] A delay unit includes a first cross-coupled pair of PMOS transistors PM1 and PM2, a second cross-coupled pair of NMOS transistors NM1 and NM2, a pair of NMOS differential input transistors NM3 and NM4, and a pair of voltage-controlled transistors PM3 and PM4. The two cross-coupled pairs form two connected inverters between a positive output signal terminal VOP and a negative output signal terminal VON, so that the output maintains a logical inversion. The delay unit is characterized in that a plurality of PMOS transistors PM5, PM7, and PM13 and a first current-limiting transistor are connected in parallel between the source and drain of the voltage-controlled transistor PM3. The first current-limiting transistor includes PMOS transistors PM9 and PM11 and sub-band control switches CB2 and CB12. A plurality of PMOS transistors PM6, PM8, and PM14 and a second current-limiting transistor are connected in parallel between the source and drain of the voltage-controlled transistor PM4. The second current-limiting transistor includes PMOS transistors PM10 and PM12 and sub-band control switches CB2 and CB12. A plurality of switching capacitors C1 to C4 are provided between the differential output terminals VOP and VON.

[0012] The first group of switched capacitors and the second group of switched capacitors are connected in parallel between VOP and VON; the first group of switched capacitors includes C1 and C2 connected in series and a sub-band control switch CB1 that controls their switching; the second group of switched capacitors includes C3 and C4 connected in series and a sub-band control switch CB2 that controls their switching;

[0013] The gates of PM5 and PM6 are connected to the sub-band control switch RB1, the gates of PM7 and PM8 are connected to the sub-band control switch RB2, the gates of PM9 and PM10 are connected to the sub-band control switch CB2, the gates of PM11 and PM12 are connected to the sub-band control switch CB12, the gates of PM13 and PM14 are connected to the ground line VSS, and the control signal of CB12 is generated by the control signals of CB1 and CB2 through the AND gate; RB1 and RB2 are used to adjust the load resistance. When the control signal is low, the corresponding PM5, PM6, PM7, PM8 are connected to the sub-band control switch CB2. When M8 is turned on, the load resistance becomes smaller, the branch current becomes larger, and the oscillation frequency becomes higher; CB1 and CB2 are used to adjust the load capacitance. When the control signal is high, the corresponding C1~C4 switches are turned on, the load capacitance becomes larger, and the oscillation frequency becomes lower; when the control signal of CB2 is high, the C3 and C4 capacitors are turned on, and the corresponding PM9 and PM10 are turned off; when the control signals of CB1 and CB2 are both high, all capacitors C1~C4 are turned on, and the corresponding PM9~PM12 are turned off; when CB1 and CB2 are both low, C1~C4 are in the disconnected state.

[0014] Furthermore, the width-to-length ratio of the PMOS coupling pair is twice the width-to-length ratio of the NMOS coupling pair.

[0015] Furthermore, the width-to-length ratio of PM1 and PM2 corresponding to the PMOS coupling pair is 18, and the width-to-length ratio of NM3 and NM4 corresponding to the NMOS coupling pair is 9; C1 and C2 are each composed of one capacitor unit in parallel, and C3 and C4 are each composed of two capacitor units in parallel.

[0016] Furthermore, C1 is connected in series with C2 via CB1 to serve as a first group of switched capacitors, and C3 is connected in series with C4 via CB2 to serve as a second group of switched capacitors.

[0017] Furthermore, the aspect ratio of PM3 and PM4 is 7, the aspect ratio of PM5 and PM6 is 2, the aspect ratio of PM7 and PM8 is 4, the aspect ratio of PM9 and PM10 is 1, the aspect ratio of PM11 and PM12 is 4, and the aspect ratio of PM13 and PM14 is 15.

[0018] Furthermore, when the resistor-type control bit is expanded, for each additional resistor-type control bit, a PMOS transistor is connected in parallel between the source and drain of the voltage-controlled transistor PM3, and a PMOS transistor is connected in parallel between the source and drain of the voltage-controlled transistor PM4, and both are controlled by the same control bit. The width-to-length ratio of the added pair of PMOS transistors increases exponentially with a value of 2. That is, when the added resistor-type control bit is the Nth resistor-type control bit RBN, the width-to-length ratio of the corresponding added pair of PMOS transistors is W / L=2. N When the capacitance control bit is expanded, each time a capacitance control bit is added, a set of parallel switching capacitors is added between VOP and VON and the switches of the capacitors are controlled by the same control bit. The number of capacitance units in the added set of switching capacitors increases exponentially with a ratio of 2. That is, when the added capacitance control bit is the Nth capacitance control bit CBN, the number of parallel capacitance units of the switching capacitors C2N-1 and C2N in the corresponding added set of switching capacitors is 2. N-1 .

[0019] A broadband multi-subband ring oscillator circuit is characterized by comprising a plurality of delay units, wherein the delay units are connected, and the output end of the last delay unit is connected to a duty cycle correction circuit.

[0020] Furthermore, three delay units are included.

[0021] Furthermore, the width-to-length ratio of the PMOS coupling pair is twice the width-to-length ratio of the NMOS coupling pair.

[0022] Furthermore, C1 and C2 are each composed of one capacitor unit in parallel, and C3 and C4 are each composed of two capacitor units in parallel; the width-to-length ratio of PM3 and PM4 is 7, the width-to-length ratio of PM5 and PM6 is 2, the width-to-length ratio of PM7 and PM8 is 4, the width-to-length ratio of PM9 and PM10 is 1, the width-to-length ratio of PM11 and PM12 is 4, and the width-to-length ratio of PM13 and PM14 is 15.

[0023] The advantages of the present invention are as follows:

[0024] The solution proposed in this invention, based on a combination of load resistors and capacitor switches, achieves a wide frequency tuning range, reduces the frequency gain Kvco, and minimizes the variance in Kvco across multiple sub-bands. This, in turn, mitigates phase noise degradation and loop stability issues that can arise from large or varying Kvcos in a phase-locked loop. Furthermore, with this architecture, the number of control switches for the load resistors and capacitors, as well as the number or size ratio of the switching transistors, can be flexibly adjusted based on the desired frequency range and number of sub-bands. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a resistive load controlled delay unit similar to this design.

[0026] Figure 2 This is the simulation result of the load resistance control type.

[0027] Figure 3 This is the simulation result of the load capacitance control type.

[0028] Figure 4 It is the structural framework of the differential ring oscillator.

[0029] Figure 5 It is the basic delay unit structure.

[0030] Figure 6 is Figure 5 The delay unit after adding equivalent load resistance and load capacitance is constructed.

[0031] Figure 7 It is the simulation result of the output frequency of the oscillator of the present invention.

[0032] Figure 8 It is a delay unit with a resistor-type control bit extended to 3 bits.

[0033] Figure 9 It is a delay unit with the resistive control bit extended to N bits.

[0034] Figure 10 It is a delay unit with the capacitance control bit extended to N bits. DETAILED DESCRIPTION

[0035] The present invention will be described in further detail below with reference to the accompanying drawings. The examples given are only used to explain the present invention and are not used to limit the scope of the present invention.

[0036] The present invention adopts a hybrid regulation method, combining load resistance and load capacitance control, adding current limiting control logic and transistors, and can reduce the Kvco value and the Kvco difference between each sub-band while achieving a wide frequency range, thereby ensuring the phase noise performance of the ring oscillator.

[0037] Figure 4 The ring oscillator example illustrated in the present invention utilizes three identical differential units and an output stage (for duty cycle correction); it can also be constructed with any integer number of differential units (k ≥ 2) and an output stage. However, the greater the number of stages, the lower the oscillation frequency and the smaller the output frequency range. On the other hand, the smaller the number of stages, the greater the phase shift required by each differential unit, and the higher the gain requirement. Therefore, to ensure a sufficiently wide frequency range and oscillation conditions, k of 2 or 3 is optimal, with k = 3 being used as an example. Each delay unit includes a pair of differential inputs (VIP and VIN) and differential output ports (VOP and VON), a voltage-controlled port (VC), four sub-band control switches (RB1, RB2, CB1, and CB2), and power and ground (VDD and VSS). The three differential units are cross-connected, with the positive output signal VOP of the previous delay unit connected to the negative input VIN of the next delay unit, and the negative output signal VON connected to the positive input VIP of the next delay unit. The output terminals (net5 and net6) of the last differential unit are connected to a duty cycle correction circuit to convert the differential signal into a large-swing CMOS signal output and ensure a 50% duty cycle of the output clock.

[0038] Figure 5 The figure shows the basic differential delay unit circuit structure used in the present invention, which includes a pair of NMOS differential input transistors (NM3 and NM4), a pair of voltage-controlled transistors (PM3 and PM4) as equivalent load resistors, a pair of PMOS cross-coupled pairs (PM1 and PM2), and a pair of NMOS cross-coupled pairs (NM1 and NM2). These two sets of cross-coupled pairs form two connected inverters between the output nodes VOP and VON, maintaining the output logic inverse. To ensure normal circuit oscillation, the width-to-length ratio (W / L) of the PMOS and NMOS coupling pairs must meet a 2:1 relationship, that is, (W / L) PM1PM2 :(W / L) NM1NM2 =2:1. The delay of the delay unit depends on the time it takes for the output to rise from a low level to a high level. Since the delay unit is a cascade structure, this time can be expressed as the output current of the previous stage ( Figure 5The charge and discharge time of I1 and I2 in the output node capacitance and the gate capacitance of the next stage input transistor (NM3~4). By adjusting the gate voltage (VC) of PM3 and PM4, the equivalent resistance (R LP and R LN ), and at the same time changes the current in the output branch (I1 and I2), thereby changing the unit delay.

[0039] Figure 6 The multi-subband delay unit circuit used in the present invention is shown in FIG. Figure 5 On the basis of the PMOS transistors (PM5 to PM14) that can be turned on and off, the output node equivalent load resistance (R LP and R LN ); At the same time, multiple switch capacitors (C1 to C4) are added between the differential outputs to adjust the equivalent load capacitance (C LP and C LN ). RB1, RB2, CB1, CB2 are sub-band control switches (red), which can be used to switch the oscillator output frequency sub-band; among them, RB1 and RB2 adjust the load resistance. When the control signal is low, PM5~PM8 are turned on, the load resistance becomes smaller, the branch current becomes larger, and the oscillation frequency becomes higher; CB1 and CB2 adjust the load capacitance. When the control signal is high, the corresponding capacitor switch is turned on, the load capacitance becomes larger, and the oscillation frequency becomes lower. When the load resistance and capacitance adjustment are combined, PM9 and PM10 need to be added to be controlled by CB2, and CB12 needs to be added to control PM11 and PM12. CB12 is controlled by CB1 and CB2 through the AND gate ( Figure 6 I1 device in the middle); when CB2 is high, the C3 and C4 capacitor switches are turned on, and the corresponding PM9 and PM10 are closed; when CB1 and CB2 are both high and all capacitors are turned on, the corresponding PM9 to PM12 are all closed; when CB1 and CB2 are low, C1 and C2, C3 and C4 are disconnected. All capacitors are composed of capacitor units of the same size, among which C1 and C2 are respectively composed of 1 capacitor unit in parallel (ie m=1), and C3 and C4 are respectively composed of 2 capacitor units in parallel (ie m=2). By limiting the current in this way, it is ensured that the sub-bands generated by the two adjustment methods do not cross or overlap, and their uniformity is guaranteed. Through the 4-bit control of RB1, RB2, CB1, and CB2, 16 sub-bands can be achieved. The design of each transistor size refers to Figure 6 The normalized W / L relationship shown can ensure uniformity of multiple sub-bands and reduce Kvco differences. Figure 7 Based on Figure 6 The simulation results obtained from the circuit show that a ring oscillator with a frequency range of up to 2.71 GHz and a small Kvco difference is achieved.

[0040] In addition, both the resistive and capacitive control bits can be expanded. For the resistive control bit expansion, each additional control bit requires adding a pair of PMOS transistors between the output node (VON, VOP) and the voltage, controlled by the same control bit, such as PM5 and PM6 (or PM7 and PM8). The width-to-length ratio generally increases in an exponential relationship of 2. Figure 6 On the basis of expansion, under the premise of not changing or slightly changing the output frequency range, it can only be expanded to 3 control bits, such as Figure 8 As shown in the figure, if PM15 and PM16 are added, W / L=8, while the previous PM13 and PM14 need to be reduced to W / L=7, and the other designs remain unchanged. If the problem of lowering the upper frequency limit caused by further adding resistance-type control bits is not considered, the resistance bits can theoretically be expanded infinitely, such as Figure 9 As shown in FIG, when the resistive control bits exceed 3, the sizes of PM13 and PM14 are reduced to 0, while the W / L of the newly added controlled transistors still increases in an exponential relationship of 2.

[0041] Capacitor control bit expansion is to add a group of switched capacitors, such as capacitor C1, switch CB1 and capacitor C2 connected in series between the output nodes VON and VOP, which is a group of switched capacitors; another connection method can also be used, where capacitors C1 and C2 are connected in series with two identical switches, and then connected between VON and VOP and ground or power respectively. Both switches are controlled by CB1 (such as Figure 6 Another switched capacitor connection is shown in ). The number of capacitor units in the switched capacitor group ( Figure 6 m) also increases in an exponential relationship of 2, but there is still a certain unevenness problem between the sub-bands. Therefore, as mentioned above, the present invention proposes to increase the corresponding current limiting PMOS tube (such as Figure 6 PM9 to PM12 in the circuit are used to compensate for the difference between capacitance control and resistance control to ensure the uniformity of the sub-bands. Among them, PM9 and PM10 are controlled by CB2, and PM11 and PM12 are controlled by the internal signal CB12. When the capacitance control bit increases, the size, number, corresponding gate control signal and control signal generation circuit of the original current limiting PMOS tube (PM9 to PM12) are changed. Figure 6 I1) needs to be adjusted according to the specific number of control bits, but without exception, the structure proposed by the present invention can be adopted.

[0042] The extended delay unit of the present invention is as follows Figures 8 to 10 As shown, when the total control bits increase to M bits, theoretically 2 M Each sub-band can be fine-tuned by adjusting VC for stepless output frequency adjustment.

[0043] While specific embodiments of the application have been disclosed in order to illustrate the application and to assist those skilled in the art in practicing the application, it is to be understood that various substitutions, modifications and changes can be made by those skilled in the art without departing from the spirit of the application and the scope of the appended claims. Accordingly, it is intended that the application not be limited, except by the scope of the claims.

Claims

1. A delay unit comprising a first cross-coupled pair of PMOS transistors PM1 and PM2, a second cross-coupled pair of NMOS transistors NM1 and NM2, a pair of NMOS differential input transistors NM3 and NM4, and a pair of voltage-controlled transistors PM3 and PM4; the two cross-coupled pairs forming two connected inverters between a positive output signal terminal VOP and a negative output signal terminal VON to maintain a logically reversed output; characterized in that: A plurality of PMOS transistors PM5, PM7, PM13 and a first current limiting transistor are connected in parallel between the source and drain of the voltage-controlled transistor PM3. The first current limiting transistor includes PMOS transistors PM9, PM11 and sub-band control switches CB2, CB12. A plurality of PMOS transistors PM6, PM8, PM14 and a second current limiting transistor are connected in parallel between the source and drain of the voltage-controlled transistor PM4. The second current limiting transistor includes PMOS transistors PM10, PM12 and sub-band control switches CB2, CB12. A plurality of switching capacitors C1 to C4 are provided between the differential output terminals VOP and VON. The first group of switched capacitors and the second group of switched capacitors are connected in parallel between VOP and VON; the first group of switched capacitors includes C1 and C2 connected in series and a sub-band control switch CB1 that controls their switching; the second group of switched capacitors includes C3 and C4 connected in series and a sub-band control switch CB2 that controls their switching; The gates of PM5 and PM6 are connected to the sub-band control switch RB1, the gates of PM7 and PM8 are connected to the sub-band control switch RB2, the gates of PM9 and PM10 are connected to the sub-band control switch CB2, the gates of PM11 and PM12 are connected to the sub-band control switch CB12, the gates of PM13 and PM14 are connected to the ground line VSS, and the control signal of CB12 is generated by the control signals of CB1 and CB2 through the AND gate; RB1 and RB2 are used to adjust the load resistance. When the control signal is low, the corresponding PM5, PM6, PM7, PM8 are connected to the sub-band control switch CB2. When M8 is turned on, the load resistance becomes smaller, the branch current becomes larger, and the oscillation frequency becomes higher; CB1 and CB2 are used to adjust the load capacitance. When the control signal is high, the corresponding C1~C4 switches are turned on, the load capacitance becomes larger, and the oscillation frequency becomes lower; when the control signal of CB2 is high, the C3 and C4 capacitors are turned on, and the corresponding PM9 and PM10 are turned off; when the control signals of CB1 and CB2 are both high, all capacitors C1~C4 are turned on, and the corresponding PM9~PM12 are turned off; when CB1 and CB2 are both low, C1~C4 are in the disconnected state.

2. The delay unit according to claim 1, wherein: The width-to-length ratio of the PMOS coupling pair is twice the width-to-length ratio of the NMOS coupling pair.

3. The delay unit according to claim 2, wherein: The width-to-length ratio of PM1 and PM2 corresponding to the PMOS coupling pair is 18, and the width-to-length ratio of NM3 and NM4 corresponding to the NMOS coupling pair is 9; C1 and C2 are each composed of one capacitor unit connected in parallel, and C3 and C4 are each composed of two capacitor units connected in parallel.

4. The delay unit according to claim 1, 2 or 3, wherein: C1 is connected in series with C2 via CB1 to serve as the first set of switched capacitors, and C3 is connected in series with C4 via CB2 to serve as the second set of switched capacitors.

5. The delay unit according to claim 1, 2 or 3, characterized in that: The width-to-length ratio of PM3 and PM4 is 7, the width-to-length ratio of PM5 and PM6 is 2, the width-to-length ratio of PM7 and PM8 is 4, the width-to-length ratio of PM9 and PM10 is 1, the width-to-length ratio of PM11 and PM12 is 4, and the width-to-length ratio of PM13 and PM14 is 15.

6. The delay unit according to claim 1, 2 or 3, characterized in that: When the resistor-type control bit is expanded, for each additional resistor-type control bit, a PMOS transistor is connected in parallel between the source and drain of the voltage-controlled transistor PM3, and a PMOS transistor is connected in parallel between the source and drain of the voltage-controlled transistor PM4, and they are controlled by the same control bit. The width-to-length ratio of the added pair of PMOS transistors increases exponentially with 2. That is, when the added resistor-type control bit is the Nth resistor-type control bit RBN, the width-to-length ratio of the corresponding added pair of PMOS transistors is W / L=2. N When the capacitance control bit is expanded, each time a capacitance control bit is added, a set of parallel switching capacitors is added between VOP and VON and the switches of the capacitors are controlled by the same control bit. The number of capacitance units in the added set of switching capacitors increases exponentially with a ratio of 2. That is, when the added capacitance control bit is the Nth capacitance control bit CBN, the number of parallel capacitance units of the switching capacitors C2N-1 and C2N in the corresponding added set of switching capacitors is 2. N-1 .

7. A broadband multi-subband ring oscillator circuit, characterized in that: The invention comprises a plurality of delay units as claimed in claim 1, wherein the delay units are connected, and the output end of the last delay unit is connected to a duty cycle correction circuit.

8. The broadband multi-sub-band ring oscillator circuit according to claim 7, wherein: The device comprises three delay units as claimed in claim 1.

9. The broadband multi-sub-band ring oscillator circuit according to claim 8, characterized in that: The width-to-length ratio of the PMOS coupling pair is twice the width-to-length ratio of the NMOS coupling pair.

10. The broadband multi-sub-band ring oscillator circuit according to claim 7, 8 or 9, characterized in that: C1 and C2 are each composed of one capacitor unit in parallel, and C3 and C4 are each composed of two capacitor units in parallel; the width-to-length ratio of PM3 and PM4 is 7, the width-to-length ratio of PM5 and PM6 is 2, the width-to-length ratio of PM7 and PM8 is 4, the width-to-length ratio of PM9 and PM10 is 1, the width-to-length ratio of PM11 and PM12 is 4, and the width-to-length ratio of PM13 and PM14 is 15.

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