Calibration method and system for high-speed pipelined ADC

Abstract

The invention provides a calibration method and system for a high-speed pipelined ADC, input signals of the high-speed pipelined ADC are respectively input into a first-stage MDAC and a first-stage sub-ADC, and the calibration method is characterized by comprising the following steps: injecting a pseudorandom sequence into the first-stage ADC and a comparator of the first-stage MDAC at the same time, wherein the pseudo-random sequence is used for representing a sequence number of a comparator corresponding to a comparator threshold value; estimating a threshold deviation of each comparator and a matching delay of an analog front-end network of the first-stage sub-ADC in a digital domain; and generating a corresponding trimming code according to the threshold deviation and the matching delay, and feeding back the trimming code to the high-speed pipelined ADC to complete calibration. The device is small in occupied layout area, low in power consumption, high in trimming speed, large in trimming range and capable of adapting to different processes and application environments.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit design, and particularly relates to a calibration method and system of a high-speed pipeline ADC. BACKGROUND

[0002] The development of portable electronic devices and wireless communication devices increases the demand for low-power high-speed high-resolution analog-to-digital converters (ADCs). Pipeline ADCs are suitable for high-speed and high-resolution applications, but the use of a large number of comparators, operational amplifiers and other circuit units in multiple pipeline stages increases power consumption and cost. In addition, the accuracy of the first stage determines the overall accuracy of the pipeline ADC, and in high-accuracy applications, special attention should be paid to the performance of the first stage during circuit design. Since about 70% of the power consumption of the pipeline ADC comes from the operational amplifier, in order to meet the low-power requirement, the industry generally adopts a pipeline ADC architecture without a front-end sample-and-hold amplifier (SHA). In some ultra-low-power pipeline ADCs, the comparator discards the front-end preamplifier to further reduce power consumption, but this brings additional challenges to the sampling and comparison accuracy of the signal, and it is difficult to meet the accuracy requirements of the first-stage pipeline ADC. In the pipeline ADC, process deviation will cause deviation of the comparator threshold. In the scene of high-frequency input signal, the absence of a sample-and-hold structure will cause the ADC to have an analog front-end network matching problem, which reduces the performance in high-speed conversion applications. Digital algorithm correction has become one of the main tools to improve performance and reduce power consumption, and its purpose is to relax the requirements on analog design and correct the errors caused thereby in a digital manner. Traditional digital correction methods have defects such as large occupied area, long convergence time, low accuracy, and difficulty in following the change of input frequency. SUMMARY

[0003] The present application provides a calibration method and system of a high-speed pipeline ADC to solve the problems of comparator threshold deviation caused by production process, analog front-end network matching problem caused by the absence of a sample-and-hold structure, and large occupied area, long convergence time, low accuracy, and difficulty in following the change of input frequency of traditional digital correction.

[0004] The present invention provides a calibration method for a high-speed pipelined ADC, wherein input signals of the high-speed pipelined ADC are respectively input into a first-stage MDAC and a first-stage sub-ADC. The calibration method comprises: simultaneously injecting a pseudo-random sequence into the comparators of the first-stage ADC and the first-stage MDAC, wherein the pseudo-random sequence is used to characterize the arrangement sequence of the comparator thresholds corresponding to the comparators; estimating the threshold deviation of each comparator and the matching delay of the analog front-end network of the first-stage sub-ADC in the digital domain; generating corresponding adjustment codes based on the threshold deviations and the matching delays, and feeding the adjustment codes back to the high-speed pipelined ADC to complete the calibration.

[0005] In one embodiment of the present application, the step of estimating the threshold deviation of the comparator in the digital domain includes: obtaining the output code value of the first-stage sub-ADC, and determining a valid data sequence in the digital domain for estimating the error based on the output code value; generating a sum sequence based on the output code value and the highest bit of the valid data sequence; positioning the comparator based on the sum sequence and the pseudo-random sequence, and initiating threshold deviation calculation after positioning is completed to obtain the threshold deviation.

[0006] In one embodiment of the present application, the step of calculating the threshold deviation includes: taking the data other than the highest bit in the valid data sequence as input for the threshold deviation calculation; when the highest bit of the valid data sequence is a first value, accumulating the data other than the highest bit; when the highest bit of the valid data sequence is a second value, accumulating the data other than the highest bit in the valid data sequence with a first preset value; generating a multi-bit data segment number based on the accumulated data; loading the data segment number through multiple registers to obtain a signed number of a preset number of bits and sending it to a comparator, comparing it with a preset unsigned threshold, and enabling the corresponding two-bit trimming control; converting the pseudo-random sequence into a threshold trimming signal of a first preset number of bits, and generating a trimming control code corresponding to each threshold in combination with the corresponding trimming enable signal, wherein each two bits in the trimming control code control one threshold trimming, corresponding to a positive trimming value or a negative trimming value respectively.

[0007] In one embodiment of the present application, the refresh of the output code value of the first-stage sub-ADC is controlled by accumulating input data corresponding to the input signal, wherein the refresh period is determined by a multiple of the clock period of the first-stage sub-ADC.

[0008] In one embodiment of the present application, the calculation step of the matching delay includes: locating the corresponding comparator according to the pseudo-random sequence; determining the first sequence according to the valid data sequence of the located comparator and the corresponding data segment number; accumulating the absolute values ​​of the negative inputs of the first sequence to obtain a first accumulation result; accumulating the absolute values ​​of the positive inputs of the first sequence to obtain a second accumulation result; determining a third accumulation result according to the difference between the second accumulation result and the first accumulation result, and using it as the first input sequence after a preset first delay; determining a fourth accumulation result according to the sum of the first accumulation result and the second accumulation result, and intercepting a specified number of bits of data in the fourth accumulation result as the second input sequence; when the data in the second input sequence is greater than twice the data in the first input sequence, determining that there is a matching delay and enabling the first control signal; the fourth accumulation result is used as the third input sequence after a preset second delay; if the third input sequence is greater than 2 21 , it is determined that there is a matching delay, and the second control signal is enabled; the fourth accumulated result is delayed for one cycle as the previous cycle data, and the fourth accumulated result is recorded as the current cycle data, and the error change trend is determined according to the previous cycle data and the current cycle data, and a third control signal and a fourth control signal are generated according to the error change trend; the jump of the state machine is jointly determined by the first control signal, the second control signal, the third control signal and the fourth control signal, wherein the first control signal and the second control signal are used to enable the state machine, and the third control signal and the fourth control signal determine the jump direction of the state machine.

[0009] In one embodiment of the present application, the calibration method further includes providing an SPI interface to verify the trimming control code, and solidifying the code through a fuse after the verification is completed.

[0010] In one embodiment of the present application, the calibration method further includes: modifying the segment interval length of the data segment number through the SPI interface, thereby adjusting the calculation step size.

[0011] In one embodiment of the present application, the pseudo-random sequence is simultaneously injected into the comparator of the first-stage ADC and the first-stage MDAC by means of disturbance injection. The disturbance injection step includes: determining a disturbance injection weight in the digital domain according to the disturbance injection capacitor, the first-stage sampling injection capacitor, and the weight of the first-stage sampling injection capacitor; determining a corresponding disturbance injection amount according to the disturbance injection weight, and performing disturbance injection based on the disturbance injection amount.

[0012] The present invention also provides a calibration system for a high-speed pipelined ADC, which is applied to the calibration of the high-speed pipelined ADC. The input signal of the high-speed pipelined ADC is respectively input into a first-stage MDAC and a first-stage sub-ADC. The calibration system includes: a pseudo-random sequence generation module, configured to simultaneously inject a pseudo-random sequence into the comparators of the first-stage ADC and the first-stage MDAC, wherein the pseudo-random sequence is used to characterize the arrangement sequence of the comparator threshold corresponding to the comparator; an error calibration module, configured to estimate the threshold deviation of each comparator and the matching delay of the analog front-end network of the first-stage sub-ADC in the digital domain; generate a corresponding adjustment code based on the threshold deviation and the matching delay, and feed the adjustment code back to the high-speed pipelined ADC to complete the calibration.

[0013] Beneficial effects of the present invention: The present invention proposes a high-speed pipeline ADC calibration method and system, which can simultaneously perform threshold error and matching delay estimation by multiplexing pseudo-random sequences, and feed back the adjustment code to the analog circuit to realize automatic adjustment function, meet the requirements of high-precision application scenarios, and occupy a small layout area. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be derived from these drawings without inventive effort.

[0015] In the attached figure:

[0016] Figure 1 A schematic diagram of the circuit architecture of an existing high-speed pipeline ADC;

[0017] Figure 2 Schematic diagram of the system architecture for high-speed pipeline ADC calibration in one embodiment of the present application;

[0018] Figure 3 is a schematic diagram of a comparator circuit in one embodiment of the present invention;

[0019] Figure 4 A schematic flow chart of a high-speed pipeline ADC calibration method provided in one embodiment of the present invention;

[0020] Figure 5 Schematic diagram of the logic architecture of threshold deviation calculation in one embodiment of the present invention;

[0021] Figure 6 Schematic diagram of the logical architecture of matching delay calculation in one embodiment of the present invention;

[0022] Figure 7 FIG. 4 is a block diagram of a high-speed pipeline ADC calibration system provided in one embodiment of the present invention. DETAILED DESCRIPTION

[0023] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments. The details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention. The following embodiments and features therein may be combined with one another without conflict.

[0024] It should be noted that the illustrations provided in the following embodiments are merely schematic illustrations of the basic concept of the present invention. The drawings only show components related to the present invention and are not drawn according to the number, shape, and size of components in actual implementation. In actual implementation, the type, quantity, and proportion of each component may be changed arbitrarily, and the component layout may also be more complex.

[0025] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present invention. However, it will be apparent to those skilled in the art that the embodiments of the present invention may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present invention.

[0026] The inventors have discovered that:

[0027] See also Figure 1 , Figure 1 This diagram shows the circuit architecture of an existing high-speed pipeline ADC. In a high-speed pipeline ADC, the input signal enters the first-stage MDAC and the comparator of the first-stage sub-ADC separately. Because the RC networks in these two paths differ, mismatching of the analog front-end network can easily occur. This can lead to timing mismatches between the comparator comparison signal Vin2 and the MDAC sampling signal Vin1, causing missing codes in the pipeline ADC. This issue can be resolved by properly designing the resistor values ​​in the Vin2 path and adjusting the RC networks in both paths.

[0028] However, because the input signal frequencies vary across different application scenarios, the time delay between the two signal paths varies with the input frequency. Therefore, the static RC network matching method is not suitable for all applications. Therefore, an algorithm that can adaptively perform analog front-end matching must be integrated into high-speed pipeline ADCs. Furthermore, fixed deviations, such as process variations, can lead to significant deviations in the comparator thresholds. Due to process instability and uncertainty, a trimming circuit and matching trimming algorithm must be designed for each comparator threshold.

[0029] In view of the above problems existing in the prior art, the present invention proposes a high-speed pipeline ADC calibration method and system, which will be described in detail below with reference to specific embodiments.

[0030] See also Figure 2 , Figure 2 This is a schematic diagram of the system architecture for high-speed pipeline ADC calibration in one embodiment of the present invention. The algorithm injects a pseudo-random sequence (PN) into the first-stage sub-ADC and MDAC, automatically estimates the comparator threshold deviation and ADC analog front-end network matching delay in the digital domain, and feeds back the adjustment code value to the analog circuit to achieve the automatic adjustment function. The high-speed, low-power pipeline ADC eliminates the sample-and-hold circuit and the pre-amplifier circuit in the comparator. The specific circuit structure is shown in FIG. Figure 3 The analog front-end network matching problem can be equivalent to the inconsistency between the sampling time point of the first-stage sampling capacitor and the comparison time point of the comparator in the first-stage sub-ADC. The analog front-end network matching can be achieved by adjusting the time delay of the enable signal ENN in the comparison and latching states of the dynamic comparator.

[0031] VM1 and VP1 are the comparator threshold voltages, derived from the resistor string. VM0 and VP0 are the input differential signals. Fine-tuning the comparator threshold is also performed within the comparator. After the algorithm estimates the error, it adjusts the comparator threshold via control signals S0 and S0N. The transistor size ratios for VM1 and VP1 in the comparator core circuit and the trimming circuit can be designed based on the actual trimming requirements. The entire comparator circuit compares the input voltage (VM0-VP0) with the threshold voltage (VM1-VP1) + a*(VM1-VP1) or (VP1-VM1) + a*(VP1-VM1), where a is the designed transistor size ratio for VM1 and VP1 in the comparator core circuit and the trimming circuit.

[0032] See Figure 4 , Figure 4 A flow chart of a high-speed pipeline ADC calibration method according to an embodiment of the present invention is shown in FIG. Figure 4 As shown, the calibration method includes the following steps:

[0033] In step S400, a pseudorandom sequence is simultaneously injected into the comparators of the first-stage ADC and the first-stage MDAC. The pseudorandom sequence is used to represent the sequence number of the comparator threshold corresponding to the comparator. The pseudorandom sequence can be generated based on the position and order of the comparators in the ADC and MDAC. The pseudorandom sequence can be used to locate the corresponding comparator, so as to estimate the threshold deviation for a specific comparator.

[0034] In one embodiment, a pseudo-random sequence is simultaneously injected into the comparator of the first-stage ADC and the first-stage MDAC by means of disturbance injection. The disturbance injection step includes: determining a disturbance injection weight in the digital domain according to a disturbance injection capacitor, a first-stage sampling injection capacitor, and a weight of the first-stage sampling injection capacitor; determining a corresponding disturbance injection amount according to the disturbance injection weight, and performing disturbance injection based on the disturbance injection amount.

[0035] In the analog circuit, the pseudo-random sequence (PN) is injected into the first-stage sub-ADC and MDAC simultaneously, where the disturbance injection capacitor is Cdither_n and the sampling capacitor is Cs. The weight of the first-stage sampling capacitor Cs in the digital domain is WCs, so the disturbance injection weight in the digital domain is

[0036] Wdither_n=WCs*(Cdither_n / Cs)n=1,2….

[0037] In an N-bit pipeline ADC, WCs in the first-stage n-bit sub-ADC is (2^N) / (2^n). If the disturbance injection capacitance is:

[0038] Cdither_1=1 / 2*Cs,

[0039] Cdither_2=1 / 4*Cs.

[0040] Then the disturbance injection amount WD in the digital domain is

[0041] WD1=Wdither_1+Wdither_2,

[0042] WD2=-Wdither_1-Wdither_2,

[0043] WD3 = Wdither_2,

[0044] WD4 = -Wdither_2.

[0045] Step S410 : estimating the threshold deviation of each comparator and the matching delay of the analog front-end network of the first-stage sub-ADC in the digital domain.

[0046] In one embodiment, the step of estimating the threshold deviation of the comparator in the digital domain includes: obtaining an output code value of the first-stage sub-ADC, and determining a valid data sequence in the digital domain for estimating the error based on the output code value; generating a sum sequence based on the output code value and the most significant bit of the valid data sequence; positioning the comparator based on the sum sequence and the pseudo-random sequence, and initiating threshold deviation calculation after positioning is completed to obtain the threshold deviation.

[0047] In one embodiment, the step of calculating the threshold deviation includes: using the data other than the highest bit in the valid data sequence as input for the threshold deviation calculation; when the highest bit of the valid data sequence is a first value, accumulating the data other than the highest bit; when the highest bit of the valid data sequence is a second value, accumulating the data other than the highest bit in the valid data sequence with a first preset value; generating a multi-bit data segment number based on the accumulated data; loading the data segment number through multiple registers to obtain a signed number of preset bits and sending it to a comparator, comparing it with a preset unsigned threshold, and enabling the corresponding two-bit adjustment control; converting the pseudo-random sequence into a threshold adjustment signal of a first preset bit, combining it with the corresponding adjustment enable signal, and generating an adjustment control code corresponding to each threshold, wherein each two bits in the adjustment control code control one threshold adjustment, corresponding to a positive adjustment value or a negative adjustment value respectively. Among them, the first value, the second value, the first preset value, and the first preset bit number can all be set and adjusted according to actual application requirements, and are not limited here.

[0048] Specifically, see Figure 5 , Figure 5 Figure 1 is a schematic diagram of the logic architecture for threshold deviation calculation in one embodiment of the present invention. The N-bit pipeline ADC outputs N bits of data as Data[N-1:0]. The first-stage n-bit sub-ADC outputs code values ​​as stage1[n-1:0]. Six bits of data are intercepted to obtain Data[Nn:Nn-5]. The resulting effective data for estimating the error in the digital domain (i.e., the effective data sequence) is:

[0049] D[5:0]=Data[Nn]-stage1[0]+Data[Nn-1:Nn-5]+WD[Nn:Nn-5]

[0050] Taking N=14, n=4, and a pipeline ADC with 14 comparators in the first stage as an example, we take the first-stage sub-ADC data stage1[3:0] and the highest bit D[5] of D[5:0] and pass them through the adder ADDER to obtain the data SUM[3:0] = stage1[3:0] - D[5:0] (i.e., the sum sequence). GENERATOR1 (pseudo-random sequence generator) generates Q[3:0] as a fixed sequence of 6, 7, 5, 8, 4, 9, ..., representing the order of the comparators in the circuit corresponding to the comparator thresholds ±Vref1, ±Vref2, ±Vref3, ... in the first-stage sub-ADC. These values ​​are then located and confirmed with SUM[3:0] in the INECOMP module. Once each comparator in the circuit is located, the output EQ = 1, data for REG4 begins loading, and the error calculation algorithm begins.

[0051] The last five bits of D[5:0], D[4:0], are used as input to the error calculation algorithm. When the algorithm is activated, in COUNT, when the highest bit D[5] of D[5:0] = 0 (i.e., the first value), D[4:0] is accumulated; when D[5] = 1 (i.e., the second value), (-32 + D[4:0]) is accumulated. The accumulated 17-bit data is segmented and numbered, and the numbers are output as Q[8:0]. Q[8:0] is loaded through 14 registers, and Q14[8:0] is selected as the signed number and sent to COMP1. The unsigned number B[7:0] is set to 0. When B[7:0]-128 ≥ Q14[8:0], the output D1 is 1; when B[7:0]-128 < |Q14[8:0]|, the output D0 is 0. The error value and sign of each threshold are calculated and the corresponding two-bit trim control enable is given. The comparator number generated in GENERATOR1 is converted into a 14-bit thermometer code in DEC1. After passing through REG6 and REG7, it is converted into the 28-bit threshold trim signals Q1[13:0] and Q2[13:0]. After passing through the DATAPATH module, it is converted into the trim control codes OUT0[7:0], OUT1[7:0], OUT2[7:0], and OUT3[7:0]. Each two bits controls a threshold trim value, with 10 and 01 representing positive and negative trim values, respectively.

[0052] In one embodiment, refreshing of the output code value of the first-stage sub-ADC is controlled by accumulating input data corresponding to an input signal, wherein a refresh period is determined by a multiple of a clock period of the first-stage sub-ADC. Specifically, refreshing of the output code value of the first-stage sub-ADC is controlled by accumulating input data corresponding to an input signal, wherein a refresh period is determined by a multiple of a clock period of the first-stage sub-ADC.

[0053] In an embodiment, the step of calculating the matching delay comprises: locating a corresponding comparator according to the pseudo-random sequence; determining a first sequence according to the valid data sequence of the located comparator and the corresponding data segment number; accumulating the absolute value of the negative number input of the first sequence to obtain a first accumulation result; accumulating the absolute value of the positive number input of the first sequence to obtain a second accumulation result; determining a third accumulation result according to the difference between the second accumulation result and the first accumulation result, and taking the third accumulation result as a first input sequence after a preset first delay; determining a fourth accumulation result according to the sum of the first accumulation result and the second accumulation result, and taking the data of a specified number of bits in the fourth accumulation result as a second input sequence; when the data in the second input sequence is greater than twice the data in the first input sequence, determining that there is a matching delay, enabling a first control signal; taking the fourth accumulation result as a third input sequence after a preset second delay; if the third input sequence is greater than 2 21 , determining that there is a matching delay, enabling a second control signal; taking the fourth accumulation result as last period data after delaying one period, and taking the fourth accumulation as current period data, determining an error change trend according to the last period data and the current period data, and generating a third control signal and a fourth control signal according to the error change trend; determining the jump of a state machine through the first control signal, the second control signal, the third control signal and the fourth control signal, wherein the first control signal and the second control signal enable the state machine, and the third control signal and the fourth control signal determine the jump direction of the state machine.

[0054] Specifically, please refer to Figure 6 , Figure 6 is a schematic diagram of the logic architecture of the matching delay calculation in an embodiment of the present application. The input and part of the calculation module of the multiplexing comparator threshold deviation estimation algorithm can obtain the analog front-end network matching time deviation estimation algorithm based on the LMS algorithm. The multiplexing input and calculation module can reduce the algorithm complexity, reduce the layout area and power consumption. The output fourteen-bit thermometer code Z0[13:0] of DEC1 is located to fourteen comparators, controls the corresponding HOLD0-14 enable signals in REG8, and selects the corresponding Qn[8:0] output. Among them, Qn[8:0] is the 17-bit data segment number result accumulated after D[4:0] when the highest bit D[5] of D[5:0] is 0 in the last algorithm COUNT module; when D[5] is 1, accumulate.

[0055] REG3's output, Q[3:0], is the fixed sequence 6, 7, 5, 8, 4, 9, ..., generated by GENERATOR1 in the previous algorithm. This represents the order of the comparators in the circuit corresponding to the comparator thresholds ±Vref1, ±Vref2, ±Vref3, ... in the first-stage sub-ADC. In ADDER1, when the value of Q[3:0] is n and the nth bit of Q0[13:0] is 1, a specific comparator among the 14 comparators is located. At this point, ADDER1 outputs SUM[8:0] = D[5:0] * 8 - Qn[8:0].

[0056] SUM[8:0] is fed into ADDER2 and ADDER3 for accumulation. ADDER2 accumulates the absolute value of negative inputs, while ADDER3 accumulates positive inputs. The 23-bit result of the two accumulators is fed into ADDER4 and ADDER5 for further accumulation. In ADDER4, the output of ADDER2 is used as A[22:0], and the output of ADDER3 is used as B[22:0]. The accumulated result SUM[22:0] = B[22:0] - A[22:0]. In ADDER5, the output of ADDER2 is used as B[22:0], and the output of ADDER3 is used as A[22:0]. The accumulated result SUM[23:0] = B[22:0] + A[22:0]. The output of ADDER4, SUM[22:0], is briefly delayed by register REG10 and fed into the DATAPATH_1 module as input D1[22:0]. The output of ADDER5, SUM[23:0], is fed into the DATAPATH_1 module, where SUM[23:3] is intercepted and used as input D2[23:3]. When D2[23:3] > |2*D1[22:0]|, a calculation error is detected and the circuit requires adjustment. The state machine enable signal CTRL1 is pulled high.

[0057] The data Q[23:0] from ADDER5 passes through register REG11 and is then sent to DATAPATH_2 as input D[23:0]. When D[23:0] > 2^21, a calculation error has been detected and the circuit needs to be adjusted. The state machine enable signal CTRL2 is pulled high.

[0058] Data Q[23:0] from ADDER5 passes through register REG11 and register REG12, where it is delayed by one cycle before entering ADDER6 as input B[23:0] and serving as the data for the previous cycle Tn. Data Q[23:0] from ADDER5 directly enters ADDER6 as input A[23:0] and serves as the data for the next cycle Tn+1. ADDER6 subtracts the error data from the two cycles to compare them and calculate the trend of the cumulative error. The comparison results are outputs CTRL3 and CTRL4, which determine the state machine jump direction.

[0059] CTRL1, CTRL2, CTRL3, and CTRL4 collectively determine the state machine's transitions. CTRL1 and CTRL2 enable the state machine, while CTRL3 and CTRL4 determine the state machine's transition direction. The state machine's transition direction is represented in the circuit by adjusting the positive or negative time delay of the enable signal ENN between the comparator's comparison and latch states.

[0060] In step S420 , a corresponding trimming code is generated according to the threshold deviation and the matching delay, and the trimming code is fed back to the high-speed pipeline ADC to complete calibration.

[0061] In one embodiment, the calibration method further includes providing an SPI interface for verifying the trim control code, and fixing the code via fuses after verification. Specifically, to facilitate testing and verification of the specific trim value of the comparator threshold, an SPI interface is added to the control code output portion. After the user verifies the trim control code via the SPI interface, the code can be fixed via fuses. The algorithm can also modify the segmented interval length of the 17-bit accumulated data corresponding to each segment number in the output Q[8:0] in the LOGIC DIVIDER module via SPI, thereby changing the algorithm step size and adjusting the convergence time and accuracy.

[0062] Based on the technical solution of the present invention, the PN injection value is reused to perform two error estimates simultaneously, which occupies a small analog layout area and has low power consumption; the output and part of the digital calculation module are multiplexed to improve the calculation speed and accuracy and reduce power consumption; in test mode, the feedback code value can be modified through SPI to facilitate testing; the algorithm step size can also be adjusted through SPI to change the convergence time and accuracy; the error adjustment speed is fast, the accuracy is high, and the adjustment range is large, which can adapt to different processes and application environments.

[0063] See also Figure 7 , Figure 7This is a block diagram of a calibration system for a high-speed pipelined ADC provided in one embodiment of the present invention. The calibration system includes: a pseudo-random sequence generation module 70 for simultaneously injecting a pseudo-random sequence into the comparators of the first-stage ADC and the first-stage MDAC, wherein the pseudo-random sequence is used to characterize the arrangement sequence of the comparator threshold corresponding to the comparator; an error calibration module 71 for estimating the threshold deviation of each comparator and the matching delay of the analog front-end network of the first-stage sub-ADC in the digital domain; generating a corresponding adjustment code based on the threshold deviation and the matching delay, and feeding the adjustment code back to the high-speed pipelined ADC to complete calibration.

[0064] The specific system implementation process has been described in detail in the aforementioned method embodiment and will not be repeated here.

[0065] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for calibrating a high-speed pipeline ADC, wherein the input signal of the high-speed pipeline ADC is input into a first-stage MDAC and a first-stage sub-ADC respectively, characterized in that: The calibration method comprises: Injecting a pseudo-random sequence into the comparators of the first-stage ADC and the first-stage MDAC simultaneously, wherein the pseudo-random sequence is used to represent the arrangement sequence number of the comparator corresponding to the comparator threshold; estimating the threshold deviation of each of the comparators and the matching delay of the analog front-end network of the first-stage sub-ADC in the digital domain; A corresponding trimming code is generated according to the threshold deviation and the matching delay, and the trimming code is fed back to the high-speed pipeline ADC to complete calibration.

2. The calibration method of the high-speed pipeline ADC according to claim 1, wherein: The step of estimating the threshold deviation of the comparator in the digital domain comprises: Obtaining an output code value of the first-stage sub-ADC, and determining a valid data sequence in a digital domain for estimating an error based on the output code value; Generate a sum sequence according to the output code value and the most significant bit of the valid data sequence; The comparator is positioned according to the sum sequence and the pseudo-random sequence, and threshold deviation calculation is started after positioning is completed to obtain the threshold deviation.

3. The calibration method of the high-speed pipeline ADC according to claim 1, wherein: The steps of calculating the threshold deviation include: taking the data other than the highest bit in the valid data sequence as input for threshold deviation calculation; accumulating the data other than the highest bit when the highest bit of the valid data sequence is a first value; accumulating the data other than the highest bit in the valid data sequence with a first preset value when the highest bit of the valid data sequence is a second value; generating a multi-bit data segment number based on the accumulated data; loading the data segment number through multiple registers to obtain a signed number of a preset number of bits and sending it to a comparator, comparing it with a preset unsigned threshold, and enabling the corresponding two-bit adjustment control; converting the pseudo-random sequence into a threshold adjustment signal of a first preset number of bits, and generating a adjustment control code corresponding to each threshold in combination with a corresponding adjustment enable signal, wherein each two bits in the adjustment control code control one threshold adjustment, corresponding to a positive adjustment value or a negative adjustment value respectively.

4. The high-speed pipeline ADC calibration method according to claim 2, wherein: The refreshing of the output code value of the first-stage sub-ADC is controlled by accumulating input data corresponding to the input signal, wherein the refreshing period is determined by a multiple of the clock period of the first-stage sub-ADC.

5. The calibration method for a high-speed pipeline ADC according to claim 3, wherein: The step of calculating the matching delay includes: Positioning a corresponding comparator according to the pseudo-random sequence; determining a first sequence according to a valid data sequence of the located comparator and a corresponding data segment number; Accumulating the absolute values ​​of the negative inputs of the first sequence to obtain a first accumulation result; Accumulating the absolute values ​​of the positive inputs of the first sequence to obtain a second accumulation result; Determine a third accumulated result according to the difference between the second accumulated result and the first accumulated result, and use the third accumulated result as the first input sequence after a preset first delay; determining a fourth accumulated result according to the sum of the first accumulated result and the second accumulated result, and intercepting data of a specified number of bits in the fourth accumulated result as a second input sequence; When the data in the second input sequence is greater than twice the data in the first input sequence, determining that a matching delay exists, and enabling a first control signal; The fourth accumulated result is used as the third input sequence after the preset second delay; if the third input sequence is greater than 2 21 , it is determined that there is a matching delay, and the second control signal is enabled; delaying the fourth accumulated result by one cycle as previous cycle data, and using the fourth accumulated result as current cycle data, determining an error change trend based on the previous cycle data and the current cycle data, and generating a third control signal and a fourth control signal based on the error change trend; The jump of the state machine is jointly determined by the first control signal, the second control signal, the third control signal and the fourth control signal, wherein the first control signal and the second control signal are used to enable the state machine, and the third control signal and the fourth control signal determine the jump direction of the state machine.

6. The high-speed pipeline ADC calibration method according to claim 3 or 5, characterized in that: The calibration method further includes providing an SPI interface to verify the trimming control code, and solidifying the code through a fuse after the verification is completed.

7. The high-speed pipeline ADC calibration method according to claim 6, wherein: The calibration method further includes: modifying the segment interval length of the data segment number through the SPI interface, thereby adjusting the calculation step size.

8. The high-speed pipeline ADC calibration method according to claim 1, wherein: The pseudo-random sequence is injected into the comparator of the first-stage ADC and the first-stage MDAC simultaneously by means of disturbance injection, wherein the disturbance injection step includes: Determining a disturbance injection weight in a digital domain according to the disturbance injection capacitor, the first-stage sampling injection capacitor, and the weight of the first-stage sampling injection capacitor; A corresponding disturbance injection amount is determined according to the disturbance injection weight, and disturbance injection is performed based on the disturbance injection amount.

9. A high-speed pipeline ADC calibration system, applied to the calibration of the high-speed pipeline ADC, wherein the input signal of the high-speed pipeline ADC is input into the first-stage MDAC and the first-stage sub-ADC respectively, characterized in that: The calibration system comprises: a pseudo-random sequence generating module, configured to simultaneously inject a pseudo-random sequence into the comparators of the first-stage ADC and the first-stage MDAC, wherein the pseudo-random sequence is used to represent an arrangement sequence number of the comparator corresponding to the comparator threshold; An error calibration module is configured to estimate, in the digital domain, the threshold deviation of each comparator and the matching delay of the analog front-end network of the first-stage sub-ADC; generate corresponding adjustment codes based on the threshold deviation and the matching delay; and feed the adjustment codes back to the high-speed pipeline ADC to complete calibration.

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