Formation method of semiconductor structure and semiconductor structure

Abstract

A method for forming a semiconductor structure and a semiconductor structure, the method comprising: providing a substrate including a high-voltage gate oxide region and high-voltage source and drain regions, the high-voltage source and drain regions being located at two sides of the high-voltage gate oxide region, and a shallow trench isolation structure between the high-voltage gate oxide region and the high-voltage source and drain regions; forming an isolating membrane on the surface of the preset region of the substrate, wherein the isolating membrane exposes the high-voltage gate oxide region; forming a first photoresist layer on the surface of the high-voltage gate oxide region, wherein the first photoresist layer exposes an edge region adjacent to the shallow trench isolation structure in the high-voltage gate oxide region; etching the exposed edge region in the high-voltage gate oxide region by taking the isolating film and the first photoresist layer as masks so as to reduce the height of the surface of the edge region of the high-voltage gate oxide region; and removing the first photoresist layer to expose the high-voltage gate oxide region, and forming a high-voltage device gate oxide layer on the high-voltage gate oxide region. The performance of the high-voltage device can be optimized, and the reliability of the high-voltage device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for forming a semiconductor structure and a semiconductor structure. Background Art

[0002] High-voltage (HV) semiconductor technology is specifically designed for manufacturing integrated circuits or discrete devices capable of withstanding high voltages. It is widely used in display drivers, power electronics, industrial control, and other fields. The HV-CMOS process is an extension of the traditional CMOS process to high voltage. Because the HV-CMOS process is less expensive than the BCD process, products produced using this process are more competitive in the market.

[0003] Generally, facing higher operating voltage (generally less than 40V), the gate oxide layer of the high voltage device needs to be thicker. In the prior art, when depositing the gate oxide layer of the high voltage device, the substrate of the high voltage device is easily Figure 1 The corner A shown has a sharp edge, which affects the performance of the high-voltage device and has an adverse effect on the reliability of the high-voltage device.

[0004] In view of this, a method is needed to reduce or eliminate the sharp corners at the corners of the substrate and the shallow trench isolation structure in the high voltage region to improve the performance of the high voltage device. Summary of the Invention

[0005] The technical problem solved by the present invention is to provide a method for forming a semiconductor structure and a semiconductor structure, thereby improving the performance of a high-voltage device and enhancing the reliability of the high-voltage device.

[0006] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising a high-voltage gate oxide region and a high-voltage source and drain region, the high-voltage source and drain regions being located on both sides of the high-voltage gate oxide region, and a shallow trench isolation structure being provided between the high-voltage gate oxide region and the high-voltage source and drain region; forming an isolation film on the surface of a preset area of ​​the substrate, the isolation film exposing the high-voltage gate oxide region; forming a first photoresist layer on the surface of the high-voltage gate oxide region, the first photoresist layer exposing an edge region of the high-voltage gate oxide region adjacent to the shallow trench isolation structure; using the isolation film and the first photoresist layer as masks, etching the exposed edge region of the high-voltage gate oxide region to reduce the height of the surface of the edge region of the high-voltage gate oxide region; removing the first photoresist layer to expose the high-voltage gate oxide region, and forming a high-voltage device gate oxide layer on the high-voltage gate oxide region.

[0007] Optionally, an isolation film is formed on the surface of a preset area of ​​the substrate, specifically including: forming an isolation material film on the surface of the substrate and the surface of the shallow trench isolation structure; forming a patterned second photoresist layer on the surface of the isolation material film, the second photoresist layer exposing the isolation material film on the high-voltage gate oxide region and the isolation material film on a portion of the shallow trench isolation structure adjacent to the high-voltage gate oxide region; using the second photoresist layer as a mask, etching the exposed isolation material film until the isolation material film on the high-voltage gate oxide region is removed to form the isolation film, the isolation film also exposing a portion of the surface of the shallow trench isolation structure adjacent to the high-voltage gate oxide region.

[0008] Optionally, the method for forming a first photoresist layer on the surface of the high-voltage gate oxide region includes: performing exposure and development based on the mask used when forming the second photoresist layer, forming an initial first photoresist layer on the exposed surface of the high-voltage gate oxide region and the shallow trench isolation structure, the material of one of the initial first photoresist layer and the second photoresist layer being a positive photoresist, and the material of the other of the initial first photoresist layer and the second photoresist layer being a negative photoresist; trimming the initial first photoresist layer, removing the initial first photoresist layer from the surface of the shallow trench isolation structure and the surface of the edge area of ​​the high-voltage gate oxide region adjacent to the shallow trench isolation structure, to form the first photoresist layer.

[0009] Optionally, the process of trimming the initial first photoresist layer includes a plasma etching process, the material of the initial first photoresist layer is a negative photoresist, and the material of the second photoresist layer is a positive photoresist.

[0010] Optionally, the top of the shallow trench isolation structure is raised relative to the surface of the substrate.

[0011] Optionally, the isolation film is made of silicon nitride.

[0012] Optionally, an oxidation process is performed to cause oxygen to react with the exposed substrate of the high-voltage gate oxide region to form the high-voltage device gate oxide layer.

[0013] Optionally, after forming the shallow trench isolation structure and before forming an isolation film on the surface of a preset area of ​​the substrate, the method for forming the semiconductor structure further includes: performing ion implantation on the high-voltage source and drain regions to form a high-voltage source region and a high-voltage drain region on both sides of the high-voltage gate oxide region, respectively.

[0014] Optionally, the proportion of the edge region in the high-voltage gate oxide region is in a range of 5% to 10%.

[0015] Correspondingly, the technical solution of the present invention also provides a semiconductor structure, including: a substrate, the substrate including a high-voltage gate oxide region and a high-voltage source and drain region, the high-voltage source and drain regions are located on both sides of the high-voltage gate oxide region, a shallow trench isolation structure is provided between the high-voltage gate oxide region and the high-voltage source and drain region, the high-voltage gate oxide region has an edge region adjacent to the shallow trench isolation structure, the surface of the edge region is lower than the surface of the high-voltage gate oxide region outside the edge region; an isolation film, located on the surface of the high-voltage source and drain region, and exposing the high-voltage gate oxide region; a high-voltage device gate oxide layer, covering the surface of the high-voltage gate oxide region.

[0016] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects: In the method for forming a semiconductor structure and the semiconductor structure provided by the technical solution of the present invention, an isolation film is formed on the surface of the high-voltage source and drain region, so that the isolation film exposes the high-voltage gate oxide region, and a first photoresist layer is formed on the surface of the high-voltage gate oxide region to expose the edge region adjacent to the shallow trench isolation structure in the high-voltage gate oxide region. Then, the isolation film and the first photoresist layer are used as masks to etch the exposed edge region in the high-voltage gate oxide region to reduce the surface height of the edge region. Therefore, the isolation film and the first photoresist layer can be used together as a mask. In the process of etching the exposed edge region in the high-voltage gate oxide region, the covered area is etched to prevent etching, thereby ensuring that the high-voltage source and drain region of the substrate and the edge region are not exposed. The high-voltage gate oxide region outside the region is not affected by etching. At the same time, the surface height of the edge region is reduced, so that the edge region is recessed relative to the surface of the high-voltage gate oxide region outside the edge region. Therefore, when forming the gate oxide layer of the high-voltage device, combined with the different oxidation rates in the high-voltage gate oxide region (the corner region close to the shallow trench isolation structure, that is, the edge region oxidizes slower, and the middle region oxidizes faster), the entire high-voltage gate oxide region can form a high-voltage device gate oxide layer with a relatively flat bottom, reducing or even avoiding the risk of sharp corners forming in the edge region. As a result, the probability of tip discharge in the high-voltage device is small, the risk of breakdown of the high-voltage device in the edge region is greatly reduced, and the reliability of the high-voltage device is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure; Figure 2 yes Figure 1 Scanning electron microscope photograph of area A in FIG; Figures 3 to 10 It is a schematic cross-sectional structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0018] Description of reference numerals: 10. High voltage device area; 100 - substrate; 101 - high-voltage gate oxide region; 1011 - edge region; 102 - remaining region; 1021 - low-voltage MOS tube region; 1022 - medium-voltage MOS tube region; 103 - high-voltage source and drain region; 20, 200- shallow trench isolation structure; 210- isolation structure mask layer; 300-isolating film; 310-isolating material film; 320-second photoresist layer; 400 - first photoresist layer; 410 - initial first photoresist layer; 30, 500- high voltage device gate oxide layer. DETAILED DESCRIPTION

[0019] As described in the background art, the substrate of the existing high voltage device is easily Figure 1 The corner A shown in the figure has a sharp edge problem, which causes poor reliability of high voltage devices. Figure 1 Provide specific instructions.

[0020] Figure 1 It is a schematic diagram of the cross-sectional structure of a semiconductor structure.

[0021] Please refer to Figure 1 The semiconductor structure includes a silicon substrate, a shallow trench isolation structure 20 and a high-voltage device gate oxide layer 30. The substrate includes a high-voltage device region 10, a shallow trench isolation structure 20 around the high-voltage device region 10, and a high-voltage device gate oxide layer 30 on the high-voltage device region 10.

[0022] In the above semiconductor structure, the high voltage device gate oxide layer 30 is formed by causing oxygen to undergo an oxidation reaction with the silicon substrate in the high voltage device region 10 .

[0023] However, during the oxidation process of forming the high-voltage device gate oxide layer 20, since the corner area close to the shallow trench isolation structure 20 oxidizes more slowly than the middle area, that is, the substrate at the edge of the high-voltage device area 10 is more difficult to be oxidized, the substrate at the edge of the high-voltage device area 10 will form a sharp corner (such as Figure 2 As shown in region B of FIG, high-voltage devices are prone to breakdown and other problems at this sharp corner, resulting in poor reliability of the semiconductor structure.

[0024] To solve the above technical problems, the technical solution of the present invention provides a method for forming a semiconductor structure and a semiconductor structure. By using an isolation film and a first photoresist layer as a mask, the exposed edge area in the high-voltage MOS tube area is etched to reduce the surface height of the edge area, thereby avoiding the formation of sharp corners and improving the reliability of the high-voltage device.

[0025] To make the above-mentioned objects, features, and beneficial effects of the present invention more clearly understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0026] The terms "first," "second," "third," "fourth," and the like (if any) in the description and claims of the present invention and in the drawings are used to distinguish similar objects and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate so that the embodiments of the present invention described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions; for example, a process, method, system, product, or apparatus that includes a series of steps or elements is not necessarily limited to those steps or elements explicitly listed, but may include other steps or elements that are not explicitly listed or that are inherent to such processes, methods, products, or apparatuses. In addition, directional terms such as above, below, up, down, upward, downward, left, right, and the like are used relative to the exemplary embodiments as they are shown in the figures, with an upward or upper direction being toward the top of the corresponding figure and a downward or lower direction being toward the bottom of the corresponding figure.

[0027] Figures 3 to 10 It is a schematic cross-sectional structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present invention.

[0028] Please refer to Figure 3 , providing a substrate 100.

[0029] In this embodiment, substrate 100 is a silicon substrate. In other embodiments, the substrate material may include at least one of the following materials: Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors. Alternatively, the substrate may include a silicon substrate, silicon-on-insulator (SOI), silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), or germanium-on-insulator (GeOI). The substrate size may be 6 inches, 8 inches, 12 inches, etc., without limitation.

[0030] The substrate 100 includes a high-voltage gate oxide region 101 and a high-voltage source and drain region 103 .

[0031] The high voltage source and drain regions 103 are located on both sides of the high voltage gate oxide region 101 .

[0032] Furthermore, the substrate 100 further includes: a remaining region 102 other than the high-voltage gate oxide region 101 and the high-voltage source and drain region 103 . The high-voltage source and drain region 103 is located between the high-voltage gate oxide region 101 and the remaining region 102 .

[0033] Furthermore, the remaining area 102 includes at least one of a medium-voltage device area 1022 and a low-voltage device area 1021 . Figure 3 For ease of understanding and explanation, the situation where both the medium-voltage device area 1022 and the low-voltage device area 1021 exist is illustrated.

[0034] The high-voltage gate oxide region 101 and the high-voltage source and drain region 103 are used to form a high-voltage MOS transistor device, the medium-voltage device region 1022 is used to form a medium-voltage device, and the low-voltage device region 1021 is used to form a low-voltage device.

[0035] Please refer to Figure 4 , a shallow trench isolation structure 200 is formed in the substrate 100 .

[0036] In this embodiment, the top of the shallow trench isolation structure 200 is raised relative to the surface of the substrate 100 .

[0037] In other embodiments, the shallow trench isolation structure 200 may also be flush with the surface of the substrate 100 .

[0038] The shallow trench isolation structure 200 is located between the high voltage gate oxide region 101 and the high voltage source and drain region 103 , and between the high voltage source and drain region 103 and the remaining region 102 , so as to isolate each region accordingly.

[0039] Furthermore, when the remaining area 102 includes both the medium voltage device area 1022 and the low voltage device area 1021, the shallow trench isolation structure 200 is also located between the medium voltage device area 1022 and the low voltage device area 1021. Thus, each medium voltage device area 1022 is isolated from the low voltage device area 1021.

[0040] Specifically, the method for forming the shallow trench isolation structure 200 can include: forming a patterned isolation structure mask layer 210 on the surface of the substrate 100, the isolation structure mask layer 210 exposing the substrate 100 except the high-voltage gate oxide region 101, the high-voltage source / drain region 103 and the remaining region 102; using the isolation structure mask layer 210 as a mask, etching the exposed substrate 100 to form a shallow trench (not shown in the figure) between the high-voltage gate oxide region 101 and the high-voltage source / drain region 103, between the high-voltage source / drain region 103 and the remaining region 102, and between the medium-voltage device region 1022 and the low-voltage device region 1021; forming a shallow trench isolation material layer (not shown in the figure) on the surface of the isolation structure mask layer 210 and in the shallow trench, the surface of the shallow trench isolation material layer being higher than the isolation structure mask layer 210; and grinding the shallow trench isolation material layer until the top surface of the isolation structure mask layer 210 is exposed.

[0041] The isolation structure mask layer 210 can be photoresist or a stack of photoresist and other materials. The stack of photoresist and other materials can include, in sequence, a pad silicon dioxide layer, a silicon nitride layer, and photoresist formed on the substrate 100. The silicon nitride layer serves as a stop layer for subsequent grinding of the shallow trench isolation material layer. After grinding, the silicon nitride layer and the pad silicon dioxide layer are removed to form the shallow trench isolation structure 200 protruding relative to the surface of the substrate 100. The process for grinding the shallow trench isolation material layer can be a chemical mechanical grinding process (CMP). In addition, after grinding the shallow trench isolation material layer and before subsequent steps, the isolation structure mask layer 210 is removed. The process for removing the isolation structure mask layer 210 can include a gray ash process. The thickness of the isolation structure mask layer 210 is used to form the shallow trench isolation structure 200 with the top portion protruding relative to the surface of the substrate 100.

[0042] Further, after removing the isolation structure mask layer 210, ion implantation is performed on the high-voltage source / drain region 103 to form a high-voltage source region and a high-voltage drain region (not shown in the figure) on both sides of the high-voltage gate oxide region 101, respectively.

[0043] Next, an isolation film 300 is formed on the surface of the substrate 100 in the predetermined region, i.e., on the surface of the high-voltage source / drain region 103, the remaining region 102 and the shallow trench isolation structure 200. The isolation film 300 exposes the high-voltage gate oxide region 101. The specific steps are described in detail in Figure 5 and Figure 6 .

[0044] Please refer to Figure 5 , an isolation material film 310 is formed on the surface of the substrate 100 and the surface of the shallow trench isolation structure 200.

[0045] The isolation material film 310 provides material for forming the isolation film 300 (as shown in Figure 6 ).

[0046] Furthermore, the isolation material film 310 may be formed by a deposition process, for example, a chemical vapor deposition process (CVD), a physical vapor deposition process (PVD), or an atomic layer deposition process (ALD).

[0047] Please refer to Figure 6 , a patterned second photoresist layer 320 is formed on the surface of the isolation material film 310 .

[0048] In this embodiment, the second photoresist layer 320 exposes the isolation material film 310 on the high voltage gate oxide region 101 and a portion of the isolation material film 310 on the shallow trench isolation structure 200 adjacent to the high voltage gate oxide region 101 .

[0049] Of course, in other embodiments, the second photoresist layer 320 may also only expose the isolation material film 310 on the high-voltage gate oxide region 101 .

[0050] Furthermore, the second photoresist layer 320 may be formed by coating a second photoresist material layer (not shown) on the surface of the isolation material film 310 ; and exposing and developing the second photoresist material layer to form a patterned second photoresist layer 320 .

[0051] Please continue to refer to Figure 6 Using the second photoresist layer 320 as a mask, the exposed isolation material film 310 is etched until the isolation material film 310 on the high-voltage gate oxide region 101 is removed, thereby forming an isolation film 300 .

[0052] In this embodiment, the isolation film 300 is located not only on the surface of the high-voltage source / drain region 103 and the remaining region 102, but also on the surface of the shallow trench isolation structure 200. Thus, it also protects the covered shallow trench isolation structure 200 during subsequent etching and oxidation processes. Preferably, the thickness of the isolation film 300 is 200 angstroms to 400 angstroms.

[0053] Furthermore, the material of the isolation film 300 can be silicon nitride. On the one hand, silicon nitride can form a large etching selectivity ratio with silicon during etching. Therefore, during the subsequent etching process of the exposed edge region 1011, the isolation film 300 can serve as an etch stop layer, blocking the etching of the high-voltage source and drain region 103 and the remaining region 102, and protecting the shallow trench isolation structure 200 covered by the isolation film 300, thereby reducing the damage caused by etching to the surface of the substrate 100 other than the high-voltage gate oxide region 101. On the other hand, during the subsequent oxidation process of forming the high-voltage device gate oxide layer 500, the high-voltage source and drain region 103 and the remaining region 102 can be covered to prevent oxidation of the remaining region 102.

[0054] In this embodiment, since the second photoresist layer 320 not only exposes the isolation material film 310 on the high-voltage gate oxide region 101, but also exposes the isolation material film 310 on part of the shallow trench isolation structure 200 adjacent to the high-voltage gate oxide region 101, it is better ensured that the isolation material film 310 on the high-voltage gate oxide region 101 can be completely removed, especially the removal of the isolation material film 310 on the edge area 1011 adjacent to the shallow trench isolation structure 200 in the high-voltage gate oxide region 101, so that when the edge area 1011 is subsequently etched to reduce the surface height of the edge area 1011, it is further ensured that the edge area 1011 can be well etched without being blocked by the isolation material film 310. In addition, compared with the graphic size corresponding to the isolation material film 310 exposed only on the high-voltage gate oxide region 101, the graphic size corresponding to the isolation material film 310 exposed on the high-voltage gate oxide region 101 and the portion of the shallow trench isolation structure 200 adjacent to the high-voltage gate oxide region 101 is larger. Therefore, the process difficulty of forming the graphic of the second photoresist layer 320 is also reduced, and the process window is increased.

[0055] In other embodiments, the isolation film 300 may also only expose the high-voltage gate oxide region 101 .

[0056] Furthermore, the process of etching the exposed isolation material film 310 may be a dry etching process or a wet etching process.

[0057] In one embodiment, after the exposed isolation material film 310 is etched using the second photoresist layer 320 as a mask, a cleaning step is performed.

[0058] It should be understood that, during the process of removing the isolation material film 310 on the high voltage gate oxide region 101, due to the over-etching and the above-mentioned cleaning steps, the portion of the shallow trench isolation structure 200 adjacent to the high voltage gate oxide region 101 is easily lost after the isolation material film 310 thereon is opened, thereby reducing the surface height (e.g., Figure 6 ).

[0059] Next, a first photoresist layer 400 is formed on the surface of the high voltage gate oxide region 101 . The first photoresist layer 400 exposes an edge region 1011 of the high voltage gate oxide region 101 adjacent to the shallow trench isolation structure 200 .

[0060] In this embodiment, the specific steps of forming the first photoresist layer 400 are as follows. Figure 7 and Figure 8 .

[0061] Please refer to Figure 7 , an initial first photoresist layer 410 is formed on the surface of the exposed high voltage gate oxide region 101 .

[0062] In this embodiment, since a portion of the shallow trench isolation structure 200 is also exposed, the initial first photoresist layer 410 is also formed on the exposed surface of the shallow trench isolation structure 200 .

[0063] The method for forming the initial first photoresist layer 410 can be: coating a first photoresist material layer (not marked in the figure) on the surface of the isolation film 300, the surface of the high-voltage gate oxide region 101 and the surface of the exposed portion of the shallow trench isolation structure 200; exposing and developing the first photoresist material layer to form a patterned initial first photoresist layer 410.

[0064] Furthermore, the material of one of the initial first photoresist layer 410 and the second photoresist layer 320 is a positive photoresist, and the material of the other of the initial first photoresist layer 410 and the second photoresist layer 320 is a negative photoresist. For example, the initial first photoresist layer 410 is a negative photoresist, and the second photoresist layer 320 is a positive photoresist; or, the initial first photoresist layer 410 is a positive photoresist, and the second photoresist layer 320 is a negative photoresist.

[0065] By using positive and negative photoresists for the initial first photoresist layer 410 and the second photoresist layer 320, respectively, photoresist layers with complementary patterns can be formed using the same photomask. In other words, based on the use of positive and negative photoresists for the initial first photoresist layer 410 and the second photoresist layer 320, respectively, exposure and development can be performed based on the photomask used to form the second photoresist layer 320, thereby forming the initial first photoresist layer 410 on the exposed surfaces of the high-voltage gate oxide region 101 and the shallow trench isolation structure 200. This reduces the number of photomasks and lowers process costs.

[0066] Of course, in other embodiments, the initial first photoresist layer 410 and the second photoresist layer 320 may also use the same photoresist, and the patterned initial first photoresist layer 410 and the second photoresist layer 320 are respectively formed based on two masks.

[0067] Please refer to Figure 8 , the initial first photoresist layer 410 is trimmed, and the initial first photoresist layer 410 on the surface of the edge region 1011 adjacent to the shallow trench isolation structure 200 in the high-voltage gate oxide region 101 is removed to form a first photoresist layer 400 exposing the edge region 1011 adjacent to the shallow trench isolation structure 200 in the high-voltage gate oxide region 101.

[0068] In this embodiment, since the initial first photoresist layer 410 is also formed on the surface of the exposed shallow trench isolation structure 200, the initial first photoresist layer 410 on the surface of the shallow trench isolation structure 200 is removed during the process of trimming the initial first photoresist layer 410 to form the first photoresist layer 400.

[0069] Specifically, the initial first photoresist layer 410 may be trimmed by using a plasma etching process.

[0070] Please refer to Figure 9 Using the isolation film 300 and the first photoresist layer 400 as masks, the exposed edge region 1011 in the high-voltage gate oxide region 101 is etched to reduce the surface height of the edge region 1011 .

[0071] Specifically, the height to which the surface of the edge region 1011 needs to be lowered can be determined based on an empirical value. This empirical value can be obtained based on the height difference generated at the warped corner structure of the gate oxide layer formed on the high-voltage gate oxide region 101 without lowering the surface height of the edge region 1011 in the high-voltage gate oxide region 101. Accordingly, the parameters of the etching process for etching the exposed edge region 1011 in the high-voltage gate oxide region 101 can be adjusted based on the height to which the surface of the edge region 1011 needs to be lowered.

[0072] Furthermore, the process of etching the exposed edge region 1011 in the high-voltage gate oxide region 101 may be a dry etching process or a wet etching process.

[0073] Please refer to Figure 10 After etching the exposed edge region 1011 in the high-voltage gate oxide region 101 , the first photoresist layer 400 is removed to expose the high-voltage gate oxide region 101 .

[0074] Furthermore, the process of removing the first photoresist layer 400 may be an ashing process.

[0075] Please continue to refer to Figure 10 After removing the first photoresist layer 400 , a high-voltage device gate oxide layer 500 is formed on the high-voltage gate oxide region 101 .

[0076] Specifically, since the gate oxide layer 500 of the high-voltage device has a very high density requirement, a thermal oxidation process is used to form the gate oxide layer 500 on the high-voltage gate oxide region 101 .

[0077] Furthermore, the thickness of the high voltage device gate oxide layer 500 is in the range of 800 angstroms to 1100 angstroms.

[0078] Furthermore, the proportion of the etched edge region 1011 in the high-voltage gate oxide region 101 ranges from 5% to 10%. Because the high-voltage gate oxide region 101 is located between the shallow trench isolation structures 200, the edge region 1011 of the high-voltage gate oxide region 101 is close to the corner region of the shallow trench isolation structure 200. Therefore, the speed of thermal oxidation to form the gate oxide layer 500 is slower than that of other regions of the high-voltage gate oxide region 101. As a result, the substrate 100 in the edge region 1011 of the high-voltage gate oxide region 101 protrudes relative to other regions of the high-voltage gate oxide region 101, resulting in sharp corners in the edge region 1011 of the high-voltage gate oxide region 101. Therefore, at different process nodes, the first photoresist layer 400 can be used to expose 5%-10% of the corner area of ​​the high-voltage gate oxide region 101 close to the shallow trench isolation structure 200 (i.e., the edge area 1011 of the high-voltage gate oxide region 101), and the substrate height of the edge area 1011 is made lower than that of other areas of the high-voltage gate oxide region 101, thereby reducing the height difference caused by the different thermal oxidation rates of different areas, and better ensuring the subsequent formation of the high-voltage device gate oxide layer 500 ( Figure 10 There are no sharp corners in the bottom substrate of the edge area of ​​​​the device (as shown in ), thereby improving the performance and reliability of the device.

[0079] In the embodiment of the present invention, an isolation film 300 is formed on the surface of the high-voltage source / drain region 103 and the remaining region 102, exposing the high-voltage gate oxide region 101 through the isolation film 300. A first photoresist layer 400 is then formed on the surface of the high-voltage gate oxide region 101, exposing the edge region 1011 of the high-voltage gate oxide region 101 adjacent to the shallow trench isolation structure 200. Subsequently, the exposed edge region 1011 of the high-voltage gate oxide region 101 is etched using the isolation film 300 and the first photoresist layer 400 as a mask to lower the surface height of the edge region 1011. Therefore, the isolation film 300 (which serves as an etch stop layer) and the first photoresist layer 400 can serve together as a mask to provide an etch stop for the covered area during the etching process of the exposed edge region 1011 of the high-voltage gate oxide region 101, thereby ensuring that the high-voltage source / drain region 103, the remaining region 102, and the high-voltage gate oxide region 101 outside the edge region 1011 of the substrate 100 are not affected by the etching. At the same time, the height of the surface of the edge region 1011 is reduced, so that the edge region 1011 is recessed relative to the surface of the high-voltage gate oxide region 101 outside the edge region 1011. Therefore, when forming the high-voltage device gate oxide layer 500, the different oxidation rates in the high-voltage gate oxide region 101 (the corner regions near the shallow trench isolation structure, i.e., the edge regions, oxidize more slowly, while the central regions oxidize more quickly) are combined to form a high-voltage device gate oxide layer 500 with a relatively flat bottom throughout the entire high-voltage gate oxide region 101, reducing or even eliminating the risk of sharp corners forming in the edge region 1011. As a result, the probability of high-voltage device tip discharge is reduced, significantly reducing the risk of high-voltage device breakdown in the edge region 1011 and improving the reliability of the high-voltage device.

[0080] The isolation film 300 also serves as an isolation layer during the formation of the high-voltage device gate oxide layer 500, preventing the area covered by the isolation film from being affected by the deposited high-voltage device gate oxide layer 500 material or from being oxidized by the oxidation process. Furthermore, since the first photoresist layer 400 is formed on the surface of the high-voltage gate oxide region 101 after the isolation film 300 is formed, the formation of both can be achieved through simple process steps.

[0081] It should be understood that since the high voltage device gate oxide layer 500 is formed by oxidation reaction of oxygen with the substrate 100 of the exposed high voltage gate oxide region 101 , the top substrate 100 in the high voltage gate oxide region 101 will be converted into a part of the high voltage device gate oxide layer 500 .

[0082] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above-mentioned formation method, please continue to refer to Figure 10 , including: a substrate 100, an isolation film 300 and a high-voltage device gate oxide layer 500.

[0083] The substrate 100 includes a high-voltage gate oxide region 101 and a high-voltage source and drain region 103. The high-voltage source and drain regions 103 are located on both sides of the high-voltage gate oxide region 101. A shallow trench isolation structure 200 is provided between the high-voltage gate oxide region 101 and the high-voltage source and drain region 103. The high-voltage gate oxide region 101 includes an edge region 1011 adjacent to the shallow trench isolation structure 200. The surface of the edge region 1011 is lower than the surface of the high-voltage gate oxide region 101 outside the edge region 1011.

[0084] The isolation film 300 is located on the surface of the high-voltage source and drain region 103 and exposes the high-voltage gate oxide region 101 .

[0085] The high-voltage device gate oxide layer 500 covers the surface of the high-voltage gate oxide region 101 .

[0086] Furthermore, substrate 100 also includes a remaining region 102 outside of the high-voltage gate oxide region 101 and the high-voltage source and drain region 103. The high-voltage source and drain regions 103 are located on both sides of the high-voltage gate oxide region 101 and between the high-voltage gate oxide region 101 and the remaining region 102. The remaining region 102 includes at least one of a medium-voltage device region 1022 and a low-voltage device region 1021. The devices are isolated from each other by shallow trench isolation structures 200. Accordingly, an isolation film 300 is also located on the surface of the remaining region 102.

[0087] The materials, formation process, working principle, specific implementation and beneficial effects involved in the semiconductor structure in the embodiment of the present invention can all be found in the method for forming the semiconductor structure in the embodiment of the present invention, and will not be repeated here.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be based on the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a high-voltage gate oxide region and a high-voltage source and drain region, the high-voltage source and drain regions being located on both sides of the high-voltage gate oxide region, and a shallow trench isolation structure being formed between the high-voltage gate oxide region and the high-voltage source and drain regions; forming an isolation film on a surface of a predetermined area of ​​the substrate, wherein the isolation film exposes the high-voltage gate oxide region; forming a first photoresist layer on the surface of the high voltage gate oxide region, wherein the first photoresist layer exposes an edge region of the high voltage gate oxide region adjacent to the shallow trench isolation structure; Using the isolation film and the first photoresist layer as masks, etching the exposed edge region of the high-voltage gate oxide region to reduce the height of the surface of the edge region of the high-voltage gate oxide region; The first photoresist layer is removed to expose the high-voltage gate oxide region, and a high-voltage device gate oxide layer is formed on the high-voltage gate oxide region.

2. The method for forming a semiconductor structure according to claim 1, wherein: Forming an isolation film on a surface of a predetermined area of ​​the substrate specifically includes: forming an isolation material film on the surface of the substrate and the surface of the shallow trench isolation structure; forming a patterned second photoresist layer on the surface of the isolation material film, wherein the second photoresist layer exposes the isolation material film on the high-voltage gate oxide region and the isolation material film on a portion of the shallow trench isolation structure adjacent to the high-voltage gate oxide region; The second photoresist layer is used as a mask to etch the exposed isolation material film until the isolation material film on the high voltage gate oxide region is removed to form the isolation film, which also exposes a portion of the shallow trench isolation structure surface adjacent to the high voltage gate oxide region.

3. The method for forming a semiconductor structure according to claim 2, wherein: The method for forming a first photoresist layer on the surface of the high-voltage gate oxide region includes: Performing exposure and development based on the photomask used when forming the second photoresist layer, forming an initial first photoresist layer on the exposed surface of the high-voltage gate oxide region and the shallow trench isolation structure, wherein the material of one of the initial first photoresist layer and the second photoresist layer is a positive photoresist, and the material of the other of the initial first photoresist layer and the second photoresist layer is a negative photoresist; The initial first photoresist layer is trimmed to remove the surface of the shallow trench isolation structure and the surface of the edge region of the high-voltage gate oxide region adjacent to the shallow trench isolation structure to form the first photoresist layer.

4. The method for forming a semiconductor structure according to claim 3, wherein: The process of trimming the initial first photoresist layer includes a plasma etching process. The material of the initial first photoresist layer is a negative photoresist, and the material of the second photoresist layer is a positive photoresist.

5. The method for forming a semiconductor structure according to claim 1, wherein: The top of the shallow trench isolation structure is raised relative to the surface of the substrate.

6. The method for forming a semiconductor structure according to claim 1, wherein: The isolation film is made of silicon nitride.

7. The method for forming a semiconductor structure according to claim 1, wherein: Through an oxidation process, oxygen is caused to undergo an oxidation reaction with the exposed substrate of the high-voltage gate oxide region to form the high-voltage device gate oxide layer.

8. The method for forming a semiconductor structure according to claim 1, wherein: After forming the shallow trench isolation structure and before forming an isolation film on the surface of a preset area of ​​the substrate, the method for forming the semiconductor structure further includes: performing ion implantation on the high-voltage source and drain regions to form a high-voltage source region and a high-voltage drain region on both sides of the high-voltage gate oxide region, respectively.

9. The method for forming a semiconductor structure according to claim 1, wherein: The proportion of the edge region in the high-voltage gate oxide region ranges from 5% to 10%.

10. A semiconductor structure, characterized in that include: A substrate comprising a high-voltage gate oxide region and a high-voltage source and drain region, wherein the high-voltage source and drain regions are located on both sides of the high-voltage gate oxide region, a shallow trench isolation structure is provided between the high-voltage gate oxide region and the high-voltage source and drain region, and the high-voltage gate oxide region comprises an edge region adjacent to the shallow trench isolation structure, wherein a surface of the edge region is lower than a surface of the high-voltage gate oxide region outside the edge region; an isolation film, located on the surface of the high-voltage source and drain region and exposing the high-voltage gate oxide region; The high-voltage device gate oxide layer covers the surface of the high-voltage gate oxide region.

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